Texas Instruments ADS1x7xEVM-PDK Manuel utilisateur

SBAU197A–February 2012–Revised January 2016

ADS1x7xEVM-PDK

User's Guide

SBAU197A–February 2012–Revised January 2016

ADS1x7xEVM-PDK

This user's guide describes the characteristics, operation, and use of the ADS1x7xEVM-PDK. These

evaluation module kits (EVM-PDK) are an evaluation system for the ADS1278, a 24-bit, 8 channel, delta-

sigma analog-to-digital converter (ADC), the ADS1178, a 16-bit version of the ADS1278 and the ADS1274

and ADS1174, which are 4 channel versions of the ADS1278 and ADS1178, respectively. The EVM-PDK

allows evaluation of all aspects of the ADS1x7x devices.

This document includes an EVM QuickStart, hardware and software details, bill of materials, and

schematic.

The following related documents are available through the Texas Instruments web site at

http://www.ti.com.

Table 1. EVM-Compatible Device Data Sheets

Device Literature Number Device Literature Number

ADS1278 SBAS367 OPA1632 SBOS286

ADS1274 SBAS367 SN74LVC2G157 SCES207

ADS1178 SBAS373 TPS73018 SBVS054

ADS1174 SBAS373 TPS65131 SLVS493

REF5025 SBOS410 PCA9535 SCPS129

OPA2350 SBOS099

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ADS1x7xEVM-PDK

Contents

1 EVM Overview ............................................................................................................... 3

2 Quick Start.................................................................................................................... 4

3 Quick Reference ............................................................................................................. 6

4 Using the ADS1178EVM-PDK/ADS1278EVM-PDK Plug-in ADCPro................................................. 7

5 ADS1278EVM Hardware Details......................................................................................... 11

6 Schematic and Bill of Materials........................................................................................... 16

List of Figures

1 ADS1x7xEVM Default Jumper Locations................................................................................. 4

2 Channel Enable.............................................................................................................. 8

3 Clock Settings and Mode................................................................................................... 9

List of Tables

1 EVM-Compatible Device Data Sheets.................................................................................... 1

2 Default Jumper/Switch Configuration ..................................................................................... 4

3 Critical Connections ......................................................................................................... 6

4 Operating Modes: Clock Frequency..................................................................................... 10

5 Jumper and Switch Descriptions......................................................................................... 11

6 J3: Primary Analog Interface Pinout..................................................................................... 13

7 J1: Secondary Analog Interface Pinout ................................................................................. 13

8 J4, Serial Interface Header ............................................................................................... 14

9 J2, DOUTx Header......................................................................................................... 15

10 J5 Configuration: Power-Supply Input................................................................................... 15

11 ADS1x7xEVM Bill of Materials ........................................................................................... 16

Trademarks

ADCPro is a trademark of Texas Instruments.

I2C is a trademark of NXP Semiconductors, Inc.

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EVM Overview

SBAU197A–February 2012–Revised January 2016

ADS1x7xEVM-PDK

1 EVM Overview

The ADS1x7xEVM-PDK is an evaluation module kit that includes an EVM, MMB0 motherboard and

software. As a standalone PCB, the ADS1x7xEVM is useful for prototyping designs and firmware. It can

be connected to any modular EVM system interface card.

1.1 Features

ADS1x7xEVM Features:

• Contains all support circuitry needed for the ADS1178/ADS1278/ADS1174/ADS1274

• Voltage reference options: external or onboard

• Clock options: External clock source (PLL or DSP supplied) or 27MHz onboard crystal oscillator

• GPIO access

• Compatible with the TI Modular EVM System

ADS1x7xEVM-PDK includes the ADS1x7xEVM board with the DSP-based MMB0 motherboard, that can

be used with ADCPro™ to quickly evaluate the device.

This manual covers the operation of the ADS1x7xEVM-PDK. Throughout this document, the abbreviation

EVM and the term evaluation module are synonymous with the

ADS1178EVM/ADS1278EVM/ADS1174EVM/ADS1274EVM. For clarity of reading, this manual will refer

only to the ADS1278EVM or ADS1x7xEVM-PDK, but operation of the EVM and kit for the

ADS1178/ADS1274/ASD1174 is identical, unless otherwise noted.

Quick Start

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2 Quick Start

This section provides a QuickStart guide to quickly begin evaluating the ADS1x7xEVM with ADCPro.

2.1 Default Jumper/Switch Configuration

Figure 1 shows the jumpers found on the EVM and the respective factory default conditions for each.

Figure 1. ADS1x7xEVM Default Jumper Locations

Table 2 lists the jumpers and switches and the factory default conditions.

Table 2. Default Jumper/Switch Configuration

Switch Default Position Switch Description

S1 All OFF (Down) Power-down channel DIP switches (Hardware control)

S2 All OFF (Down) Mode, Format, and CLKDIV DIP switches (Hardware

control)

S3 INT (Right) On-board voltage reference selected

S4 Header connected to converter (Left) Channel 4 header connected to converter (not

buffered)

S5 Header connected to converter (Left) Channel 3 header connected to converter (not

buffered)

S6 [1-2], [4-5], [7-8], [10-11] Jumpers installed to select FS serial interface format

S7 Header connected to converter (Left) Channel 2 header connected to converter (not

buffered)

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Quick Start

SBAU197A–February 2012–Revised January 2016

ADS1x7xEVM-PDK

Table 2. Default Jumper/Switch Configuration (continued)

Switch Default Position Switch Description

S8 Header connected to converter (Left) Channel 1 header connected to converter (not

buffered)

Jumper

JP1 Open FSX NOT connected to SYNC/DRDY

JP2 Short FSR connected to SYNC/DRDY

JP3 Short Input buffer op-amps are powered-down

JP4 Short Clock source selection using software control

JP5 Short External clock source selected (invalid since using

software control)

2.2 ADS1x7xEVM-PDK Operation

To prepare to evaluate the ADS1278 with the ADS1x7xEVM-PDK, complete the following steps:

1. Verify the jumpers on the ADS1x7xEVM are as shown in Figure 1 (note that these settings are the

factory-configured settings for the EVM).

2. Using ADCPro HW/SW Installation Manual, verify the MMB0 jumpers are in the default position and

install ADCPro and ADS1278EVM plug-in software. Complete hardware connection and driver

installation as part of ADCPro HW/SW Installation Manual using the below settings.

• MMB0 J13A →Open

• MMB0 J13B →Short

• No additional power connections are required

3. Plug the ADS1278EVM onto the MMB0 (if not already connected). The female portion of J3, J4 and J5

on the EVM align with male connectors J10, J4, and J5 respectively on the MMB0.

4. Connect power to the MMB0 board. If power is supplied from an AC adapter (not included), ensure that

it satisfies the following requirements:

• Output voltage: 5.5 VDC to 15 VDC

• Maximum output current: ≥500 mA

• Output connector: barrel plug (positive center), 2.5-mm I.D. x 5.5-mm O.D. (9-mm insertion depth)

• Complies with applicable regional safety standards

CAUTION

Do not misalign the pins when plugging the ADS1278EVM into the MMB0.

Check the pin alignment of J3, J4, and J5 carefully before applying power to

the PDK.

Quick Reference

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3 Quick Reference

Table 3 provides a quick summary of the connections required for operation of the EVM as a standalone

Table 3. Critical Connections

Function Header/Pin Pin Name Description

Interface

SCLK J4.3 CLKX SCLK

DIN J4.11 DX Data In

DOUT J4.13 DR Data Out

Interrupt J4.15 INT DRDY/FSYNC

Power 1.8V J5.7 +1.8VD Digital supply

3.3V J5.9 +3.3VD Digital supply

5.0V J5.3 +5VA Analog supply

Analog Inputs Channels 1-4 J3.1-8 Analog Inputs

Channels 5-8 J1.3-10 Analog Inputs (ADS1178 and

ADS1278 only)

CAUTION

When using the EVM as part of the ADS1278EVM-PDK, the DIP switches S1

and S2 must all be switched so that they are down, toward the center of the

board. Failure to do so may damage the EVM.

3.1 Analog Inputs

The analog inputs for the ADS1278EVM are connected to J1 and J3. Channels 1-4 connect to J3 and

provisions are provided to buffer these signals before being connected to the converter. Switches S4, S5,

S7, and S8 control whether the buffered or unbuffered signal is connected to the ADS1278. Channels 5-8

connect to J1 and have an RC filter available to filter the input before connecting to the converter.

Channels 5-8 do not have provisions for buffering the signal.

3.2 Digital Control

The digital control signals can be applied directly to J4 (top or bottom side).

3.3 Power Supply

The ADS1278EVM requires power rails as follows:

• 5.0V analog supply - supplied by MMB0 motherboard via J13B

• 3.3V digital supply - supplied by MMB0 motherboard

• 1.8V digital supply - supplied by MMB0 motherboard

3.4 Voltage Reference

The ADS1278EVM has two options for the reference voltage. Switch S3 selects the reference voltage

from either the buffered REF5025 or a external reference voltage that is connected to the reference pins

of J3 (J3.18 = REFN and J3.20 = REFP).

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Using the ADS1178EVM-PDK/ADS1278EVM-PDK Plug-in ADCPro

SBAU197A–February 2012–Revised January 2016

ADS1x7xEVM-PDK

4 Using the ADS1178EVM-PDK/ADS1278EVM-PDK Plug-in ADCPro

The ADS1278EVM-PDK plug-in for ADCPro provides complete control over all settings of the ADS1278. It

consists of a tabbed interface (see Figure 2) with different functions available on different tabs. The tabs

are:

• Channel Enable

• Settings

• About

The user can adjust the ADS1178EVM/ADS1278EVM settings when not acquiring data. During

acquisition, all controls are disabled and settings may not be changed. When a setting is changed on the

ADS1178EVM/ADS1278EVM plug-in, the setting immediately updates on the board.

Settings on the ADS1178EVM/ADS1278EVM correspond to settings described in the ADS1278 product

data sheet product data sheet.

4.1 Top Level Controls

You can adjust the ADS1278EVM settings when you are not acquiring data. During acquisition, all

controls are disabled and settings may not be changed.

The effective data rate of the ADS1278 depends upon settings of the Clock Freq and Operating Mode.

The Data Rate indicator in the upper right corner of the plug-in interface (see Figure 2) is always visible

and updates whenever a setting changes that affects the data rate.

4.2 Channel Enable Tab

The ADS1278 can acquire data from one to eight channels simultaneously. The Channel Enable tab (as

shown in Figure 2) provides the control to power on or off each channel.

Using the ADS1178EVM-PDK/ADS1278EVM-PDK Plug-in ADCPro

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Figure 2. Channel Enable

The Master (All) Enable control allows for the selection of channels to convert. Manual Control allows

channel enable control via CH1 through CH8 selector switches. All Channels Enabled and All Channels

Disabled turn all the selector switches either ON or OFF.

4.3 Settings Tab

The Settings tab allows for the selection of the various clock frequencies, operating mode, data format,

and other settings.

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Using the ADS1178EVM-PDK/ADS1278EVM-PDK Plug-in ADCPro

SBAU197A–February 2012–Revised January 2016

ADS1x7xEVM-PDK

Figure 3. Clock Settings and Mode

The Clock Source control selects the input clock source for the ADS1278. The clock can be selected

from the MMB0 PLL, an External source, or use the On-board oscillator.

The Modulator Frequency indicator shows the ADS1278 modulator frequency based on the clock

source.

The Clock Frequency control allows the user to input the desired clock frequency when the PLL clock

source is selected. Once the frequency is entered, the software finds the closest frequency for the PLL to

synthesize (and which is within the maximum allowable frequency for the mode selected). This clock

frequency is configured in the PLL and overwrites the user entered value in the Clock Frequency

indicator.

The Operating Mode control allows selection of the converter operating mode: High-Speed,High-

Resolution,Low-Power, or Low-Speed.

The CLKDIV control can be set to 0or 1.

The Data Output Format allows selection of the data output formats. For the ADS1278EVM software, the

formats are limited to the Frame-Sync, TDM Format. The available options select whether the software

collects data for all channels Fixed Mode or only channels that are powered up Dynamic Mode.

The Vref control allows the user to input the current Vref value being used by the data converter. This

control does not change the actual reference voltage, but is required for the software to process the data

correctly for display.

The maximum clock frequency is shown for the different converter options in Table 4.

Using the ADS1178EVM-PDK/ADS1278EVM-PDK Plug-in ADCPro

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Table 4. Operating Modes: Clock Frequency

Operating Mode CLKDIV Frequency (MHz)

High-Speed 1 32.768

High-Resolution 1 27

Low-Power 1 27

Low-Power 0 13.5

Low-Speed 1 27

Low-Speed 0 5.4

4.4 About Tab

The About tab provides information on the EVM hardware and software versions.

Plug-in Version is software version of ADCPro plug-in.

Firmware Version is firmware version loaded and running on the processor.

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