Texas Instruments TMS320DM646x Manuel utilisateur

TMS320DM646x DMSoCEthernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO)Module

User's Guide

Literature Number: SPRUEQ6December 2007

2 SPRUEQ6 – December 2007Submit Documentation Feedback

Contents

Preface .............................................................................................................................. 101 Introduction .............................................................................................................. 121.1 Purpose of the Peripheral ..................................................................................... 121.2 Features ......................................................................................................... 121.3 Functional Block Diagram ..................................................................................... 131.4 Industry Standard(s) Compliance Statement ............................................................... 142 Architecture .............................................................................................................. 142.1 Clock Control .................................................................................................... 142.2 Memory Map .................................................................................................... 152.3 Signal Descriptions ............................................................................................. 152.4 Ethernet Protocol Overview ................................................................................... 192.5 Programming Interface ......................................................................................... 202.6 EMAC Control Module ......................................................................................... 312.7 MDIO Module ................................................................................................... 342.8 EMAC Module ................................................................................................... 382.9 Media Independent Interface (MII) ........................................................................... 412.10 Packet Receive Operation ..................................................................................... 452.11 Packet Transmit Operation .................................................................................... 502.12 Receive and Transmit Latency ............................................................................... 502.13 Transfer Node Priority .......................................................................................... 512.14 Reset Considerations .......................................................................................... 512.15 Initialization ...................................................................................................... 522.16 Interrupt Support ................................................................................................ 562.17 Power Management ............................................................................................ 602.18 Emulation Considerations ..................................................................................... 603 EMAC Control Module Registers ................................................................................. 613.1 EMAC Control Module Identification and Version Register (CMIDVER) ................................ 613.2 EMAC Control Module Software Reset Register (CMSOFTRESET) .................................... 623.3 EMAC Control Module Emulation Control Register (CMEMCONTROL) ................................ 623.4 EMAC Control Module Interrupt Control Register (CMINTCTRL) ........................................ 633.5 EMAC Control Module Receive Threshold Interrupt Enable Register(CMRXTHRESHINTEN) ....................................................................................... 643.6 EMAC Control Module Receive Interrupt Enable Register (CMRXINTEN) ............................. 643.7 EMAC Control Module Transmit Interrupt Enable Register (CMTXINTEN) ............................. 653.8 EMAC Control Module Miscellaneous Interrupt Enable Register (CMMISCINTEN) ................... 663.9 EMAC Control Module Receive Threshold Interrupt Status Register(CMRXTHRESHINTSTAT) .................................................................................... 673.10 EMAC Control Module Receive Interrupt Status Register (CMRXINTSTAT) ........................... 673.11 EMAC Control Module Transmit Interrupt Status Register (CMTXINTSTAT) .......................... 683.12 EMAC Control Module Miscellaneous Interrupt Status Register (EWMISCSTAT) .................... 693.13 EMAC Control Module Receive Interrupts per Millisecond Register (CMRXINTMAX) ................ 703.14 EMAC Control Module Transmit Interrupts per Millisecond Register (CMTXINTMAX) ............... 704 MDIO Registers ......................................................................................................... 714.1 MDIO Version Register (VERSION) ......................................................................... 714.2 MDIO Control Register (CONTROL) ......................................................................... 72

SPRUEQ6 – December 2007 Table of Contents 3Submit Documentation Feedback

4.3 PHY Acknowledge Status Register (ALIVE) ................................................................ 734.4 PHY Link Status Register (LINK) ............................................................................. 734.5 MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW) ............................ 744.6 MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED) .......................... 754.7 MDIO User Command Complete Interrupt (Unmasked) Register (USERINTRAW) ................... 764.8 MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED) ................. 774.9 MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET) ................ 784.10 MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR) .......... 794.11 MDIO User Access Register 0 (USERACCESS0) ......................................................... 804.12 MDIO User PHY Select Register 0 (USERPHYSEL0) .................................................... 814.13 MDIO User Access Register 1 (USERACCESS1) ......................................................... 824.14 MDIO User PHY Select Register 1 (USERPHYSEL1) .................................................... 835 Ethernet Media Access Controller (EMAC) Registers ..................................................... 845.1 Transmit Identification and Version Register (TXIDVER) ................................................. 875.2 Transmit Control Register (TXCONTROL) .................................................................. 875.3 Transmit Teardown Register (TXTEARDOWN) ............................................................ 885.4 Receive Identification and Version Register (RXIDVER) .................................................. 895.5 Receive Control Register (RXCONTROL) .................................................................. 895.6 Receive Teardown Register (RXTEARDOWN) ............................................................. 905.7 Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW) .................................... 915.8 Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED) ................................... 925.9 Transmit Interrupt Mask Set Register (TXINTMASKSET) ................................................ 935.10 Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR) .......................................... 945.11 MAC Input Vector Register (MACINVECTOR) ............................................................. 955.12 MAC End Of Interrupt Vector Register (MACEOIVECTOR) .............................................. 955.13 Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW) ..................................... 965.14 Receive Interrupt Status (Masked) Register (RXINTSTATMASKED) ................................... 975.15 Receive Interrupt Mask Set Register (RXINTMASKSET) ................................................. 985.16 Receive Interrupt Mask Clear Register (RXINTMASKCLEAR) ........................................... 995.17 MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW) ..................................... 1005.18 MAC Interrupt Status (Masked) Register (MACINTSTATMASKED) ................................... 1005.19 MAC Interrupt Mask Set Register (MACINTMASKSET) ................................................. 1015.20 MAC Interrupt Mask Clear Register (MACINTMASKCLEAR) ........................................... 1015.21 Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) .......... 1025.22 Receive Unicast Enable Set Register (RXUNICASTSET) ............................................... 1055.23 Receive Unicast Clear Register (RXUNICASTCLEAR) .................................................. 1065.24 Receive Maximum Length Register (RXMAXLEN) ....................................................... 1075.25 Receive Buffer Offset Register (RXBUFFEROFFSET) .................................................. 1075.26 Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH) .................. 1085.27 Receive Channel 0-7 Flow Control Threshold Register (RX nFLOWTHRESH) ....................... 1085.28 Receive Channel 0-7 Free Buffer Count Register (RX nFREEBUFFER) .............................. 1095.29 MAC Control Register (MACCONTROL) .................................................................. 1105.30 MAC Status Register (MACSTATUS) ...................................................................... 1125.31 Emulation Control Register (EMCONTROL) .............................................................. 1145.32 FIFO Control Register (FIFOCONTROL) .................................................................. 1145.33 MAC Configuration Register (MACCONFIG) .............................................................. 1155.34 Soft Reset Register (SOFTRESET) ........................................................................ 1155.35 MAC Source Address Low Bytes Register (MACSRCADDRLO) ....................................... 116

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5.36 MAC Source Address High Bytes Register (MACSRCADDRHI) ....................................... 1165.37 MAC Hash Address Register 1 (MACHASH1) ............................................................ 1175.38 MAC Hash Address Register 2 (MACHASH2) ............................................................ 1175.39 Back Off Test Register (BOFFTEST) ....................................................................... 1185.40 Transmit Pacing Algorithm Test Register (TPACETEST) ............................................... 1185.41 Receive Pause Timer Register (RXPAUSE) .............................................................. 1195.42 Transmit Pause Timer Register (TXPAUSE) .............................................................. 1195.43 MAC Address Low Bytes Register (MACADDRLO) ...................................................... 1205.44 MAC Address High Bytes Register (MACADDRHI) ...................................................... 1215.45 MAC Index Register (MACINDEX) ......................................................................... 1215.46 Transmit Channel 0-7 DMA Head Descriptor Pointer Register (TX nHDP) ............................ 1225.47 Receive Channel 0-7 DMA Head Descriptor Pointer Register (RX nHDP) ............................ 1225.48 Transmit Channel 0-7 Completion Pointer Register (TX nCP) ........................................... 1235.49 Receive Channel 0-7 Completion Pointer Register (RX nCP) ........................................... 1235.50 Network Statistics Registers ................................................................................. 124Appendix A Glossary ...................................................................................................... 133

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List of Figures

1 EMAC and MDIO Block Diagram ........................................................................................ 132 Ethernet Configuration—MII Connections .............................................................................. 153 Ethernet Configuration—GMII Connections ............................................................................ 174 Ethernet Frame Format .................................................................................................... 195 Basic Descriptor Format ................................................................................................... 206 Typical Descriptor Linked List ............................................................................................ 217 Transmit Buffer Descriptor Format ....................................................................................... 248 Receive Buffer Descriptor Format ........................................................................................ 279 EMAC Control Module Block Diagram .................................................................................. 3110 MDIO Module Block Diagram ............................................................................................. 3411 EMAC Module Block Diagram ............................................................................................ 3812 EMAC Control Module Interrupt Logic Diagram ........................................................................ 5613 EMAC Control Module Identification and Version Register (CMIDVER) ............................................ 6114 EMAC Control Module Software Reset Register (CMSOFTRESET) ................................................ 6215 EMAC Control Module Emulation Control Register (CMEMCONTROL) ............................................ 6216 EMAC Control Module Interrupt Control Register (CMINTCTRL) ................................................... 6317 EMAC Control Module Receive Threshold Interrupt Enable Register (CMRXTHRESHINTEN) ................. 6418 EMAC Control Module Receive Interrupt Enable Register (CMRXINTEN) ......................................... 6419 EMAC Control Module Transmit Interrupt Enable Register (CMTXINTEN) ........................................ 6520 EMAC Control Module Miscellaneous Interrupt Enable Register (CMMISCINTEN) .............................. 6621 EMAC Control Module Receive Threshold Interrupt Status Register (CMRXTHRESHINTSTAT) .............. 6722 EMAC Control Module Receive Interrupt Status Register (CMRXINTSTAT) ...................................... 6723 EMAC Control Module Transmit Interrupt Status Register (CMTXINTSTAT) ...................................... 6824 EMAC Control Module Miscellaneous Interrupt Status Register (CMMISCINTSTAT) ............................ 6925 EMAC Control Module Receive Interrupts per Millisecond Register (CMRXINTMAX) ............................ 7026 EMAC Control Module Transmit Interrupts per Millisecond Register (CMTXINTMAX) ........................... 7027 MDIO Version Register (VERSION) ..................................................................................... 7128 MDIO Control Register (CONTROL) ..................................................................................... 7229 PHY Acknowledge Status Register (ALIVE) ............................................................................ 7330 PHY Link Status Register (LINK) ......................................................................................... 7331 MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW) ........................................ 7432 MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED) ...................................... 7533 MDIO User Command Complete Interrupt (Unmasked) Register (USERINTRAW) ............................... 7634 MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED) ............................. 7735 MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET) ........................... 7836 MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR) ..................... 7937 MDIO User Access Register 0 (USERACCESS0) ..................................................................... 8038 MDIO User PHY Select Register 0 (USERPHYSEL0) ................................................................ 8139 MDIO User Access Register 1 (USERACCESS1) ..................................................................... 8240 MDIO User PHY Select Register 1 (USERPHYSEL1) ................................................................ 8341 Transmit Identification and Version Register (TXIDVER) ............................................................. 8742 Transmit Control Register (TXCONTROL) .............................................................................. 8743 Transmit Teardown Register (TXTEARDOWN) ........................................................................ 8844 Receive Identification and Version Register (RXIDVER) ............................................................. 8945 Receive Control Register (RXCONTROL) .............................................................................. 8946 Receive Teardown Register (RXTEARDOWN) ........................................................................ 9047 Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW) ................................................ 9148 Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED) .............................................. 9249 Transmit Interrupt Mask Set Register (TXINTMASKSET) ............................................................ 9350 Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR) ...................................................... 9451 MAC Input Vector Register (MACINVECTOR) ......................................................................... 9552 MAC End Of Interrupt Vector Register (MACEOIVECTOR) .......................................................... 95

6List of Figures SPRUEQ6 – December 2007Submit Documentation Feedback

53 Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW) ................................................ 9654 Receive Interrupt Status (Masked) Register (RXINTSTATMASKED) ............................................... 9755 Receive Interrupt Mask Set Register (RXINTMASKSET) ............................................................. 9856 Receive Interrupt Mask Clear Register (RXINTMASKCLEAR) ...................................................... 9957 MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW) ................................................ 10058 MAC Interrupt Status (Masked) Register (MACINTSTATMASKED) ............................................... 10059 MAC Interrupt Mask Set Register (MACINTMASKSET) ............................................................. 10160 MAC Interrupt Mask Clear Register (MACINTMASKCLEAR) ...................................................... 10161 Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) ...................... 10262 Receive Unicast Enable Set Register (RXUNICASTSET) .......................................................... 10563 Receive Unicast Clear Register (RXUNICASTCLEAR) ............................................................. 10664 Receive Maximum Length Register (RXMAXLEN) ................................................................... 10765 Receive Buffer Offset Register (RXBUFFEROFFSET) .............................................................. 10766 Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH) .............................. 10867 Receive Channel nFlow Control Threshold Register (RX nFLOWTHRESH) ..................................... 10868 Receive Channel nFree Buffer Count Register (RX nFREEBUFFER) ............................................ 10969 MAC Control Register (MACCONTROL) .............................................................................. 11070 MAC Status Register (MACSTATUS) .................................................................................. 11271 Emulation Control Register (EMCONTROL) .......................................................................... 11472 FIFO Control Register (FIFOCONTROL) .............................................................................. 11473 MAC Configuration Register (MACCONFIG) ......................................................................... 11574 Soft Reset Register (SOFTRESET) .................................................................................... 11575 MAC Source Address Low Bytes Register (MACSRCADDRLO)................................................... 11676 MAC Source Address High Bytes Register (MACSRCADDRHI) ................................................... 11677 MAC Hash Address Register 1 (MACHASH1) ........................................................................ 11778 MAC Hash Address Register 2 (MACHASH2) ........................................................................ 11779 Back Off Random Number Generator Test Register (BOFFTEST) ................................................ 11880 Transmit Pacing Algorithm Test Register (TPACETEST) ........................................................... 11881 Receive Pause Timer Register (RXPAUSE) .......................................................................... 11982 Transmit Pause Timer Register (TXPAUSE) .......................................................................... 11983 MAC Address Low Bytes Register (MACADDRLO) .................................................................. 12084 MAC Address High Bytes Register (MACADDRHI) .................................................................. 12185 MAC Index Register (MACINDEX) ..................................................................................... 12186 Transmit Channel nDMA Head Descriptor Pointer Register (TX nHDP) .......................................... 12287 Receive Channel nDMA Head Descriptor Pointer Register (RX nHDP) .......................................... 12288 Transmit Channel nCompletion Pointer Register (TX nCP) ......................................................... 12389 Receive Channel nCompletion Pointer Register (RX nCP) ......................................................... 12390 Statistics Register ......................................................................................................... 124

SPRUEQ6 – December 2007 List of Figures 7Submit Documentation Feedback

List of Tables

1 EMAC and MDIO Signals for MII Interface ............................................................................. 162 EMAC and MDIO Signals for GMII Interface ........................................................................... 173 Ethernet Frame Description ............................................................................................... 194 Basic Descriptor Description .............................................................................................. 215 EMAC Control Module Interrupts ......................................................................................... 326 Receive Frame Treatment Summary .................................................................................... 487 Middle of Frame Overrun Treatment .................................................................................... 498 Emulation Control .......................................................................................................... 609 EMAC Control Module Registers ......................................................................................... 6110 EMAC Control Module Identification and Version Register (CMIDVER) Field Descriptions ..................... 6111 EMAC Control Module Software Reset Register (CMSOFTRESET) Field Descriptions ......................... 6212 EMAC Control Module Emulation Control Register (CMEMCONTROL) Field Descriptions ..................... 6213 EMAC Control Module Interrupt Control Register (CMINTCTRL) Field Descriptions ............................. 6314 EMAC Control Module Receive Threshold Interrupt Enable Register (CMRXTHRESHINTEN) FieldDescriptions ................................................................................................................. 6415 EMAC Control Module Receive Interrupt Enable Register (CMRXINTEN) Field Descriptions .................. 6416 EMAC Control Module Transmit Interrupt Enable Register (CMTXINTEN) Field Descriptions .................. 6517 EMAC Control Module Miscellaneous Interrupt Enable Register (CMMISCINTEN) Field Descriptions ........ 6618 EMAC Control Module Receive Threshold Interrupt Status Register (CMRXTHRESHINTSTAT) FieldDescriptions ................................................................................................................. 6719 EMAC Control Module Receive Interrupt Status Register (CMRXINTSTAT) Field Descriptions ................ 6720 EMAC Control Module Transmit Interrupt Status Register (CMTXINTSTAT) Field Descriptions ................ 6821 EMAC Control Module Miscellaneous Interrupt Status Register (CMMISCINTSTAT) Field Descriptions ...... 6922 EMAC Control Module Receive Interrupts per Millisecond Register (CMRXINTMAX) Field Descriptions ..... 7023 EMAC Control Module Transmit Interrupts per Millisecond Register (CMTXINTMAX) Field Descriptions ..... 7024 Management Data Input/Output (MDIO) Registers .................................................................... 7125 MDIO Version Register (VERSION) Field Descriptions ............................................................... 7126 MDIO Control Register (CONTROL) Field Descriptions .............................................................. 7227 PHY Acknowledge Status Register (ALIVE) Field Descriptions ..................................................... 7328 PHY Link Status Register (LINK) Field Descriptions .................................................................. 7329 MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW) Field Descriptions ................. 7430 MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED) Field Descriptions ................ 7531 MDIO User Command Complete Interrupt (Unmasked) Register (USERINTRAW) Field Descriptions ........ 7632 MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED) Field Descriptions ....... 7733 MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET) Field Descriptions ..... 7834 MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR) FieldDescriptions ................................................................................................................. 7935 MDIO User Access Register 0 (USERACCESS0) Field Descriptions ............................................... 8036 MDIO User PHY Select Register 0 (USERPHYSEL0) Field Descriptions .......................................... 8137 MDIO User Access Register 1 (USERACCESS1) Field Descriptions ............................................... 8238 MDIO User PHY Select Register 1 (USERPHYSEL1) Field Descriptions .......................................... 8339 Ethernet Media Access Controller (EMAC) Registers ................................................................. 8440 Transmit Identification and Version Register (TXIDVER) Field Descriptions ....................................... 8741 Transmit Control Register (TXCONTROL) Field Descriptions ....................................................... 8742 Transmit Teardown Register (TXTEARDOWN) Field Descriptions.................................................. 8843 Receive Identification and Version Register (RXIDVER) Field Descriptions ....................................... 8944 Receive Control Register (RXCONTROL) Field Descriptions ........................................................ 8945 Receive Teardown Register (RXTEARDOWN) Field Descriptions .................................................. 9046 Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW) Field Descriptions .......................... 9147 Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED) Field Descriptions ........................ 92

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48 Transmit Interrupt Mask Set Register (TXINTMASKSET) Field Descriptions ...................................... 9349 Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR) Field Descriptions ................................ 9450 MAC Input Vector Register (MACINVECTOR) Field Descriptions ................................................... 9551 MAC End Of Interrupt Vector Register (MACEOIVECTOR) Field Descriptions ................................... 9552 Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW) Field Descriptions .......................... 9653 Receive Interrupt Status (Masked) Register (RXINTSTATMASKED) Field Descriptions......................... 9754 Receive Interrupt Mask Set Register (RXINTMASKSET) Field Descriptions ...................................... 9855 Receive Interrupt Mask Clear Register (RXINTMASKCLEAR) Field Descriptions ................................ 9956 MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW) Field Descriptions .......................... 10057 MAC Interrupt Status (Masked) Register (MACINTSTATMASKED) Field Descriptions......................... 10058 MAC Interrupt Mask Set Register (MACINTMASKSET) Field Descriptions ...................................... 10159 MAC Interrupt Mask Clear Register (MACINTMASKCLEAR) Field Descriptions ................................ 10160 Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) Field Descriptions 10261 Receive Unicast Enable Set Register (RXUNICASTSET) Field Descriptions .................................... 10562 Receive Unicast Clear Register (RXUNICASTCLEAR) Field Descriptions ....................................... 10663 Receive Maximum Length Register (RXMAXLEN) Field Descriptions ............................................ 10764 Receive Buffer Offset Register (RXBUFFEROFFSET) Field Descriptions ........................................ 10765 Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH) Field Descriptions ....... 10866 Receive Channel nFlow Control Threshold Register (RX nFLOWTHRESH) Field Descriptions ............... 10867 Receive Channel nFree Buffer Count Register (RX nFREEBUFFER) Field Descriptions ...................... 10968 MAC Control Register (MACCONTROL) Field Descriptions ........................................................ 11069 MAC Status Register (MACSTATUS) Field Descriptions ........................................................... 11270 Emulation Control Register (EMCONTROL) Field Descriptions .................................................... 11471 FIFO Control Register (FIFOCONTROL) Field Descriptions........................................................ 11472 MAC Configuration Register (MACCONFIG) Field Descriptions ................................................... 11573 Soft Reset Register (SOFTRESET) Field Descriptions .............................................................. 11574 MAC Source Address Low Bytes Register (MACSRCADDRLO) Field Descriptions ............................ 11675 MAC Source Address High Bytes Register (MACSRCADDRHI) Field Descriptions............................. 11676 MAC Hash Address Register 1 (MACHASH1) Field Descriptions ................................................. 11777 MAC Hash Address Register 2 (MACHASH2) Field Descriptions ................................................. 11778 Back Off Test Register (BOFFTEST) Field Descriptions ............................................................ 11879 Transmit Pacing Algorithm Test Register (TPACETEST) Field Descriptions ..................................... 11880 Receive Pause Timer Register (RXPAUSE) Field Descriptions .................................................... 11981 Transmit Pause Timer Register (TXPAUSE) Field Descriptions ................................................... 11982 MAC Address Low Bytes Register (MACADDRLO) Field Descriptions ........................................... 12083 MAC Address High Bytes Register (MACADDRHI) Field Descriptions ............................................ 12184 MAC Index Register (MACINDEX) Field Descriptions ............................................................... 12185 Transmit Channel nDMA Head Descriptor Pointer Register (TX nHDP) Field Descriptions .................... 12286 Receive Channel nDMA Head Descriptor Pointer Register (RX nHDP) Field Descriptions .................... 12287 Transmit Channel nCompletion Pointer Register (TX nCP) Field Descriptions .................................. 12388 Receive Channel nCompletion Pointer Register (RX nCP) Field Descriptions ................................... 123A-1 Physical Layer Definitions ............................................................................................... 134

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PrefaceSPRUEQ6 – December 2007

Read This First

About This Manual

This document provides a functional description of the Ethernet Media Access Controller (EMAC) andphysical layer (PHY) device Management Data Input/Output (MDIO) module integrated in theTMS320DM646x Digital Media System-on-Chip. Included are the features of the EMAC and MDIOmodules, a discussion of their architecture and operation, how these modules connect to the outsideworld, and the registers description for each module.

Notational Conventions

This document uses the following conventions.•Hexadecimal numbers are shown with the suffix h. For example, the following number is 40hexadecimal (decimal 64): 40h.•Registers in this document are shown in figures and described in tables.– Each register figure shows a rectangle divided into fields that represent the fields of the register.Each field is labeled with its bit name, its beginning and ending bit numbers above, and itsread/write properties below. A legend explains the notation used for the properties.– Reserved bits in a register figure designate a bit that is used for future device expansion.

Related Documentation From Texas InstrumentsThe following documents describe the TMS320DM646x Digital Media System-on-Chip (DMSoC). Copiesof these documents are available on the Internet at www.ti.com .Tip: Enter the literature number in thesearch box provided at www.ti.com.

The current documentation that describes the DM646x DMSoC, related peripherals, and other technicalcollateral, is available in the C6000 DSP product folder at: www.ti.com/c6000 .

SPRUEP8 —TMS320DM646x DMSoC DSP Subsystem Reference Guide. Describes the digital signalprocessor (DSP) subsystem in the TMS320DM646x Digital Media System-on-Chip (DMSoC).

SPRUEP9 —TMS320DM646x DMSoC ARM Subsystem Reference Guide. Describes the ARMsubsystem in the TMS320DM646x Digital Media System-on-Chip (DMSoC). The ARM subsystem isdesigned to give the ARM926EJ-S (ARM9) master control of the device. In general, the ARM isresponsible for configuration and control of the device; including the DSP subsystem and a majorityof the peripherals and external memories.

SPRUEQ0 —TMS320DM646x DMSoC Peripherals Overview Reference Guide. Provides an overviewand briefly describes the peripherals available on the TMS320DM646x Digital MediaSystem-on-Chip (DMSoC).

SPRAA84 —TMS320C64x to TMS320C64x+ CPU Migration Guide. Describes migrating from theTexas Instruments TMS320C64x digital signal processor (DSP) to the TMS320C64x+ DSP. Theobjective of this document is to indicate differences between the two cores. Functionality in thedevices that is identical is not included.

SPRU732 —TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide. Describes the CPUarchitecture, pipeline, instruction set, and interrupts for the TMS320C64x and TMS320C64x+ digitalsignal processors (DSPs) of the TMS320C6000 DSP family. The C64x/C64x+ DSP generationcomprises fixed-point devices in the C6000 DSP platform. The C64x+ DSP is an enhancement ofthe C64x DSP with added functionality and an expanded instruction set.

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