STMicroelectronics STEVAL-IME008V1 Manuel utilisateur

For further information contact your local STMicroelectronics sales office.

August 2015 DocID026791 Rev 2 1/19

STEVAL-IME008V1

STHV749 Ultrasound Pulser IC evaluation board

Data brief

Features

•4-channel outputs: high voltage and low

voltage BNC connectors

•Load simulator using signal equivalent circuits

•Possibility to set up own load simulator

•16 preset waveforms

•USB connector to connect STM32 with PC and

supply power to it

•4 MB serial Flash memory to host FPGA code

and waveforms

•Memory expansion connector to add external

serial Flash

•Connectors to supply high voltage and low

voltage to the STHV749 output stage

•LEDs to monitor the power management stage

•Human machine interface to select, start and

stop the generation of the preset waveforms

•25 LEDs to monitor board behavior

•RoHS compliant

Description

The STEVAL-IME008V1 is a product evaluation

board designed around the STHV749 4-channel

7-level high voltage pulser, a state-of-the-art

device designed for ultrasound imaging

applications.

The output waveforms can be displayed directly

on an oscilloscope by connecting the scope probe

to the relative BNCs. 16 preset waveforms are

available to test the HV pulser under varying

conditions.

www.st.com

Schematic diagrams STEVAL-IME008V1

2/19 DocID026791 Rev 2

1 Schematic diagrams

Figure 1. STEVAL-IME008V1 circuit schematic (1 of 16)

DATAOUT0

DATAOUT1

DATAOUT2

DATAOUT3

DATAOUT4

DATAOUT5

DATAOUT6

DATAOUT7

DATAOUT8

DATAOUT9

DATAOUT10

DATAOUT11

DATAOUT[0:15]

MCU_FPGA_GPIO[0:7]

DATAOUT12

DATAOUT13

HVPCW

DVDD VDDP HVP0

HVMCWVDDM HVM0

DVDD VDDP VDDM HVP0 HVP1 HVPCW HVM0 HVM1 HVMCW

HVM1

HVP1

FPGA_BLK

FPGA

THSD_EN

FPGA_SPI_CCLK

FPGA_SPI_MOSI

FPGA_SPI_MISO1

FPGA_SPI_MISO2

FPGA_SPI_MISO3

FPGA_SPI_SEL

+VFPGA_CORE_1V2

+VFPGA_IO_3V3

DATAOUT[0:15]

MCU_FPGA_GPIO[0:7]

MCU_FPGA_PROG

MCU_FPGA_INIT_B

MCU_FPGA_MODE1

FPGA_MCU_DONE

MCU_FPGA_OSC_EN

FPGA_MCU_AWAKE

MCU_FPGA_SUSPEND

BOARD_POWER_BLK

BOARD_POWER

HVP0

DVDD

VDDP

VDDM

HVM0

+VFPGA_CORE_1V2

+VFPGA_IO_3V3

FLASH_3V3

USB_DISCONNECT

USB_DM

USB_DP

MCU_3V3

HVPCW

HVMCW

HVP1

HVM1

STM32_FLASH_BLK

STM32_FLASH

FLASH_C

FLASH_DQ0

FLASH_nS

FLASH_DQ2

FLASH_DQ3

FLASH_DQ1

USB_DISCONNECT

USB_DM

USB_DP

MCU_FPGA_PROG

MCU_FPGA_INIT_B

MCU_FPGA_MODE1

FPGA_MCU_DONE

MCU_FPGA_OSC_EN

FPGA_MCU_AWAKE

MCU_FPGA_SUSPEND

FLASH_3V3

MCU_3V3

FPGA_GPIO[0:7]

STHV749_BLK

STHV749

DVDD

VDDP

VDDM

IN1_0

IN1_1

IN4_0

IN3_1

IN4_1

THSD_EN

IN2_0

IN3_0

IN2_1

HVM_CW

HVP_CW

HVP1

IN2_2

IN3_2

HVM0

IN4_2

HVM1

IN1_2

HVP0

SEL

GSPG30072014DI1135

DocID026791 Rev 2 3/19

STEVAL-IME008V1 Schematic diagrams

Figure 2. STEVAL-IME008V1 circuit schematic (2 of 16)

SOT23-5L

C7 Details:

Digikey (445-4998-2-ND) - TDK (C1005X5R0J105K)

Package 0402

USB

C8 Details:

DigiKey (478-2552-2-ND) - AVX (TACL225M006XTA)

Package 0603

SOTT323-6L

RS (515-1995)

Molex (54819-0572)

Kingbright KP2012SURC

RS: 466-3829

Farnell: 8529930

LED 0805

USB ON

USBDP

USBDM

USB_DISCONNECT

USBDM

USBDP

USB_3V3

USB_DISCONNECT

USB_DM

USB_DP

USB_5V

4.7nF

2.2uF 6.3V

R90 56R

CN1

USB_miniB

VBUS

4ID nc

5GND

6SHELL

7SHELL

8SHELL

9SHELL

D26

RED

D2 D3

USBUF02W6

Grd

3.3V

D4 6

C11

33nF

1uF

VIN

LDS3985M33R

GND

INH

4BYPS

VOUT

GSPG30072014DI1140

Schematic diagrams STEVAL-IME008V1

4/19 DocID026791 Rev 2

Figure 3. STEVAL-IME008V1 circuit schematic (3 of 16)

3.3V Power Management

J4 Details

Phoenix Contact (Mfg Code MPT 0.5/2-2.54)

RS (220-4260)

C12 and C13 Detail

TDK (C1608X5R0J475K) - Digikey (445-5178-2-ND)

Dimension 0603 - EIA 1608

C14 Detail

TDK (C2012X7R1A106K) - DIGIKEY (445-6857-2-ND)

Dimension 0805 - EIA 2012

L1 Detail

TDK (VLF4012AT-2R2M1R5) - RS (614-3147)

NOT ASSEMBLY

MCU

FPGA

3V3 Connector

3V3

SW1 Details:

SW1

RS 711-8329

KNITTER-SWITCH (MMS228T)

USB_3V3

EXT_3V3

MCU_3V3

+VFPGA_IO_3V3

+VFPGA_CORE_1V2

FLASH_3V3FLASH_3V3

EXT_3V3 DVDD

D27

RED

L1 2.2uH

C12

4u7

6.3V

MMS228T

2COM_1a 7

COM_1b

3ON_2a 6

ON_2b

1ON_1a 8

ON_1b

4nc 5

ST1S12xx

Vin

FB/VoEN

2GND

SW 3

C13

4u7

6.3V

R124

C14

10u

10V

R125 56

J41

1 2

D28

RED

SM2T3V3A

GSPG30072014DI1150

DocID026791 Rev 2 5/19

STEVAL-IME008V1 Schematic diagrams

Figure 4. STEVAL-IME008V1 circuit schematic (4 of 16)

STHV800 Power Management

MKDS 1.5/2-5.08)

J2 Details

RS 2X(193-0564)

Phoenix Contact

(Mfg Code

C1, C2, C9, C10, C15, C16 Details:

GND_POWER

Digikey (445-5217-2-ND) - TDK (CKG57NX7S2A226M)

Package 6.5mm x 5.5 mm

C4, C5, C6 Details:

Digikey (445-1436-2-ND) - TDK (C3225X5R1C226M)

Package 1210 - EIA 3225

DVDD

VDDP

GND

HVPCW

HVP1

HVP0

GND

VDDM

HVMCW

HVM1

HVM0

GND

LOW POWER- HIGH VOLTAGE + HIGH VOLTAGE

J1 Details

RS 2X(193-0564)

Phoenix Contact

(Mfg Code

MKDS 1.5/2-5.08)

J3 Details

RS 2X(193-0564)

Phoenix Contact

(Mfg Code

HVPCW

HVP0

DVDD

VDDP

VDDM

HVP1

HVMCW

HVM0

HVM1

HVPCW

HVP0

DVDD

VDDP

VDDM

HVMCW

HVM0

HVP1

HVM1

GND_POWER

MKDS 1.5/2-5.08)

GND_POWER

GND_POWER GND_SHIELD

100V

22000n 100V

R123

100V

22000n 100V

J2 LV

16V

22000n 16V

C79

100V

22000n 100V

16V

22000n 16V

C78

100V

22000n 100V

C10

100V

22000n 100V

16V

22000n 16V

22000n 100V

100V

J3 HVM

J1 HVP

GSPG30072014DI1155

Schematic diagrams STEVAL-IME008V1

6/19 DocID026791 Rev 2

Figure 5. STEVAL-IME008V1 circuit schematic (5 of 16)

Jumper J5 is used to control I/O pullups during FPGA configuration.

Diff. pair

Open (default) to float I/O output during FPGA configuration.

Set jumper 1:2 to enable I/O pullups during FPGA configuration.

Diff. pair

C16 and C17 Details:

TDK (C2012X7R1A106K) - DIGIKEY (445-6857-2-ND)

Dimension 0805 - EIA 2012

Jumpers J35, J36 and J37 are used to set dataout output state.

Configure J35 and J36 to setup outputs idle state as follows:

NOT ASSEMBLY

THESE JUMPERS

HSWAPEN

Open J37 (default) to connect FPGA outputs

Close J37 to disconnect outputs (High-Z)

00 - (J35 and J36 open) --> High-Z (default)

01 - (J35 closed and J36 open) --> Clamp/HVR_SW

11 - (J35 and J36 closed) --> High-Z

10 - (J35 open and J36 closed) --> Clamp

IDLE STATE

HEADER 17X2

STHV748 I/O CONNECTOR

FPGA DISCONNECT

DATAOUT0

DATAOUT1

DATAOUT2

DATAOUT3

DATAOUT4

DATAOUT5

DATAOUT6

DATAOUT7

DATAOUT8

DATAOUT9

DATAOUT10

DATAOUT11

DATAOUT12

DATAOUT13

DATAOUT14

DATAOUT15

DATAOUT[0:15]

HSWAPEN

THSD_EN

DATAOUT11

THSD_EN

DATAOUT0

DATAOUT2

DATAOUT4

DATAOUT6

DATAOUT8

DATAOUT10

DATAOUT12

DATAOUT14

DATAOUT1 DATAOUT3

DATAOUT5

DATAOUT7

DATAOUT9

DATAOUT13

DATAOUT15

HI_Z

IDLE_STATE1

IDLE_STATE0

THSD_EN

DATAOUT[0:15]

+VFPGA_IO_3V3

R122

10K 0402

JUMPER

C15

100n 0402

C16

10uF 10V 0805

J35

C17

10uF 10V 0805

J37

1 2

R120

10K 0402

U4A

FPGA - Bank 0

XC6SLX16-2CSG324C

C11

D11

A10

C10

A11

B11

F10

G11

A12

B12

E11

F11

C12

D12

A13

C13

E12

F12

A14

B14

E13

F13

A15

C15

C14

D14

A16

B16

10K 0402

R121

10K 0402

C18

100n 0402

J36

1 2

IO_0_L01N_VREF

IO_0_L01P_HSWAPEN

IO_0_L02N

IO_0_L02P

IO_0_L03N

IO_0_L03P

IO_0_L04N

IO_0_L04P

IO_0_L05N

IO_0_L05P

IO_0_L06N

IO_0_L06P

IO_0_L07N

IO_0_L07P

IO_0_L08N_VREF

IO_0_L08P

IO_0_L09N

IO_0_L09P

IO_0_L10N

IO_0_L10P

IO_0_L11N

IO_0_L11P

IO_0_L32N

IO_0_L32P

IO_0_L33N

IO_0_L33P

IO_0_L34N_GCLK18

IO_0_L34P_GCLK19

IO_0_L35N_GCLK16

IO_0_L35P_GCLK17

IO_0_L36N_GCLK14

IO_0_L36P_GCLK15

IO_0_L37N_GCLK12

IO_0_L37P_GCLK13

IO_0_L38N_VREF

IO_0_L38P

IO_0_L39N

IO_0_L39P

IO_0_L40N

IO_0_L40P

IO_0_L41N

IO_0_L41P

IO_0_L42N

IO_0_L42P

IO_0_L47N

IO_0_L47P

IO_0_L50N

IO_0_L50P

IO_0_L51N

IO_0_L51P

IO_0_L62N_VREF

IO_0_L62P

IO_0_L63N_SCP6

IO_0_L63P_SCP7

IO_0_L64N_SCP4

IO_0_L64P_SCP5

IO_0_L65N_SCP2

IO_0_L65P_SCP3

IO_0_L66N_SCP0

IO_0_L66P_SCP1

GSPG30072014DI1200

DocID026791 Rev 2 7/19

STEVAL-IME008V1 Schematic diagrams

Figure 6. STEVAL-IME008V1 circuit schematic (6 of 16)

NOT ASSEMBLY

FPGA USER I/O

STOP_PB

FPGA_RESET

CTRL_LED1

CTRL_LED0

SEL_PROG_PB

FPGA_CLK_66MHZ

START_PB

FPGA_DOUT_BUSY

FPGA_AWAKE

FPGA_USER_IO_10

FPGA_USER_IO_11

FPGA_USER_IO_12

FPGA_USER_IO_13

FPGA_USER_IO_14

FPGA_USER_IO_15

CTRL_LED3

CTRL_LED2

FPGA_PMOD1_P2

FPGA_PMOD1_P1

FPGA_PMOD1_P4

FPGA_PMOD1_P3

FPGA_PMOD1_P8

FPGA_PMOD1_P7

FPGA_PMOD1_P10

FPGA_PMOD1_P9

FPGA_PMOD2_P2

FPGA_PMOD2_P1

FPGA_PMOD2_P4

FPGA_PMOD2_P3

FPGA_PMOD2_P8

FPGA_PMOD2_P7

FPGA_PMOD2_P10

FPGA_PMOD2_P9

FPGA_USER_IO_0

FPGA_USER_IO_1

FPGA_USER_IO_2

FPGA_USER_IO_3

FPGA_USER_IO_4

FPGA_USER_IO_5

FPGA_USER_IO_6

FPGA_USER_IO_7

FPGA_USER_IO_8

FPGA_USER_IO_9

FPGA_MCU_AWAKE

TP1

TEST POINT

HEADER 16X2

U4B

FPGA - Bank 1

XC6SLX16-2CSG324C

F16

F15

C18

C17

G14

F14

D18

D17

G13

H12

E18

E16

K13

K12

F18

F17

H14

H13

H16

H15

G18

G16

K14

J13

L13

L12

K16

K15

L16

L15

H18

H17

J18

J16

K18

K17

L18

L17

M18

M16

N18

N17

P18

P17

N16

N15

T18

T17

U18

U17

N14

M14

M13

L14

P16

P15

IO_1_L01N_A24_VREF

IO_1_L01P_A25

IO_1_L29N_A22_M1A14

IO_1_L29P_A23_M1A13

IO_1_L30N_A20_M1A11

IO_1_L30P_A21_M1RESET

IO_1_L31N_A18_M1A12

IO_1_L31P_A19_M1CKE

IO_1_L32N_A16_M1A9

IO_1_L32P_A17_M1A8

IO_1_L33N_A14_M1A4

IO_1_L33P_A15_M1A10

IO_1_L34N_A12_M1BA2

IO_1_L34P_A13_M1WE

IO_1_L35N_A10_M1A2

IO_1_L35P_A11_M1A7

IO_1_L36N_A8_M1BA1

IO_1_L36P_A9_M1BA0

IO_1_L37N_A6_M1A1

IO_1_L37P_A7_M1A0

IO_1_L38N_A4_M1CLKN

IO_1_L38P_A5_M1CLK

IO_1_L39N_M1ODT

IO_1_L39P_M1A3

IO_1_L40N_GCLK10_M1A6

IO_1_L40P_GCLK11_M1A5

IO_1_L41N_GCLK8_M1CASN

IO_1_L41P_GCLK9_IRDY1_M1RASN

IO_1_L42N_GCLK6_TRDY1_M1LDM

IO_1_L42P_GCLK7_M1UDM

IO_1_L43N_GCLK4_M1DQ5

IO_1_L43P_GCLK5_M1DQ4

IO_1_L44N_A2_M1DQ7

IO_1_L44P_A3_M1DQ6

IO_1_L45N_A0_M1LDQSN

IO_1_L45P_A1_M1LDQS

IO_1_L46N_FOE_B_M1DQ3

IO_1_L46P_FCS_B_M1DQ2

IO_1_L47N_LDC_M1DQ1

IO_1_L47P_FWE_B_M1DQ0

IO_1_L48N_M1DQ9

IO_1_L48P_HDC_M1DQ8

IO_1_L49N_M1DQ11

IO_1_L49P_M1DQ10

IO_1_L50N_M1UDQSN

IO_1_L50P_M1UDQS

IO_1_L51N_M1DQ13

IO_1_L51P_M1DQ12

IO_1_L52N_M1DQ15

IO_1_L52P_M1DQ14

IO_1_L53N_VREF

IO_1_L53P

IO_1_L61N

IO_1_L61P

IO_1_L74N_DOUT_BUSY

IO_1_L74P_AWAKE

GSPG30072014DI1205

Schematic diagrams STEVAL-IME008V1

8/19 DocID026791 Rev 2

Figure 7. STEVAL-IME008V1 circuit schematic (7 of 16)

Place R7 (1%) close to the clock

source DS1088LU-66 device

PERIPHERRAL MODULE (PMOD)

66MHZ EXTERNAL OSCILLATOR

BACKUP OF U5

NOT ASSEMBLY

C26, C27, C30 and C31 Detail

TDK (C2012X7R1A106K) - DIGIKEY (445-6857-2-ND)

Dimension 0805 - EIA 2012

PMOD2

PMOD1

66MHZ OSC

When using backup oscillator X1,

R126 have to be mounted and R6

must be unplaced.

FPGA_PMOD1_P2

FPGA_PMOD1_P4

FPGA_PMOD1_P1

FPGA_PMOD1_P3

FPGA_PMOD1_P7 FPGA_PMOD1_P8

FPGA_PMOD1_P10

FPGA_PMOD1_P9

FPGA_PMOD2_P2

FPGA_PMOD2_P4

FPGA_PMOD2_P1

FPGA_PMOD2_P3

FPGA_PMOD2_P7 FPGA_PMOD2_P8

FPGA_PMOD2_P10FPGA_PMOD2_P9

FPGA_CLK_66MHZ

MCU_FPGA_OSC_EN

+VFPGA_IO_3V3

+VFPGA_IO_3V3 +VFPGA_IO_3V3

C28

100nF

HEADER 6X2

1OE ST

GND

VCC

OUT

C25

100nF

C27

10uF 10V 0805

C20

10nF

C29

100nF

C19

100nF

C30

10uF 10V 0805

10K NM

C32

100nF

33R2

R126

10k

C31

10uF 10V 0805

C26

10uF 10V 0805

2VCC

DS1088LU-66

VCC

7n/c

n/c

1OUT

GND

PDN 6

HEADER 6X2

Two right-angle, 12-pin

(2 x 6 female) Peripheral

Module (PMOD) headers

(J8, J9) are interfaced to

the FPGA, with each

header providing 3.3 V

power, ground, and

eight I/O's. These headers

may be utilized as

general-purpose I/Os

or may be used to

interface to PMODs.

J6 and J8 are placed in

close proximity

(0'9" -centers) on the

PCB in order to

support dual PMODs.

GSPG30072014DI1210

DocID026791 Rev 2 9/19

STEVAL-IME008V1 Schematic diagrams

Figure 8. STEVAL-IME008V1 circuit schematic (8 of 16)

SW2, SW3, SW4, Details RS (378-6527)

PUSHBUTTONS

CTRL LED

GREEN LED

Kingbright KP2012SURC

RS: 466-3778

Farnell: 8529906

LED 0805

Near START button

Near STOP button

IDLE state signal

ERROR signal

PROGRAM

STOP

FPGA RESET

START

IDLE

ERROR

RED LED

Kingbright KP2012SURC

RS: 466-3829

Farnell: 8529930

LED 0805

CTRL_LED0

CTRL_LED2

CTRL_LED1

CTRL_LED3

FPGA_RESET

START_PB

SEL_PROG_PB

STOP_PB

+VFPGA_IO_3V3 +VFPGA_IO_3V3

GREEN

R10

56R 0402

10K 0402

R12

56R 0402

SW3

R11

SW PUSHBUTTON-DPST

56R 0402

C22

100nF

GREEN

10K 0402

C24

100nF

10K 0402

SW2

SW PUSHBUTTON-DPST

C21

100nF

GREEN

R13

56R 0402

RED

SW4

SW PUSHBUTTON-DPST

C23

100nF

SW5

SW PUSHBUTTON-DPST

GSPG30072014DI1215

Schematic diagrams STEVAL-IME008V1

10/19 DocID026791 Rev 2

Figure 9. STEVAL-IME008V1 circuit schematic (9 of 16)

MCU_FPGA_GPIO2

MCU_FPGA_GPIO3

MCU_FPGA_GPIO0

MCU_FPGA_GPIO1

PROG_LED10

PROG_LED11

PROG_LED2

PROG_LED3

PROG_LED6

PROG_LED7

PROG_LED0

PROG_LED1

PROG_LED4

PROG_LED5

PROG_LED8

PROG_LED9

FPGA_MODE0

CCLK

FPGA_SPI_MISO1

PROG_LED14

PROG_LED15

MCU_FPGA_GPIO6

MCU_FPGA_GPIO7

MCU_FPGA_GPIO4

MCU_FPGA_GPIO5

PROG_LED12

PROG_LED13

FPGA_SPI_MISO2

FPGA_SPI_MOSI

FPGA_SPI_SEL

FPGA_INIT_B

FPGA_SPI_MISO3

FPGA_MODE1

MCU_FPGA_GPIO[0:7]

MCU_FPGA_GPIO0

MCU_FPGA_GPIO1

MCU_FPGA_GPIO2

MCU_FPGA_GPIO3

MCU_FPGA_GPIO4

MCU_FPGA_GPIO5

MCU_FPGA_GPIO6

MCU_FPGA_GPIO7

MCU_FPGA_GPIO[0:7]

U4C

FPGA - Bank 2

XC6SLX16-2CSG324C

T15

R15

V16

U16

T13

R13

V15

U15

V14

T14

P12

N12

V13

U13

N11

M11

T11

R11

V12

T12

P11

N10

M10

V11

U11

T10

R10

V10

U10

TP2

TEST POINT

IO_2_L01N_M0_CMPMISO

IO_2_L01P_CCLK

IO_2_L02N_CMPMOSI

IO_2_L02P_CMPCLK

IO_2_L03N_MOSI_CSI_B_MISO0

IO_2_L03P_D0_DIN_MISO_MISO1

IO_2_L05N

IO_2_L05P

IO_2_L12N_D2_MISO3

IO_2_L12P_D1_MISO2

IO_2_L13N_D10

IO_2_L13P_M1

IO_2_L14N_D12

IO_2_L14P_D11

IO_2_L15N

IO_2_L15P

IO_2_L16N_VREF

IO_2_L16P

IO_2_L19N

IO_2_L19P

IO_2_L20N

IO_2_L20P

IO_2_L22N

IO_2_L22P

IO_2_L23N

IO_2_L23P

IO_2_L29N_GCLK2

IO_2_L29P_GCLK3

IO_2_L30N_GCLK0_USERCCLK

IO_2_L30P_GCLK1_D13

IO_2_L31N_GCLK30_D15

IO_2_L31P_GCLK31_D14

IO_2_L32N_GCLK28

IO_2_L32P_GCLK29

IO_2_L40N

IO_2_L40P

IO_2_L41N_VREF

IO_2_L41P

IO_2_L43N

IO_2_L43P

IO_2_L44N

IO_2_L44P

IO_2_L45N

IO_2_L45P

IO_2_L46N

IO_2_L46P

IO_2_L47N

IO_2_L47P

IO_2_L48N_RDWR_B_VREF

IO_2_L48P_D7

IO_2_L49N_D4

IO_2_L49P_D3

IO_2_L62N_D6

IO_2_L62P_D5

IO_2_L63N

IO_2_L63P

IO_2_L64N_D9

IO_2_L64P_D8

IO_2_L65N_CSO_B

IO_2_L65P_INIT_B

GSPG30072014DI1220

Table des matières

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