Motorola M6800 EXORciser Manuel utilisateur

MPU-1

INTRODUCTION

The Motorola M6800 Microcomputer System of standard LSI (Large Scale

Integration) devices permits the systems designer to configure and connect a

total system with a minimum amount of time and effort. The MC6800

Microprocessing Unit (MPU) forms the nucleus of the system. LSI modules

available which may be used to configure a total system in conjunction with

the MC6800 MPU, include: 1) MC6810 Random Access Memory (RAM); 2) MC6830 Read

Only Memory (ROM); 3) MC6820 Peripheral Interface Adapter (PIA), and 4)

MC6850 Asynchronous Communications Interface Adapter (ACIA).

The MPU communicates with the rest of the system via a 16 bit

address bus and an 8 bit data bus. The 16 bit address bus provides the MPU

the capability of addressing up to 64K. The 8 bit data bus is bi-directional

in that data is transferred both into the MPU or out of the MPU over the same

bus. A read/write (R/W) line is provided to allow the MPU to control the

direction of data transfer.. Since the same bus is used for both data into

the MPU or out of the MPU, a separate 8 line bus is saved.

Other features of the M6800 system include a single +5 volt supply,

operation at clock rates from 100 kilohertz to 1 megahertz, plus hardware and

software interrupt capability.

MPU-2

Microprocessing Unit (MC6800)

The nucleus of the M6800 Microcomputer Family is the microprocessing

unit (MPU). The MPU is enclosed in a 40 pin package as shown below:

Features included in the MPU are:

1. Two accumulators (ACCA and ACCB)

2. One index register (X)

3. One program counter register (PC)

4. One stack pointer register (SP)

MPU-3

5. One condition code register (CC)

6. 72 instructions

7. Five addressing modes

8. System clock range of 100 kilohertz to 1 megahertz

9. Program interrupt capability

Accumulators

The MPU contains 2 accumulators designated ACCA and ACCB. Each

accumulator is 8 bits (one byte) long and is used to hold operands and data

from the arithmetic logic unit. Instructions which involve one or both

accumulators are:

ABA -Add accumulator A to accumulator B

ADC -Add with carry

ADD -Add without carry

AND -Logical AND

ASL -Arithmetic shift left

ASR -Arithmetic shift right

BIT -Bit test

CBA -Compare accumulators

CLR -Clear

CMP -Compare

COM -Complement

DAA -Decimal adjust ACCA

DEC -Decrement

EOR -Exclusive OR

MPU-4

INC –Increment

LDA -Load accumulator

LSR -Logical shift right

NEA -Negate

ORA -Inclusive OR

PSH -Push data onto stack

PUL -Pull data from stack

ROL -Rotate left

ROR -Rotate right

RTI -Return from interrupt

SBA -Subtract accumulators

SBC -Subtract with carry

STA -Store accumulator

SUB -Subtract

SWI -Software interrupt

TAB -Transfer from accumulator A to accumulator B

TAP -Transfer from accumulator A to processor condition

codes register

TBA -Transfer from accumulator B to accumulator A

TPA -Transfer from processor condition codes register to

accumulator A

TST -Test

WAI -Wait for interrupt

Index Register

The index register (X) is a 16 bit (2 byte) register which is

primarily used to store a memory address in the Indexed mode of memory

addressing. The index register may be decremented, incremented and stored.

Instructions which involve the index register are:

MPU-5

CPX -Compare index register

DEX -Decrement index register

INX -Increment index register

LDX -Load index register

RTI -Return from interrupt

STX -Store index register

SWI -Software interrupt

TSX -Transfer stack pointer to index register

TXS -Transfer index register to stack pointer

WAI -Wait for interrupt

Program Counter

The program counter (PC) is a 16 bit register that contains the

address of the next byte to be fetched from memory. When the current value of

the program counter is placed on the address buss, the program counter will

be incremented automatically.

Stack Pointer

The Stack Pointer (SP) is a 16 bit (2 byte) register that contains a

beginning address, normally in RAM, where the status of the MPU registers may

be stored when the MPU has other functions to perform, such as during an

interrupt or during a Branch to Subroutine (BTS). The address in the stack

pointer is the starting address of sequential memory locations in RAM where

MPU status registers will be stored. The status of the MPU will be stored in

the RAM as follows:

Stack Pointer Address : contents of PCL

Stack Pointer Address-1 : contents of PCH

Stack Pointer Address-2 : contents of IXL

Stack Pointer Address-3 : contents of IXH

Stack Pointer Address-4 : contents of ACCA

MPU-6

Stack Pointer Address-5 : Contents of ACCB

Stack Pointer Address-6 : Contents of CC

After the status of each register is stored on the stack, the Stack

Pointer will be decremented. When the stack is unloaded (status of registers

restored), the status of the last register on the stack will be the first

Condition Code Register (CC)

The condition code register is an 8 bit register. Each individual

bit may get set or get cleared from execution of an instruction. To see how

each instruction effects the condition code register, refer to the M6800

programming manual. The primary use of this register is execution of the

conditional branch instruction. Bit 6 and 7 are not used and remain at logic

"1."

BIT N0. FUNCTION

0C (Carry-Borrow Test)

1V (Overflow Test)

2Z (Zero Test)

3N (Negative Test)

4I (Interrupt Mask Test)

5H (Half Carry Test)

MPU-7

Carry-Borrow: For addition, the carry-borrow condition code (C) in the

zero bit position, represents a carry. This bit gets set

(C=1) to indicate a carry, and is reset (C=0) if there is

no carry.

For subtraction, the C bit is set (C=1) to indicate a

borrow and is reset (C=0) to indicate there was no borrow.

Overflow: The V bit (bit 1) of the condition code register is set

(V=1) when two's complement overflow results from an

arithmetic operation, and is reset (V=O) if two's

complement overflow does not occur.

Zero:The Z bit (bit 2) of the condition code register is set

(Z=1) if the result of an arithmetic operation is zero, and

is reset (Z=0) if the result is not zero.

Negative: The N bit (bit 3) of the condition code register is set

(N=1) if bit 7 of an arithmetic operation is set (equal to

1). This indicates that the two's complement number,

represented by the bit pattern of the result, is negative.

The N bit is reset (N=0) if bit 7 of the arithmetic result

is equal to 0.

Interrupt Mask: If this I bit (bit 4) is set (I=1), the MPU cannot respond

to an interrupt request from any peripheral device.

Half-Carry: The half carry bit H (bit 5) of the condition code register

is set (H=1) during execution of any of the instructions

ABA,ADC, or ADD, if there is a carry from bit position 3 to

bit position 4. The half carry is reset (H=0) during these

operations, if there is no carry from bit position 4.

MPU-8

MPU Signal Descriptions

1. READ/WRITE (R/W):

This output line is used to signal all devices external to

the MPU that the MPU is in a read state (R/W = High) or a

write state (R/W = Low). The normal standby state of this

line when no external devices are being accessed is a high

state. This line is three-state. When three-state goes

high, this line enters the high impedance mode.

2. VALID MEMORY ADDRESS(VMA):

This output line, (when in the high state) tells all

devices external to the MPU that there is a valid address

in the address bus. For RAM's and ROM's, this line should

be ANDed with 12 clock and used as one of the enables. For

PIA's, this line should be ANDed with one of the PIA

address lines. This signal is not three-state.

3. DATA BUS ENABLE(DBE):

This signal will enable the data bus drives when in the

high state. This input is normally the phase 2 (12) clock.

During the high state, it will permit data to be output

during a write cycle. During an MPU read cycle, the data

bus drives will be disabled internally.

4. INTERRUPT REQUEST(IRQ):

This input from the PIA's requests that an interrupt

sequence be generated within the machine. The processor

will wait until it completes the current instruction that

is being executed before it recognizes the request. At that

time, if the interrupt mask bit in the Condition Code

begin an interrupt sequence. The Index Register, Program

MPU-9

Counter, Accumulators, and Condition Code Register are

stored away on the stack. Next the MPU will respond to the

interrupt request by setting the interrupt mask bit high so

that no further interrupts may occur. At the end of the

cycle, a 16-bit address will be loaded that points to a

vectoring address which is located in memory locations n-6

and n-7 where n is the highest ROM address. An address

loaded at these locations causes the MPU to branch to an

interrupt routine in memory.

5. Phase One (Øl)& Phase (Ø2)Clocks:

These two pins are used or a two phase non-overlapping

clock that runs at the V DD voltage level.

These clocks run at a rate up to 1 megahertz.

6. Restart (RES):

RESTART (RES)--This input is used to start the MPU from a

power down condition, resulting from a power failure or an

initial start-up of the processor. If a positive edge is

detected on the input, this will signal the MPU to begin

the restart sequence. This will restart the MPU and start

execution of a routine to initialize the processor. All the

higher order address lines will be forced high. For the

restart, the last 2 memory locations in the last ROM

(n&n-1) will be accessed, whereby an address is stored

which is the address to be loaded in the program counter

which tells the processor where program execution is to

begin.

7. NON-MASKABLE INTERRUPT(NMI):

This input requests that a nonmask-interrupt sequence be

generated within the processor. As with the Interrupt

MPU-10

Request signal, the processor will complete the current

instruction that is being executed before it recognizes the

NMI signal. The interrupt mask bit in the Condition Code

Counter, Accumulators, and Condition Code Register are

stored away on the stack. At the end of the cycle, a 16-bit

address will be loaded that points to a vectoring address

which is located in memory locations n-2 and n-3. An

address loaded at these locations causes the MPU to branch

to an nonmaskable interrupt routine in memory.

8. Go/Halt(G/H):

When this input is in the high state, the machine will

fetch the instruction addressed by the program counter and

start execution. When low all activity in the machine will

be halted. This input is level sensitive. In the halt mode,

the machine will stop at the end of an instruction. Bus

Available will be at a logic "1" level. Valid Memory

Address will be at a logic "0" and all other three-state

lines will be in the three-state mode.

The halt line must go low with the leading edge of phase

one to insure single instruction operation. If the halt

line does not go low with the leading edge of phase one,

one or two instruction operations may result, depending on

when the halt line goes low relative to the phasing of the

clock.

9. BUS AVAILABLE (BA):

The Bus Available signal will normally be in the low state.

When activated, it will go to the high state indicating

that the MPU has stopped and that the address bus is

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