Motorola MPC823e Manuel utilisateur

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PowerPC

™

MPC823e

Reference Manual

The Microprocessor for Mobile Computing

Trademarks

QUICC

™

is a registered trademark of Motorola, Inc. PowerPC

™

is a registered trademark of IBM Corporation

and is used by Motorola under license from IBM. I

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All other trademarks are the property of their respective owners.

Acknowledgments

The MPC823e Support Team would like to thank the following people for their

contribution to the success of the MPC823e:

Art Miller, CW Clark, Ken Edwards, Kevin Owen, Ray Burgess, Tom Gunter, John Round, Mike Shoemake,

James Wilson, Chris Lines, Ricardo Berger, Yehuda Rudin, Yair Liebman, Udi Barel, the rest of the Israel

design team, Stu Werbner, Tiffany Huling-Broadous, John Dailey, Lan Nguyen, Richard Hendricks,

Darcy Volden, Trish Sierer, Arnaldo Cruz, Danny Nguyen, Myle Buchanan, Joseph Mayfield, Rodolfo Guillen,

the rest of the product/test engineering team, Brian McCalley, Alan Weiss, Steve Rosebaugh, Jasmine Hsiao,

Mike Collier, John Southard, Joseph Lee, Pat Carr, Mark VandenBrink, the rest of the Systems Software team,

Yoichi Kimura, Yuzo Kuramochi, Tanamachi Goro, Fumihiko Kondo, Keiji Momozaki, Jean-Paul Davi,

Per-Eric Josefsson, Rodney Watt, Axel Streicher, Pierre Juste, Gary Segal, Mark DiPerri, Kurt Miller,

Steve Shoap, Rob Wackerman, Rick Heider, Gary Wilson, Thomas Yeh, Bill Durrenberger, Dave Hyder,

the rest of the Field Applications Engineering/Sales support team, Pamela Mitchell, Nina Friedman,

the rest of the Technical Information Center support team, Dan Malek, Jim Belesiu, Clark Liang, Ronny

Svensson, Mark Wagner, Bulent Egilmez, Kurt Fuqua, Robert Applebaum, Nick Vaccaro, Weifu Shi,

Roozbeh Ghorishi, Robert Ritchey, Brad Scott, Dan Malek, the rest of our customers,

the gang at comp.sys.powerpc.tech and linuxppc-embedded, and to many others.

MOTOROLA

MPC823e REFERENCE MANUAL

TABLE OF CONTENTS

Paragraph Page

Number Title Number

Section 1

Introduction

1.1 Features ................................................................................................1-1

1.2 Architecture ...........................................................................................1-6

1.2.1 The Embedded PowerPC Core ..................................................1-8

1.2.2 The System Interface Unit ..........................................................1-8

1.2.3 The Communication Processor Module .....................................1-9

1.2.4 The Video/LCD Controller ........................................................1-10

1.2.4.1 The Video Controller .....................................................1-10

1.2.4.2 The LCD Controller .......................................................1-10

1.3 The PCMCIA-ATA Controller ..............................................................1-10

1.4 Power Management ............................................................................1-11

1.5 System Debug Support .......................................................................1-11

1.6 Applications .........................................................................................1-11

1.7 Differences Between MPC823 (Rev B) and MPC823e .......................1-12

1.8 MPC823e Glueless System Design ....................................................1-12

Section 2

External Signals

2.1 The System Bus Signals .......................................................................2-2

Section 3

Memory Map

Section 4

Reset

4.1 Types of Reset ......................................................................................4-2

4.1.1 Power-On Reset .........................................................................4-2

4.1.2 External Hard Reset ...................................................................4-3

4.1.3 Internal Hard Reset ....................................................................4-3

4.1.3.1 Loss of Lock ....................................................................4-3

4.1.3.2 Software Watchdog Reset ..............................................4-3

4.1.3.3 Checkstop Reset ............................................................4-3

4.1.3.4 Debug Port Hard Reset ..................................................4-4

4.1.3.5 JTAG Reset ....................................................................4-4

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4.1.4 External Soft Reset ....................................................................4-4

4.1.5 Internal Soft Reset .....................................................................4-4

4.1.5.1 Debug Port Soft Reset ....................................................4-4

4.2 Reset Status Register ...........................................................................4-5

4.3 How to Configure Reset ........................................................................4-7

4.3.1 Hard Reset .................................................................................4-7

4.3.1.1 Hard Reset Configuration Word ...................................4-10

4.3.2 Soft Reset ................................................................................4-12

Section 5

Clocks and Power Control

5.1 Features ................................................................................................5-1

5.2 Register Model ......................................................................................5-3

5.2.1 System Clock and Reset Control Register .................................5-3

5.2.2 PLL, Low-Power, and Reset Control Register ...........................5-7

5.3 The Clock Module ...............................................................................5-10

5.3.1 On-Chip Oscillators and External Clock Input ..........................5-12

5.3.2 System PLL ..............................................................................5-12

5.3.2.1 SPLL Stability ...............................................................5-13

5.3.3 The Low-Power Clock Divider ..................................................5-14

5.3.4 Internal Clock Signals ..............................................................5-16

5.3.4.1 The General System Clocks .........................................5-16

5.3.4.2 The Baud Rate Generator Clock ..................................5-19

5.3.4.3 The Synchronization Clocks .........................................5-20

5.3.4.4 The LCD Clocks ...........................................................5-21

5.3.5 Clock Configuration ..................................................................5-22

5.3.5.1 Mode Clock Pins ...........................................................5-22

5.3.5.2 The System Phase-Locked Loop Pins .........................5-23

5.4 Power Control .....................................................................................5-24

5.4.1 Power Rails ..............................................................................5-24

5.4.2 Keep-Alive Power .....................................................................5-25

5.4.2.1 Power Switching Example ............................................5-26

5.4.2.2 Register Lock ................................................................5-27

5.5 Low-Power Operation .........................................................................5-28

Section 6

The PowerPC Core

6.1 Features ................................................................................................6-1

6.2 Basic Structure of the Core ...................................................................6-2

6.2.1 Instruction Flow Within the Core ................................................6-2

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6.2.2 Basic Instruction Pipeline ...........................................................6-4

6.3 Sequencer Unit .....................................................................................6-4

6.3.1 Flow Control ...............................................................................6-5

6.3.2 Issuing Instructions .....................................................................6-6

6.3.3 Interrupts ....................................................................................6-7

6.3.4 Implementing the Precise Exception Model ...............................6-8

6.3.4.1 Restartability After An Interrupt .....................................6-10

6.3.5 Processing an Interrupt ............................................................6-11

6.3.6 Serialization ..............................................................................6-12

6.3.6.1 Latency .........................................................................6-12

6.3.7 The External Interrupt ...............................................................6-13

6.3.7.1 Latency .........................................................................6-13

6.3.8 Interrupt Ordering .....................................................................6-14

6.4 The Register Unit ................................................................................6-15

6.4.1 Control Registers ......................................................................6-16

6.4.1.1 Physical Location of Special Registers .........................6-19

6.4.1.2 PowerPC Standard Control Register Bit Assignment....6-20

6.4.1.2.1 Machine State Register ....................................6-20

6.4.1.2.2 The Condition Register ....................................6-22

6.4.1.2.3 Fixed-Point Exception Cause Register ............6-23

6.4.1.3 Initializing the Control Registers ...................................6-24

6.4.1.3.1 System Reset Interrupt ....................................6-24

6.4.1.3.2 Hard/Soft Reset ................................................6-24

6.5 The Fixed-Point Unit ...........................................................................6-24

6.5.1 XER Update In Divide Instructions ...........................................6-24

6.6 The Load/Store Unit ............................................................................6-25

6.6.1 Issuing Load/Store Instructions ................................................6-26

6.6.2 Serializing Load/Store Instructions ...........................................6-27

6.6.3 Instructions Issued to the Data Cache .....................................6-27

6.6.4 Issuing Store Instruction Cycles ...............................................6-27

6.6.5 Issuing Nonspeculative Load Instructions ................................6-27

6.6.6 Executing Unaligned Instructions .............................................6-28

6.6.7 Little-Endian Mode Support ......................................................6-29

6.6.8 Atomic Update Primitives .........................................................6-29

6.6.9 Instruction Timing .....................................................................6-30

6.6.10 Stalling Storage Control Instructions ........................................6-30

6.6.11 Accessing Off-Core Special Registers .....................................6-30

6.6.12 Storage Control Instructions .....................................................6-31

6.6.13 Exceptions ................................................................................6-31

6.6.13.1 DAR, DSISR, and BAR Operation ................................6-31

Section 7

TABLE OF CONTENTS (Continued)

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PowerPC Architecture Compliance

7.1 PowerPC User Instruction Set Architecture (Book I) ............................7-1

7.1.1 Computation Modes ...................................................................7-1

7.1.2 Reserved Fields .........................................................................7-1

7.1.3 Classes of Instructions ...............................................................7-1

7.1.4 Exceptions ..................................................................................7-2

7.1.5 The Branch Processor ...............................................................7-2

7.1.6 Fetching Instructions ..................................................................7-2

7.1.7 Branch Instructions ....................................................................7-2

7.1.7.1 Invalid Branch Instruction Forms ....................................7-2

7.1.7.2 Branch Prediction ...........................................................7-2

7.1.8 The Fixed-Point Processor .........................................................7-2

7.1.8.1 Move To/From System Register Instructions .................7-3

7.1.8.2 Fixed-Point Arithmetic Instructions .................................7-3

7.1.9 The Load/Store Processor .........................................................7-3

7.1.9.1 Fixed-Point Load With Update and Store

With Update Instructions ................................................7-3

7.1.9.2 Fixed-Point Load and Store Multiple Instructions ...........7-3

7.1.9.3 Fixed-Point Load String Instructions ...............................7-3

7.1.9.4 Storage Synchronization Instructions .............................7-4

7.1.9.5 Optional Instructions .......................................................7-4

7.1.9.6 Little-Endian Byte Ordering ............................................7-4

7.2 PowerPC Virtual Environment Architecture (Book II) ............................7-4

7.2.1 Storage Model ............................................................................7-4

7.2.1.1 Memory Coherence ........................................................7-4

7.2.1.2 Atomic Update Primitives ...............................................7-4

7.2.2 The Effect Of Operand Placement on Performance ..................7-5

7.2.3 The Storage Control Instructions ...............................................7-5

7.2.4 Timebase ...................................................................................7-6

7.3 PowerPC Operating Environment Architecture (Book III) .....................7-6

7.3.1 The Branch Processor ...............................................................7-6

7.3.1.1 Machine State Register ..................................................7-6

7.3.1.2 Processor Version Register ............................................7-6

7.3.1.3 Branch Processors Instructions ......................................7-6

7.3.2 The Fixed-Point Processor .........................................................7-6

7.3.2.1 Unsupported Registers ...................................................7-6

7.3.2.2 Added Registers .............................................................7-6

7.3.3 Storage Model ............................................................................7-6

7.3.3.1 Address Translation ........................................................7-6

7.3.4 Reference and Change Bits .......................................................7-7

7.3.5 Storage Protection .....................................................................7-7

7.3.6 Storage Control Instructions .......................................................7-7

TABLE OF CONTENTS (Continued)

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MOTOROLA

MPC823e REFERENCE MANUAL

7.3.6.1 Data Cache Block Invalidate (dcbi) .................................7-7

7.3.6.2 TLB Invalidate Entry (tlbie) .............................................7-7

7.3.6.3 TLB Invalidate All (tlbia) ..................................................7-7

7.3.6.4 TLB Synchronize (tlbsync) ..............................................7-7

7.3.7 Interrupts ....................................................................................7-7

7.3.7.1 Classes ...........................................................................7-7

7.3.7.2 Processing ......................................................................7-8

7.3.7.3 Definitions .......................................................................7-8

7.3.7.3.1 System Reset Interrupt ......................................7-9

7.3.7.3.2 Machine Check Interrupt ....................................7-9

7.3.7.3.3 Data Storage Interrupt ......................................7-10

7.3.7.3.4 Instruction Storage Interrupt .............................7-10

7.3.7.3.5 Alignment Interrupt ...........................................7-10

7.3.7.3.6 Program Interrupt .............................................7-11

7.3.7.3.7 Floating-Point Unavailable Interrupt .................7-11

7.3.7.3.8 Trace Interrupt ..................................................7-11

7.3.7.3.9 Floating-Point Assist Interrupt ..........................7-11

7.3.7.3.10 Implementation-Dependent Software

Emulation Interrupt ............................................7-12

7.3.7.3.11 Implementation-Specific Instruction TLB

Miss Interrupt ....................................................7-12

7.3.7.3.12 Implementation-Specific Instruction TLB

Error Interrupt ....................................................7-13

7.3.7.3.13 Implementation-Specific Data TLB Miss

Interrupt .............................................................7-14

7.3.7.3.14 Implementation-Specific Data TLB Error

Interrupt .............................................................7-14

7.3.7.3.15 Implementation-Specific Debug Register .........7-15

7.3.7.4 Partially Executed Instructions ......................................7-17

7.3.8 Timer Facilities .........................................................................7-17

7.3.9 Optional Facilities and Instructions ...........................................7-17

Section 8

Instruction Execution Timing

8.1 Instruction Timing List ...........................................................................8-1

8.2 Instruction Execution Timing Examples ................................................8-4

8.2.1 Data Cache Load .......................................................................8-4

8.2.2 Writeback ...................................................................................8-5

8.2.2.1 Writeback Arbitration ......................................................8-5

8.2.2.2 Private Writeback Bus Load ...........................................8-6

8.2.3 Fastest External Load (Data Cache Miss) ..................................8-7

TABLE OF CONTENTS (Continued)

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8.2.4 A Full History Buffer ...................................................................8-8

8.2.5 Branch Folding ...........................................................................8-9

8.2.6 Branch Prediction .....................................................................8-10

Section 9

Instruction Cache

9.1 Features ................................................................................................9-1

9.2 Programming the Instruction Cache .....................................................9-4

9.2.1 Instruction Cache Control and Status Register ..........................9-5

9.2.2 Instruction Cache Address Register ...........................................9-6

9.2.3 Instruction Cache Data Port Register .........................................9-7

9.3 Instruction Cache Operation .................................................................9-7

9.3.1 Instruction Cache Hit ..................................................................9-7

9.3.2 Instruction Cache Miss ...............................................................9-8

9.3.3 Instruction Fetch On A Predicted Path .......................................9-8

9.4 instruction Cache Commands ...............................................................9-8

9.4.1 Invalidating the Instruction Cache ..............................................9-9

9.4.2 Loading and Locking the Instruction Cache .............................9-10

9.4.3 Unlocking A Line ......................................................................9-10

9.4.4 Unlocking the Entire Instruction Cache ....................................9-11

9.4.5 Inhibiting the Instruction Cache ................................................9-11

9.4.6 Instruction Cache Read ............................................................9-12

9.4.7 Instruction Cache Write ............................................................9-14

9.5 Restrictions .........................................................................................9-14

9.6 Instruction Cache Coherency ..............................................................9-14

9.7 Updating Code And Memory Region Attributes ..................................9-14

9.8 Reset Sequence .................................................................................9-14

9.9 Debug Support ....................................................................................9-15

9.9.1 Fetching Instructions From The Development Port ..................9-15

Section 10

Data Cache

10.1 Features ..............................................................................................10-1

10.2 Organization of the Data Cache ..........................................................10-2

10.3 Programming the Data Cache ............................................................10-3

10.3.1 PowerPC Architecture Instructions ..........................................10-3

10.3.1.1 PowerPC User Instruction Set Architecture (Book I).....10-3

10.3.1.2 PowerPC Virtual Environment Architecture (Book II)....10-4

10.3.1.3 PowerPC Operating Environment Architecture

(Book III) .......................................................................10-4

TABLE OF CONTENTS (Continued)

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vii

10.3.2 Implementation-Specific Operations ........................................10-4

10.3.3 Special Registers of the Data Cache .......................................10-4

10.3.3.1 Data Cache Control and Status Register ......................10-5

10.3.3.2 Data Cache Address Register ......................................10-7

10.3.3.3 Reading the Cache Structures ......................................10-7

10.4 Operating the Data Cache ................................................................10-10

10.4.1 Data Cache Read ...................................................................10-10

10.4.2 Data Cache Write ...................................................................10-10

10.4.2.1 Copyback Mode ..........................................................10-11

10.4.2.2 Writethrough Mode .....................................................10-12

10.4.3 Data Cache Inhibited Accesses .............................................10-12

10.4.4 Data Cache Freeze ................................................................10-12

10.4.5 Data Cache Coherency ..........................................................10-13

10.5 Data Cache Commands ....................................................................10-13

10.5.1 Flushing and Invalidating the Cache ......................................10-13

10.5.2 Enabling and Disabling the Cache .........................................10-13

10.5.3 Locking and Unlocking the Cache ..........................................10-13

10.5.4 Data Cache Instructions .........................................................10-14

10.5.4.1 dcbi, dcbst, dcbf And dcbz Instructions ......................10-14

10.5.4.2 Touch ..........................................................................10-14

10.5.4.3 Storage Synchronization/Reservation ........................10-14

10.5.5 Data Cache Read ...................................................................10-14

Section 11

Memory Management Unit

11.1 Features ..............................................................................................11-1

11.2 Address Translation ............................................................................11-2

11.2.1 Translation Lookaside Buffer Operation ...................................11-2

11.3 Protection ............................................................................................11-3

11.4 Storage Control ...................................................................................11-4

11.5 Translation Table Structure .................................................................11-5

11.5.1 Level One Descriptor ................................................................11-9

11.5.2 Level Two Descriptor ..............................................................11-10

11.6 Programming the Memory Management Unit ...................................11-15

11.6.1 Control Registers ....................................................................11-16

11.6.1.1 MMU Instruction Control Register ...............................11-16

11.6.1.2 MMU Data Control Register ........................................11-17

11.6.1.3 MMU Current Address Space ID Register ..................11-18

11.6.1.4 MMU Instruction Effective Page Number Register .....11-19

11.6.1.5 MMU Data Effective Page Number Register ..............11-20

11.6.1.6 MMU Instruction Real Page Number Register ............11-21

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11.6.1.7 MMU Data Real Page Number Register ....................11-26

11.6.1.8 MMU Instruction Access Protection Register .............11-31

11.6.1.9 MMU Data Access Protection Register ......................11-32

11.6.1.10 MMU Instruction Tablewalk Control Register .............11-33

11.6.1.11 MMU Data Tablewalk Control Register ......................11-34

11.6.1.12 MMU Tablewalk Base Register ..................................11-36

11.6.1.13 MMU Tablewalk Special Register ...............................11-37

11.6.2 MMU Data Content-Addressable Registers ...........................11-37

11.6.2.1 MMU Data CAM Entry Read Register ........................11-38

11.6.2.2 MMU Data RAM Entry Read Register 0 .....................11-39

11.6.2.3 MMU Data RAM Entry Read Register 1 .....................11-41

11.6.3 MMU Instruction Content-Addressable Registers ..................11-43

11.6.3.1 MMU Instruction CAM Entry Read Register ...............11-43

11.6.3.2 MMU Instruction RAM Entry Read Register 0 ............11-45

11.6.3.3 MMU Instruction RAM Entry Read Register 1 ............11-46

11.7 Interrupts ...........................................................................................11-47

11.7.1 Implementation-Specific Instruction TLB Miss .......................11-47

11.7.2 Implementation-Specific Data TLB Miss ................................11-47

11.7.3 Implementation-Specific Instruction TLB Error .......................11-48

11.7.4 Implementation-Specific Data TLB Error ................................11-48

11.8 Manipulating the Translation Lookaside Buffer .................................11-49

11.8.1 Reloading the Translation Lookaside Buffer ..........................11-49

11.8.1.1 Translation Reload Examples .....................................11-50

11.8.2 Controlling the TLB Replacement Counter ............................11-51

11.8.3 Invalidating the Translation Lookaside Buffer ........................11-51

11.8.4 Loading the Reserved TLB Entries ........................................11-51

11.9 Requirements For Accessing The Memory Management Unit

Control Registers ..............................................................................11-52

Section 12

System Interface Unit

12.1 Features ..............................................................................................12-2

12.2 System Configuration and Protection .................................................12-2

12.3 Interrupt Configuration ........................................................................12-5

12.3.1 The Interrupt Structure .............................................................12-5

12.3.2 Priority of the Interrupt Sources ...............................................12-6

12.3.3 Programming the Interrupt Controller .......................................12-7

12.3.3.1 SIU Interrupt Pending Register .....................................12-7

12.3.3.2 SIU Interrupt Mask Register .........................................12-8

12.3.3.3 SIU Interrupt Edge/Level Register ................................12-9

12.3.3.4 SIU Interrupt Vector Register .....................................12-10

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