Intel Pentium III Processor 512K Mode d’emploi

Low Voltage Intel

Pentium

III

Processor 512K Dual Processor

Platform

Design Guide

March 2002

Order Number: 273674-001

2Design Guide

Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any intellectual

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Intel may make changes to specifications and product descriptions at any time, without notice.

Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for

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The Low Voltage Intel®Pentium®III processor 512K may contain design defects or errors known as errata which may cause the product to deviate

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Design Guide 3

LV Intel

Pentium

III Processor 512K Dual Processor Platform

Contents

1.0 Introduction ...............................................................................................................................7

1.1 Related Documents ..............................................................................................................7

1.2 Conventions and Terminology..............................................................................................8

2.0 General Design Considerations........................................................................................9

2.1 Nominal Board Stackup........................................................................................................9

2.2 Micro-FCBGA Component Keepout ...................................................................................10

3.0 Processor Host Bus Design..............................................................................................13

3.1 Initial Timing Analysis .........................................................................................................13

3.2 General Topology and Layout Guidelines ..........................................................................14

3.3 Wired-OR Signal Considerations........................................................................................15

3.4 Simulation Methodology .....................................................................................................16

3.5 Trace Routing.....................................................................................................................17

3.6 Layout Rules for AGTL Signals ..........................................................................................17

3.6.1 Ground Reference .................................................................................................17

3.6.2 Reference Plane Splits ..........................................................................................17

3.6.3 CPU Breakout........................................................................................................17

3.6.4 Minimizing Crosstalk..............................................................................................17

3.7 Layout Rules for Non-AGTL (CMOS) Signals ....................................................................18

3.8 Undershoot/Overshoot Requirements ................................................................................18

3.9 Debug Port Routing Guidelines..........................................................................................19

3.9.1 Target System Implementation..............................................................................19

4.0 Clocking ....................................................................................................................................24

4.1 General Clocking Considerations .......................................................................................24

4.2 Single Ended Host Bus Clocking Routing...........................................................................25

4.2.1 CLKREF Filter Implementation..............................................................................27

4.2.2 Single-Ended Clocking BSEL[1:0] Implementation................................................28

4.3 Debug Port Host Clock Connection....................................................................................29

4.4 Clock Driver Decoupling and Power Delivery.....................................................................29

5.0 Power..........................................................................................................................................30

5.1 Terminology........................................................................................................................30

5.2 Typical Power Delivery .......................................................................................................30

5.3 LV Intel®Pentium®III Processor 512K Power Requirements............................................32

5.3.1 Voltage Tolerance..................................................................................................32

5.3.2 Multiple Voltages ...................................................................................................32

5.3.3 Voltage Sequencing...............................................................................................33

5.4 Meeting Dual Processor Power Requirements...................................................................33

5.4.1 Supplying Voltage..................................................................................................33

5.4.2 Decoupling Technology and Transient Response.................................................33

5.5 Recommendations..............................................................................................................35

5.5.1 Decoupling Guidelines for LV Intel®Pentium®III Processor 512K Designs .........35

5.5.2 PLL Filter Recommendations ................................................................................36

4Design Guide

LV Intel

Pentium

III Processor 512K Dual Processor Platform

6.0 Thermals...................................................................................................................................38

6.1 THERMTRIP# Requirements .............................................................................................38

6.2 THERMTRIP# Erratum.......................................................................................................38

7.0 System Design Checklist...................................................................................................40

7.1 Introduction.........................................................................................................................40

7.2 Host Interface AGTL Bus and AGTL Signals......................................................................40

7.3 CMOS (Non-AGTL) Signals................................................................................................41

7.4 TAP/ITP Checklist...............................................................................................................42

7.5 Miscellaneous Checklist .....................................................................................................42

Figures

1 Sample Board Stackup.................................................................................................................9

2 Micro-FCBGA Component Keepout ...........................................................................................10

3Micro-FCBGA Package – Top and Bottom Isometric Views ......................................................12

4 System Bus T-Topology .............................................................................................................14

5 Wired-OR Termination Topology................................................................................................16

6 Simple Terminations...................................................................................................................20

7 TCK Termination, DP System ....................................................................................................21

8 PRDYx# Signal Termination.......................................................................................................21

9 RESET# Signal Termination.......................................................................................................22

10 JTAG Signals TDI/TDO for Processor Only ...............................................................................23

11 Host Bus Clock Connections......................................................................................................24

12 Single Ended Clocking Topology - CPU.....................................................................................25

13 Single Ended Clocking Topology................................................................................................25

14 CLKREF Filter Implementation...................................................................................................27

15 Single-Ended Clock BSEL Circuit (133 MHz).............................................................................28

16 Ideal LV Intel®Pentium®III Processor 512K Power Supply Scheme........................................31

17 Power Distribution for a DP System Motherboard......................................................................31

18 Detailed Power Distribution Model .............................................................................................32

19 VRM 8.5 Board Power Distribution Model..................................................................................32

20 1206 Capacitor Pad and Via Layouts.........................................................................................34

21 Processor PLL Filter...................................................................................................................36

22 PLL Power Low Pass Filter Response.......................................................................................37

23 LV Intel Pentium III processor 512K Example THERMTRIP# Workaround Circuit.....................39

Design Guide 5

LV Intel

Pentium

III Processor 512K Dual Processor Platform

Tables

1 Related Documents......................................................................................................................7

2 Micro-FCBGA Package Mechanical Specifications....................................................................11

3 System Timing Equations...........................................................................................................13

4 System Timing Terms.................................................................................................................13

5 System Bus Timing Parameters.................................................................................................14

6 Sample CPU to CPU flight time calculations..............................................................................14

7Trace Lengths for “T” Topology (ServerWorks Chipset).............................................................15

8 Component Values for T Topology.............................................................................................15

9 Wired-OR Values........................................................................................................................16

10 System Signal Layout Guidelines...............................................................................................20

11 JTAG Signal Layout Guidelines..................................................................................................20

12 Execution Signals Routing Guidelines........................................................................................21

13 Debug Port Termination Requirement........................................................................................22

14 Routing Guidelines .....................................................................................................................23

15 Component Values for SE Clocking Topology............................................................................26

16 CLKREF Component Values......................................................................................................27

17 BSEL[1:0] Encoding....................................................................................................................28

18 LV Intel Pentium III processor 512K Bulk Capacitance Recommendations ...............................35

19 THERMTRIP# Timing Requirements..........................................................................................38

20 AGTL Signals..............................................................................................................................40

21 CMOS Signals............................................................................................................................41

22 TAP/ITP Signals .........................................................................................................................42

23 Clock Signals..............................................................................................................................42

24 Miscellaneous Signals................................................................................................................43

25 Power Signals.............................................................................................................................44

6Design Guide

LV Intel

Pentium

III Processor 512K Dual Processor Platform

Revision History

Date Revision Description

March 2002 001 First release of this document.

LV Intel

Pentium

III Processor 512K Dual Processor Platform

Design Guide 7

1.0 Introduction

This design guide is intended to be used by LV Intel Pentium III processor 512K system developers.

This design guide documents Intel’s design recommendations for dual-processor systems based on

the LV Intel®Pentium®III processor 512K with the ServerWorks* HE-SL and LE3 chipset. In

addition to providing design recommendations such as layout and routing guidelines, this

document also addresses possible system design issues such as processor power delivery, layout

considerations for mechanical pieces, EMI design impacts and system bus decoupling.

Carefully follow the design information, debug recommendations and system checklist presented

in this document. These design guidelines have been developed to ensure maximum flexibility for

board designers while reducing the risk of board related issues. The design information provided in

this document falls into one of two categories:

•Design Recommendations are necessary to meet the timing and signal quality specifications.

•Design Considerations are suggestions for platform design. These provide one way to meet

the design recommendations. They are based on the reference platforms designed by Intel.

They could be used as an example, but may not be applicable to your particular design.

Note: The guidelines recommended in this document are based on experience and simulation work done

at Intel while developing LV Intel Pentium III processor 512K based systems. The

recommendations are subject to change.

1.1 Related Documents

The reader of this specification should also be familiar with the material and concepts presented in

the following documents:

Table 1. Related Documents

Document Order Number

P6 Family of Processors Hardware Developer’s Manual

244001

IA-32 Intel

Architecture Software Developer’s Manual

•

Volume I: Basic Architecture

•

Volume II: Instruction Set Reference

•

Volume III: System Programming Guide

245470

245471

245472

VRM 8.5 DC-DC Converter Design Guidelines

249659

Low Voltage Intel

Pentium

III

Processor 512K Datasheet

273673

Low Voltage Intel

Pentium

III

Processor 512K (DP) Thermal Design Guide

273675

Low Voltage Intel

Pentium

III

Processor 512K/815E Chipset Platform Design

Guide

273676

Intel

Pentium

III

Processor Specification Update

244453

Intel Processor Identification and the CPUID Instruction

241618

LV Intel

Pentium

III Processor 512K Dual Processor Platform

8Design Guide

1.2 Conventions and Terminology

For this document, the following terminology applies.

•Low Voltage Intel®Pentium®III Processor 512K - Intel’s name for the next generation

Intel®Pentium®III processor based on Intel’s 0.13-micron (i.e., 1.25 V VTT / AGTL)

technology. This processor contains 512 Kbytes of L2 cache, is dual processor capable, and

has a 133 MHz processor side bus.

•Micro FCBGA - Micro Flip Chip Ball Grid Array. The package technology used on the LV

Intel Pentium III processor 512K.

•Keep-out zone - The area on or near a Micro FCBGA packaged processor that system designs

can not utilize.

•Processor - For this document, the term processor is the generic form of the LV Intel Pentium

III processor 512K for the Micro FCBGA package.

LV Intel

Pentium

III Processor 512K Dual Processor Platform

Design Guide 9

2.0 General Design Considerations

This section documents layout and routing guidelines for LV Intel Pentium III processor 512K

platforms. This section does not discuss the functional aspects of any bus, or the layout guidelines

for an add-in device.

If the guidelines listed in this document are not followed, it is very important that thorough signal

integrity and timing simulations are completed for each design. Any deviation from the guidelines

should be simulated. Even when the guidelines are followed, Intel recommends that you simulate

critical signals to ensure proper signal integrity and flight time.

The trace impedance noted (i.e., 55 Ω± 10%) is the “nominal” trace impedance for a 4.5-mil wide

trace. Nominal trace impedance is the impedance of the trace when not subjected to the fields

created by changing current in neighboring traces. When calculating flight times, it is important to

consider the minimum and maximum impedance of a trace based on the switching of neighboring

traces. Using wider spaces between the traces can minimize this trace-to-trace coupling. In

addition, these wider spaces reduce settling time.

Coupling between two traces is a function of the coupled length, the distance separating the traces,

the signal edge rate, and the degree of mutual capacitance and inductance. To minimize the effects

of trace-to-trace coupling, follow the routing guidelines documented in this section.

2.1 Nominal Board Stackup

Figure 1 is an example of a 14-layer board stack-up. The impedance of all the signal layers should

be 55 Ω± 10%. A lower trace impedance reduces signal edge rates, overshoot, and undershoot, and

has less crosstalk than a higher trace impedance. A higher trace impedance increases edge rates and

may slightly decrease signal flight times. Please note that thicker core may help reduce board

warpage issues.

Figure 1. Sample Board Stackup

Signal Layer

Power Plane

Signal Layer

Ground Plane

Signal Layer

Power Plane

Ground Plane

Signal Layer

Ground Plane

Signal Layer

Power Plane

Signal Layer

LV Intel

Pentium

III Processor 512K Dual Processor Platform

10 Design Guide

Additional guidelines on board stack-up, placement, and layout include the following.

•The board impedance (Z) should be between 49.5 Ωand 60.5 Ω(55 Ω± 10% is

recommended).

•The dielectric process variation in the PCB fabrication should be minimized.

•The ground plane should not be split on the ground plane layer.

•Keep vias for decoupling capacitors as close to the capacitor pads as possible.

2.2 Micro-FCBGA Component Keepout

Figure 2 shows the keepout zones and dimensions for the Micro-FCBGA package. Table 2

provides the values for the mechanical specifications.

Figure 2. Micro-FCBGA Component Keepout

35 (E)

35 (D)

PIN A1 CORNER

Ø0.78(b)

479 places

SUBSTRATE KEEPOUT ZONE

DO NOT CONTACT PACKAGE

INSIDE THIS LINE

7 (K1)

8 places

5 (K)

4 places

NOTE:

Alldimensions in millimeters. Values shownare for reference only

0.20

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