Infineon PG-TO252 DPAK Manuel utilisateur

Additional information Please read the Important Notice and Warnings at the end of this document Revision 4.0

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Recommendations for board assembly of

Infineon transistor outline type packages

 
Additional information 2 of 31 Revision 4.0 
 2021-10-11 
Recommendations for board assembly of Infineon transistor outline 
type packages 
 
Table of contents 
 
Table of contents 
Table of contents............................................................................................................................ 2 
Acronyms and abbreviations............................................................................................................ 3 
1Package description ............................................................................................................... 4 
1.1 TO SMD package type..............................................................................................................................4 
1.2 TO THD package type..............................................................................................................................5 
1.3 HSOG package type.................................................................................................................................6 
1.4 Package features and general handling guidelines...............................................................................6 
2Printed circuit board .............................................................................................................10 
2.1 Routing ..................................................................................................................................................10 
2.2 Pad design .............................................................................................................................................10 
2.3 Via-in-pad design...................................................................................................................................11 
3Mounting of surface-mount devices ........................................................................................13 
3.1 Solder paste stencil...............................................................................................................................13 
3.2 Solder paste...........................................................................................................................................13 
3.3 Component placement of SMD.............................................................................................................14 
3.4 Reflow soldering....................................................................................................................................14 
3.5 Wave soldering of SMD..........................................................................................................................15 
4Mounting of through-hole devices...........................................................................................16 
4.1 Pre-mounting processes and mounting materials ..............................................................................16 
4.2 Component placement of THD.............................................................................................................19 
4.3 Heat sink mounting...............................................................................................................................19 
4.4 Soldering of THD ...................................................................................................................................23 
4.5 Alternative mounting methods.............................................................................................................24 
5Cleaning...............................................................................................................................25 
6Inspection ............................................................................................................................26 
6.1 Optical solder joint inspection..............................................................................................................26 
6.2 X-ray solder joint inspection.................................................................................................................27 
7Rework ................................................................................................................................28 
8References ...........................................................................................................................29 
Revision history.............................................................................................................................30 
 
 

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Acronyms and abbreviations

AOI ………………………………………… automated optical inspection

AXI ………………………………………… automated X-ray inspection

CSAM ………………………………………… c-scanning acoustic microscopy

DSO ………………………………………… dual small outline package

ESD ………………………………………… electrostatic discharge

HDSOP ………………………………………… heatspreader dual small outline package

HSOG ………………………………………… heatsink small outline gullwing

IGBT ………………………………………… insulated-gate bipolar transistor

I/O ………………………………………… input/output

K/W ………………………………………… Kelvin per Watts

MOSFET …..….….….…....….………….…..… metal-oxide-semiconductor field-effect transistor

MSL ……...………………………….……… moisture-sensitivity level

NSMD ……...………………………….……… non-solder mask defined

PG ………………………………………… plastic green

PCB ………………………………………… printed circuit board

SAC ………………………………………… tin silver copper (SnAgCu)

Si ………………………………………… silicon

SiC ………………………………………… silicon carbide

SMD ………………………………………… colder mask defined pad

SMD ………………………………………… surface-mount device

SMT ………………………………………… surface-mount technology

Sn ………………………………………… matte tin plating

TCoB ………………………………………… temperature cycling on board

THD ………………………………………… through-hole device

THT ………………………………………… through-hole technology

TO ………………………………………… transistor outline package

TOLG ………………………………………… transistor outline leaded with gullwing package

TOLT ………………………………………… transistor outline leaded top-side cooling package

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Package description

1Package description

This document provides information about the board assembly of Infineon transistor outline (TO) and heatsink

small outline gullwing (HSOG) packages by surface mount technology (SMT) and through-hole technology

(THT). TO packages are available as surface-mount devices (SMD) and through-hole devices (THD).

The I/O leads of the single-ended SMD packages are bent outwards from the package mold body side forming a

distinct “foot” and “heel” geometry. That “gullwing” shaped lead geometry can be mounted on the same board

surface together with the heat sink pad using fully automated processes.

The leads of THD are inserted in drilled holes of the board prior to soldering. Depending on the specific process

and technology, this may require certain pre-mount processing steps. The heat sink of THD package can either

be mounted on the board or can be equipped with an additional heatspreader.

The packages are optimized for silicon (Si) and silicon carbide (SiC) metal-oxide-semiconductor field-effect

transistor (MOSFET), insulated-gate bipolar transistor (IGBT), and Schottky diode devices for automotive and

industrial power applications and provide a high heat dissipation.

This document does not discuss dual small outline (DSO) or heatspreader dual small outline package (HDSOP)

from so called transistor outline leaded top-side cooling (TOLT) package family. These package families are

described in separate documents.

1.1 TO SMD package type

Infineon TO SMD packages are available as DPAK and D2PAK with with a mold body size of approx. 6 to 9 mm.

Infineon designations are following the standardized names TO-252 and TO-263 as given by JEDEC. Figure 1

shows examples of the TO SMD package family.

PG-TO252 DPAK

PG-TO263 D2PAK

PG = plastic green

TO = transistor outline

Figure 1 Examples of surface-mount TO packages.

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Package description

1.2 TO THD package type

Infineon TO SMD packages are available in various versions such as IPAK, I2PAK and else. Fully isolated package

versions without open metal lug are called “FullPAK”. There are package versions with screw mounting hole

and without it featuring an increased heatsink area (“Plus”version). Some packages feature leads with

extended or reduced length (“Long lead” and “Short lead” versions). Infineon designations are following the

standardized names from TO-220 to TO-262 as given by JEDEC. Figure 2 shows examples of the TO THD

package families.

PG-TO220

PG-TO220 FullPAK

PG-TO247

PG-TO247 Long lead

PG-TO247 Plus

PG-TO251 IPAK

PG-TO262 I²PAK

PG-TO273 Super 220

PG = plastic green

TO = transistor outline

Figure 2 Examples of through-hole TO packages.

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Package description

1.3 HSOG package type

Infineon heatsink small outline gullwing (HSOG) packages present a space optimized version of the TO263

(D2PAK) and are also called TO-Leaded with gullwing (TOLG). The tab thickness is reduced to decrease the

junction to case thermal resistance while the height shrink increases the power density. The gullwing lead

shape is preserved in contrast to leadless TO solutions in order to achieve high performance during

temperature cycling on board (TCoB). Figure 3 shows a HSOG package.

PG-HSOG

PG = plastic green

H = heatsink

SO = small outline

G = gullwing

Figure 3 Example of surface-mount HSOG package.

1.4 Package features and general handling guidelines

General handling guidelines

Semiconductor devices are sensitive to excessive electrostatic discharge (ESD), moisture, mechanical handling,

and contamination. Therefore, they require specific precautionary measures to ensure that they are not

damaged during transport, storage, handling, and processing.

For further information about component handling, please refer to the General Recommendations for Board

Assembly of Infineon Packages document that is available on the Infineon web page [1]. Please also feel free to

contact your local sales, application, or quality engineer.

Internal construction

The components of the TO SMD and HSOG package families feature plastic-encapsulated chips on a copper

leadframe using single-ended perimeter leads. An example of the inner setup of TO SMD or HSOG packages is

shown in Figure 4.

The TO THD components provide long strait leads for through-hole insertion. Large heat sink pads can protrude

the mold body outline or can terminate within it. An example of the inner setup of TO THT packages is shown in

Figure 5.

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Package description

Figure 4 Schematic showing the inner setup of a TO SMD package.

Figure 5 Schematic showing the inner setup of a TO THT package.

Thermal performance

The overall thermal performance of a package with a heat sink is characterized by a junction-to-ambient

thermal resistance Rthja. The Rthja can be calculated as shown in Figure 6 and Equation 1.

Figure 6 Thermal model of a TO package on a heatsink.

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Package description

𝑅𝑡ℎ 𝑗𝑎 = 𝑅𝑡ℎ 𝑗𝑐 + 𝑅𝑡ℎ 𝑐𝑠 + 𝑅𝑡ℎ 𝑠 + 𝑅𝑡ℎ 𝑠𝑎 (1)

Rth ja thermal resistance junction to ambient (K/W)

Rth jc thermal resistance junction to case (K/W) –specified in relevant datasheet

Rth cs thermal resistance case to sink (K/W)

Rth s thermal resistance sink (K/W)

Rth sa thermal resistance sink to ambient (K/W)

When mounting a package on an external heat spreader, it is important to consider the interface resistance

Rthcs. In real application cases, Rthcs will exceed the ideal value of 0. That is caused by small air gaps between the

package and the heat spreader that can have the following reasons:

Surface roughness and waviness of package heat sink and external heat spreader

Slight tilt between package heat sink and external heat spreader

For insulated packages such as the PG-TO220 FullPAK, the use of thermal grease is recommended to fill the air

gap between the package and the heat sink. Measurements have shown that the usage of thermal grease

reduces the interface resistance by 1.2 to 1.5 K/W.

In many applications, the package must be electrically isolated from its mounting surface. The isolation

material has a relatively high thermal resistance, which raises junction operating temperatures.

For further information about thermal performance, please refer to the Thermal performance of surface mount

semiconductor packagesdocument that is available on the Infineon web page [2]. Please also feel free to

contact your local sales, application, or quality engineer.

Termination design

The gullwing lead is considered to be one of the most reliable terminations for SMD. To form gullwing

terminations, the leads are bent outwards at the tip. These bent input/output (I/O) lead foot and heel areas

form the seating plane that is then soldered to the PCB. The leads as well as the heat sink pad feature a

solderable surface for board mounting. The distance between the I/O lead seating plane and the exposed pad

landing area at the package bottom is defined as the package stand-off. The single-ended gullwing lead row of

TO SMD will result in a non-symmetric stand-off between the lead landing area and the heat sink pad.

The solder joints are mainly formed underneath the package. The tips of such terminations often feature bare

copper (e.g. cut edges) and are therefore not intended to wet with solder by design according to IPC-A-610 [7].

Figure 7 Cross-section of a HSOG package lead with proper solder connection to board.

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Package description

Termination plating

Infineon TO SMD and HSOG packages with gullwing leads feature a matte tin (Sn) surface finish that is applied

to the base metal by a post-mold process. The solder connection is then made to the underlaying copper or

nickel.

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Printed circuit board

2Printed circuit board

This section addresses specifically the surface-mount TO SMD and HSOG packages.

2.1 Routing

Printed circuit board design and construction are key factors for achieving solder joints with high reliability.

Packages with exposed pads should not be placed opposite to each other on either side of a PCB when doing

double-sided mounting. This will stiffen the assembly and cause solder joints to fatigue earlier than in a design

in which the components are offset. Furthermore, the board stiffness itself has a significant influence on the

reliability of the solder joint interconnect if the system is used in critical temperature-cycling conditions

2.2 Pad design

The quality and reliability of interconnect solder joints to the board are affected by:

Pad type (solder mask defined, SMD or non-solder mask defined, NSMD)

Specific pad dimensions

Pad finish (also called metallization or final finish)

Via layout and technology

For optimal heat dissipation in high-current applications, the SMD pad type is preferred beause it allows for

large copper areas under the solder mask layer of the PCB. Beside the power application aspect, the SMD

design type can also be beneficial in terms of routing flexibility. Mixing different pad definition types in one

footprint is not recommended due to the typical alignment tolerances between the solder mask and the copper

layer.

It is generally possible to layout the board pad with the same dimensions as the exposed die pad of the

package. If the exposed die pad protrudes on one or more sides of the package body, it can be helpful to

increase the board pad slightly in this area to improve self-centering of the component during reflow soldering.

Figure 8 shows examples of pad and stencil designs for a PG-TO263-7-2 package without and with vias in pad.

Figure 8 Examples of a pad and stencil design for a PG-TO263-7-2 package without (left) and with

(right) vias in pad.

Ce manuel convient aux modèles suivants

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