Infineon PG-LQFP Manuel utilisateur

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Recommendations for Board Assembly of

Infineon Quad Flat Packages

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Recommendations for Board Assembly of Infineon Quad Flat

Packages

Table of Contents

Table of Contents ........................................................................................................................... 2

Acronyms and Abbreviations ........................................................................................................... 3

1Package Description............................................................................................................... 4

1.1 QFP Package Type...................................................................................................................................4

1.2 Package Features and General Handling Guidelines.............................................................................4

2Printed Circuit Board.............................................................................................................. 7

2.1 Routing ....................................................................................................................................................7

2.2 Pad Design...............................................................................................................................................7

2.3 Via-in-Pad Design ....................................................................................................................................9

3PCB Assembly .......................................................................................................................11

3.1 Solder Paste Stencil ..............................................................................................................................11

3.2 Solder Paste...........................................................................................................................................11

3.3 Component Placement.........................................................................................................................12

3.4 Reflow Soldering ...................................................................................................................................12

4Cleaning...............................................................................................................................14

5Inspection ............................................................................................................................15

5.1 Optical Solder Joint Inspection ............................................................................................................15

5.2 X-Ray Solder Joint Inspection...............................................................................................................15

6Rework ................................................................................................................................17

7References ...........................................................................................................................18

Revision History ............................................................................................................................19

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Acronyms and Abbreviations

AOI ………………………………………… Automated Optical Inspection

AXI ………………………………………… Automated X-ray Inspection

ESD ………………………………………… Electrostatic Discharge

IC ………………………………………… Integrated Circuit

I/O ………………………………………… Input/Output

LF ………………………………………… Lead Frame

LQFP ………………………………………… Low-profile Quad Flat Package

MQFP ………………………………………… Metric Quad Flat Packages

MSL ………………………………………… Moisture-Sensitivity Level

Ni/Pd/Au ……………………………………… Nickel/Palladium/Gold

NSMD ………………………………………… Non-Solder Mask Defined pad

PG ………………………………………… Plastic Green

PCB ………………………………………… Printed Circuit Board

PPF ………………………………………… Pre-Plated lead Frame

QFP ………………………………………… Quad-Flat Package

SAC ………………………………………… Tin Silver Copper (SnAgCu)

SMD ………………………………………… Solder Mask Defined

SMD ………………………………………… Surface-Mount Device

SMT ………………………………………… Surface-Mount Technology

Sn ………………………………………… matte tin plating

TQFP ………………………………………… Thin Quad Flat Packages

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Recommendations for Board Assembly of Infineon Quad Flat

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Package Description

1Package Description

This recommendation provides information about the board assembly of Infineon Quad Flat Packages (QFP) by

Surface Mount Technology (SMT). The typical gullwing leads are arranged on all four sides of the package mold

body. An exposed die pad in the center of the package landing allows for optimum heat transfer and electrical

grounding. The reliable setup and high lead count of QFP makes them ideal carriers for microcontroller or gate

driver Integrated Circuits (IC).

This document does not discuss other Infineon dual row packages with gullwing leads. These package families

are described in a separate document.

1.1 QFP Package Type

Infineon QFP come with different total heights and lead pitches. The typical pitch of Low-profile Quad Flat

Packages (LQFP) and Thin Quad Flat Packages (TQFP) is of 0.5 mm. The latter also provides a pitch down to

0.4 mm. Metric Quad Flat Packages (MQFP) have a typical pitch of 0.65 mm up to 0.8 mm. Figure 1 shows

representatives of the QFP package families.

PG-LQFP

PG-MQFP

PG-TQFP

PG = Plastic Green

L = Low-profile

M = Metric

T = Thin

QFP = Quad Flat Package

Figure 1 Examples of QFP packages.

1.2 Package Features and General Handling Guidelines

General Handling Guidelines

Semiconductor devices are sensitive to excessive electrostatic discharge (ESD), certain moisture levels,

mechanical handling, and contamination. Therefore, they require specific precautionary measures to ensure

that they are not damaged during transport, storage, handling, and processing.

For further information about component handling, please refer to the General Recommendations for Board

Assembly of Infineon Packages document that is available on the Infineon web page [1]. Please also feel free to

contact your local sales, application, or quality engineer.

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Package Description

Internal Construction

Infineon QFP are plastic encapsulated lead frame packages. Most of them have an exposed die pad on the

bottom of the package, which is created by an appropriate lead frame down-set. The exposed pads are usually

soldered to the Printed Circuit Board (PCB) for mechanical, electrical and thermal connection. Figure 2 shows

the typical setup of QFP with and without exposed die pad.

Figure 2 Schematics showing the inner setup of a QFP without (top) and with exposed die pad

(bottom).

Termination Design

The gullwing lead is considered to be one of the most reliable terminations for Surface-Mount Devices (SMD).

To form gullwing terminations, the leads are bent outwards at the tip. These bent Input/Output (I/O) lead foot

and heel areas form the seating plane that is then soldered to the PCB.

The distance between the I/O lead seating plane and the exposed pad landing area at the package bottom is

defined as the package stand-off. On QFP it can vary around the nominal value of 100 µm by ±50 µm.

Consequences to the board assembly are discussed in the following sections.

Termination Plating

Infineon QFP are available with matte tin (Sn) surface finish or with a Pre-Plated lead Frame (PPF). While the

Sn-plating is applied to the base metal by a post-mold process, the PPF provides a solderable surface that is

already deposited on the lead frame prior to the die attach process. The PPF surfaces basically consist of a

nickel/palladium/gold (Ni/Pd/Au) stack-up. While the Sn melts during reflow, the sacrificial Au layer of the PPF

surface is dissolved. The solder connection is then made with the Ni layer.

Figure 3 shows cross-sections of gullwing leads with Sn plated and PPF surface. While the appearance of solder

wetted PPF surfaces is slightly different to Sn surfaces it is in full agreement with IPC-A-610 standard [6]. Images

of the outer solder joint appearance can be found in Figure 8.

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Recommendations for Board Assembly of Infineon Quad Flat

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Package Description

Figure 3 Soldered gullwing leads with post-mold plated Sn (left) and with pre-plated Ni/Pd/Au

(right).

For further information about the specific component configuration, please contact your local Infineon sales,

application, or quality engineer.

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Printed Circuit Board

2Printed Circuit Board

2.1 Routing

Printed circuit board design and construction are key factors for achieving solder joints with high reliability.

Packages with exposed pads should not be placed opposite to each other on either side of a PCB when doing

double-sided mounting. This will stiffen the assembly and cause solder joints to fatigue earlier than in a design

in which the components are offset. Furthermore, the board stiffness itself has a significant influence on the

reliability of the solder joint interconnect if the system is used in critical temperature-cycling conditions.

2.2 Pad Design

The quality and reliability of interconnect solder joints to the board are affected by:

Pad type (Solder-Mask Defined, SMD or Non-Solder-Mask Defined, NSMD)

Specific pad dimensions

Pad finish (also called metallization or final finish)

Via layout and technology

The NSMD pad design is recommended for QFP components. The approach applies to the peripheral

terminations as well as to the exposed pads. Mixing different pad definition types in one footprint is not

recommended.

The exposed pads of QFP can feature anti-flash profiles. These are meander structures at the outline of the pad

to taper off potential mold flash during fabrication process. In Figure 4 such an anti-flash profile is shown.

Despite that structure, the exposed pad outline is used for soldering purpose as can be seen in Figure 5.

Besides their electrical function, the exposed pad areas of QFP packages are designed to conduct high thermal

loads into the PCB in order to achieve an optimal thermal performance. Therefore, the exposed pad area on the

PCB should be congruent with the area on the package at minimum. Using a PCB pad of the same size as the

package exposed pad will also increase the solder joint reliability, and the electrical performance for some

applications. Figure 5 shows an example of print pattern on a PCB pad for a die pad connection including

thermal vias.

Figure 4 QFP with anti-flash profile in the exposed pad. The outer extension of the exposed pad

including the anti-flash profile should be used as the reference for the PCB pad design.

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Printed Circuit Board

Figure 5 Example of a pads and stencil design for QFP. The outer extension of the exposed pad

including the anti-flash profile is used as the reference for the PCB pad (left). Potential

vias-in-pad should be placed in between the stencil apertures to avoid solder flowing into

the vias (right).

Figure 6 shows schematic depictions of the backward PCB pad extension at the gullwing lead heel that is

necessary for an optimal solder fillet formation. According to the IPC-A-610 the minimum solder wetting height

shall reach an extended line projected from the lead tip top corner in parallel to the PCB pad plane [6]. As a rule

of thumb often the line parallel to the lead top plane is used to take into account the lower bend angle.

The PCB pad and therefore the solder paste print should have a distinct distance to the package mold in order

to avoid an unclean solder process as it is induced by e.g. solder spatters.

Generally, an optimal PCB design depends on the specific application as well as on the specific design rules of

the chosen board manufacturer.

Figure 6 Schematic depiction of a QFP mounted on a PCB. There are two critical parameters to

consider. First is the package stand-off between the landing plane of the exposed pad and

the copper plane of the PCB. The second is the pad extension for optimal solder fillet

formation at the gullwing heel according to the IPC-A-610 [6].

For further information about PCB pad design, please refer to the General Recommendations for Borad Assembly

of Infineon Packages document that is available on the Infineon web page [1]. Please also feel free to contact

your local sales, application, or quality engineer.

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Printed Circuit Board

Further details and specific footprint recommendations can be found in Infineon package data that is available

on the Infineon web page [1]. Please choose a specific package when searching the data base, which will then

show you an example of the stencil aperture layout for each package.

2.3 Via-in-Pad Design

Thermal and electrical connections to the inner and/or bottom copper planes of the PCB are usually created by

plated through-hole vias in the board. The heat is then transferred from the chip over the package die pad and

the solder joint to the thermal pad on the board and further through the PCB by the thermal vias.

The diameter and the number of vias in the thermal pad depend on the specific thermal requirements of the

final product, the power consumption of the product, the application, and the construction of the PCB. A

typical hole diameter for thermal vias is 0.2 - 0.5 mm. An array with 1.0 - 1.2 mm pitch can be a reasonable

starting point for further design optimization. The implementation of thermal vias has several impacts on the

board assembly as outlined below. A constant increase of number of vias does not necessarily translate into a

constant decrease of the thermal resistance of the entire assembly set-up. Thermal and electrical analysis

and/or testing together with a proper board assembly design procedure are recommended to determine the

optimum number of vias needed.

One of the primary exposed pad design objectives, besides the thermal management, should be to avoid the

penetration of the vias by solder. Consequences of solder penetration can be a decreased stand-off between

the PCB and the package, an increased void formation ultimately resulting in an insufficient solder joint area, or

surplus solder on the opposite side of the PCB.

A first approach for risk reduction should be the prevention of a direct print of solder paste on the via orifice.

Since the stencil for large area prints such as on die pads is usually segmented, it is a good practice to position

the vias under the beam intersections of the aperture as shown in Figure 5. With such an approach, a good

solder joint on a central die pad can be formed using vias that remain open on both sides of the board.

Despite the precautionary stencil design approach, the solder can move into the via, driven by the wetting

forces. If the solder then protrudes to the opposite side of the PCB, it may interfere with a second solder paste

print process. To minimize the effect, dummy areas on the opposite side as shown in Figure 7 can catch the

surplus solder to avoid beading and solder lumping.

Figure 7 Wettable “dummy” area on the opposite side of the board surrounds the vias to act as a

buffer for surplus solder.

In case the solder variance in volume below the die pad is too high due to the wetting of vias, they can be

closed by “tenting.” This process includes covering the vias by a solder mask (e.g. dry-film solder mask). If the

via tenting is done only on the opposite side of the board, the voiding rate will increase significantly. Another

method to close vias is called “plugging” (filling with epoxy), followed by overplating. Very small vias (100 µm in

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Printed Circuit Board

diameter or smaller) should be filled with copper and be overplated. In both cases, the specification of a planar

filling is necessary to avoid cavities that will trap gases, forming voids during reflow soldering.

In case it is not necessary to provide a direct connection from the solder pad under the exposed die pad to the

inner layers of the PCB, the vias can be placed next to the footprint near the package and covered with solder

mask.

For further information about vias in pad, please refer to the General Recommendations for Board Assembly of

Infineon Packages document that is available on the Infineon web page [1]. Please also feel free to contact your

local sales, application, or quality engineer.

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