Freescale Semiconductor PowerPC e500 Core Manuel utilisateur

PowerPC™ e500 Core

Family Reference Manual

Supports

e500v1

e500v2

E500CORERM

Rev. 1, 4/2005

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Document Number: E500CORERM

Rev. 1, 4/2005

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Part I—e500 Core I

Core Complex Overview 1

Instruction Model 3

Execution Timing 4

Interrupts and Exceptions 5

Power Management 6

Performance Monitor 7

Debug Support 8

Part II—e500 Core Complex II

Timer Facilities 9

Auxiliary Processing Units (APUs) 10

L1 Caches 11

Memory Management Units 12

Core Complex Bus (CCB) 13

Appendix A—Programming Examples A

Appendix B—Guidelines for 32-Bit Book E B

Appendix C—Simplified Mnemonics for PowerPC Instructions C

Appendix D—Opcode Listings D

Appendix E—Revision History E

Index IND

IPart I—e500 Core

1Core Complex Overview

2Register Model

3Instruction Model

41Execution Timing

5Interrupts and Exceptions

6Power Management

7Performance Monitor

8Debug Support

II Part II—e500 Core Complex

9Timer Facilities

10 Auxiliary Processing Units (APUs)

11 L1 Caches

12 Memory Management Units

13 Core Complex Bus (CCB)

AAppendix A—Programming Examples

BAppendix B—Guidelines for 32-Bit Book E

CAppendix C—Simplified Mnemonics for PowerPC Instructions

DAppendix D—Opcode Listings

EAppendix E—Revision History

IND Index

PowerPC e500 Core Family Reference Manual, Rev. 1

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Contents

Paragraph

Number Title

Page

Number

Co nt en t s

About This Book

Audience.......................................................................................................................xxxii

Organization.................................................................................................................. xxxii

Suggested Reading....................................................................................................... xxxiii

General Information............................................................................................. xxxiii

Related Documentation ....................................................................................... xxxiv

Conventions ................................................................................................................. xxxiv

Terminology Conventions..............................................................................................xxxv

Part I

e500 Core

Chapter 1

Core Complex Overview

1.1 Overview.......................................................................................................................... 1-1

1.1.1 Upward Compatibility ................................................................................................. 1-3

1.1.2 Core Complex Summary ............................................................................................. 1-3

1.2 e500 Processor and System Version Numbers.................................................................1-5

1.3 Features............................................................................................................................1-5

1.3.1 e500v2 Differences.................................................................................................... 1-11

1.4 Instruction Set................................................................................................................1-12

1.5 Instruction Flow.............................................................................................................1-14

1.5.1 Initial Instruction Fetch.............................................................................................. 1-14

1.5.2 Branch Detection and Prediction............................................................................... 1-14

1.5.3 e500 Execution Pipeline ............................................................................................ 1-16

1.6 Programming Model...................................................................................................... 1-18

1.7 On-Chip Cache Implementation.................................................................................... 1-20

1.8 Interrupts and Exception Handling................................................................................ 1-20

1.8.1 Exception Handling ................................................................................................... 1-20

1.8.2 Interrupt Classes ........................................................................................................ 1-21

1.8.3 Interrupt Types........................................................................................................... 1-21

1.8.4 Upper Bound on Interrupt Latencies ......................................................................... 1-22

1.8.5 Interrupt Registers...................................................................................................... 1-22

1.9 Memory Management.................................................................................................... 1-24

1.9.1 Address Translation ................................................................................................... 1-26

1.9.2 MMU Assist Registers (MAS0–MAS4 and MAS6–MAS7).....................................1-27

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1.9.3 Process ID Registers (PID0–PID2)............................................................................ 1-28

1.9.4 TLB Coherency.......................................................................................................... 1-28

1.10 Memory Coherency ....................................................................................................... 1-29

1.10.1 Atomic Update Memory References ......................................................................... 1-29

1.10.2 Memory Access Ordering.......................................................................................... 1-29

1.10.3 Cache Control Instructions ........................................................................................ 1-29

1.10.4 Programmable Page Characteristics .......................................................................... 1-30

1.11 Core Complex Bus (CCB) ............................................................................................. 1-30

1.12 Performance Monitoring................................................................................................ 1-30

1.12.1 Global Control Register............................................................................................. 1-31

1.12.2 Performance Monitor Counter Registers................................................................... 1-31

1.12.3 Local Control Registers............................................................................................. 1-31

1.13 Legacy Support of PowerPC Architecture..................................................................... 1-32

1.13.1 Instruction Set Compatibility..................................................................................... 1-32

1.13.1.1 User Instruction Set ............................................................................................... 1-32

1.13.1.2 Supervisor Instruction Set...................................................................................... 1-32

1.13.2 Memory Subsystem ................................................................................................... 1-33

1.13.3 Exception Handling ................................................................................................... 1-33

1.13.4 Memory Management................................................................................................ 1-33

1.13.5 Reset...........................................................................................................................1-34

1.13.6 Little-Endian Mode.................................................................................................... 1-34

Chapter 2

2.1 Overview.......................................................................................................................... 2-1

2.2 e500 Register Model........................................................................................................ 2-2

2.2.1 Special-Purpose Registers (SPRs) ............................................................................... 2-5

2.3 Registers for Integer Operations...................................................................................... 2-9

2.3.1 General-Purpose Registers (GPRs).............................................................................. 2-9

2.3.2 Integer Exception Register (XER)............................................................................... 2-9

2.4 Registers for Branch Operations...................................................................................... 2-9

2.4.1 Condition Register (CR).............................................................................................. 2-9

2.4.2 Link Register (LR)..................................................................................................... 2-10

2.4.3 Count Register (CTR)................................................................................................ 2-10

2.5 Processor Control Registers........................................................................................... 2-10

2.5.1 Machine State Register (MSR).................................................................................. 2-10

2.5.2 Processor ID Register (PIR) ...................................................................................... 2-12

2.5.3 Processor Version Register (PVR)............................................................................. 2-13

2.5.4 System Version Register (SVR)................................................................................. 2-13

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2.6 Timer Registers..............................................................................................................2-14

2.6.1 Timer Control Register (TCR)................................................................................... 2-15

2.6.2 Timer Status Register (TSR)...................................................................................... 2-16

2.6.3 Time Base (TBU and TBL) ....................................................................................... 2-16

2.6.4 Decrementer Register (DEC)..................................................................................... 2-16

2.6.5 Decrementer Auto-Reload Register (DECAR)..........................................................2-16

2.6.6 Alternate Time Base Registers (ATBL and ATBU)................................................... 2-16

2.6.6.1 Alternate Time Base Upper (ATBU) ..................................................................... 2-17

2.7 Interrupt Registers..........................................................................................................2-17

2.7.1 Interrupt Registers Defined by Book E......................................................................2-18

2.7.1.1 Save/Restore Register 0/1 (SRR0 and SRR1) .......................................................2-18

2.7.1.2 Critical Save/Restore Register 0/1 (CSRR0 and CSRR1)..................................... 2-18

2.7.1.3 Data Exception Address Register (DEAR)............................................................ 2-18

2.7.1.4 Interrupt Vector Prefix Register (IVPR)................................................................ 2-19

2.7.1.5 Interrupt Vector Offset Registers (IVORs)............................................................ 2-19

2.7.1.6 Exception Syndrome Register (ESR) ....................................................................2-20

2.7.2 e500-Specific Interrupt Registers .............................................................................. 2-22

2.7.2.1 Machine Check Save/Restore Register 0 (MCSRR0)...........................................2-22

2.7.2.2 Machine Check Save/Restore Register 1 (MCSRR1)...........................................2-22

2.7.2.3 Machine Check Address Register (MCAR) .......................................................... 2-22

2.7.2.4 Machine Check Syndrome Register (MCSR)........................................................ 2-23

2.8 Software-Use SPRs (SPRG0–SPRG7 and USPRG0) ................................................... 2-24

2.9 Branch Target Buffer (BTB) Registers.......................................................................... 2-24

2.9.1 Branch Buffer Entry Address Register (BBEAR) ..................................................... 2-25

2.9.2 Branch Buffer Target Address Register (BBTAR)....................................................2-25

2.9.3 Branch Unit Control and Status Register (BUCSR)..................................................2-26

2.10 Hardware Implementation-Dependent Registers...........................................................2-27

2.10.1 Hardware Implementation-Dependent Register 0 (HID0).........................................2-27

2.10.2 Hardware Implementation-Dependent Register 1 (HID1).........................................2-29

2.11 L1 Cache Configuration Registers................................................................................. 2-31

2.11.1 L1 Cache Control and Status Register 0 (L1CSR0) .................................................. 2-31

2.11.2 L1 Cache Control and Status Register 1 (L1CSR1) .................................................. 2-33

2.11.3 L1 Cache Configuration Register 0 (L1CFG0) .........................................................2-34

2.11.4 L1 Cache Configuration Register 1 (L1CFG1) .........................................................2-35

2.12 MMU Registers.............................................................................................................. 2-35

2.12.1 Process ID Registers (PID0–PID2)............................................................................ 2-36

2.12.2 MMU Control and Status Register 0 (MMUCSR0)..................................................2-36

2.12.3 MMU Configuration Register (MMUCFG) .............................................................. 2-37

PowerPC e500 Core Family Reference Manual, Rev. 1

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2.12.4 TLB Configuration Registers (TLBnCFG) ............................................................... 2-37

2.12.4.1 TLB0 Configuration Register (TLB0CFG)...........................................................2-38

2.12.4.2 TLB1 Configuration Register 1 (TLB1CFG)........................................................2-39

2.12.5 MMU Assist Registers (MAS0–MAS4, MAS6–MAS7) .......................................... 2-39

2.12.5.1 MAS Register 0 (MAS0)....................................................................................... 2-40

2.12.5.2 MAS Register 1 (MAS1)....................................................................................... 2-41

2.12.5.3 MAS Register 2 (MAS2)....................................................................................... 2-42

2.12.5.4 MAS Register 3 (MAS3)....................................................................................... 2-43

2.12.5.5 MAS Register 4 (MAS4)....................................................................................... 2-43

2.12.5.6 MAS Register 6 (MAS6)....................................................................................... 2-44

2.12.5.7 MAS Register 7 (MAS7)—e500v2 Only..............................................................2-45

2.13 Debug Registers.............................................................................................................2-45

2.13.1 Debug Control Registers (DBCR0–DBCR2)............................................................ 2-46

2.13.1.1 Debug Control Register 0 (DBCR0)......................................................................2-46

2.13.1.2 Debug Control Register 1 (DBCR1)......................................................................2-46

2.13.1.3 Debug Control Register 2 (DBCR2)......................................................................2-47

2.13.2 Debug Status Register (DBSR).................................................................................. 2-47

2.13.3 Instruction Address Compare Registers (IAC1–IAC4).............................................2-48

2.13.4 Data Address Compare Registers (DAC1–DAC2).................................................... 2-48

2.14 SPE and SPFP APU Registers....................................................................................... 2-49

2.14.1 Signal Processing and Embedded Floating-Point Status and Control

2.14.2 Accumulator (ACC)................................................................................................... 2-52

2.15 Performance Monitor Registers (PMRs) ....................................................................... 2-52

2.15.1 Global Control Register 0 (PMGC0)......................................................................... 2-53

2.15.2 User Global Control Register 0 (UPMGC0).............................................................. 2-54

2.15.3 Local Control A Registers (PMLCa0–PMLCa3) ...................................................... 2-55

2.15.4 User Local Control A Registers (UPMLCa0–UPMLCa3)........................................2-56

2.15.5 Local Control B Registers (PMLCb0–PMLCb3)...................................................... 2-56

2.15.6 User Local Control B Registers (UPMLCb0–UPMLCb3)........................................ 2-57

2.15.7 Performance Monitor Counter Registers (PMC0–PMC3).........................................2-57

2.15.8 User Performance Monitor Counter Registers (UPMC0–UPMC3).......................... 2-58

2.16 Synchronization Requirements for SPRs....................................................................... 2-58

Chapter 3

Instruction Model

3.1 Operand Conventions ...................................................................................................... 3-1

3.1.1 Data Organization in Memory and Data Transfers......................................................3-1

3.1.2 Alignment and Misaligned Accesses........................................................................... 3-2

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3.1.3 e500 Floating-Point Implementation ........................................................................... 3-2

3.1.4 Unsupported Book E Instructions................................................................................ 3-3

3.2 Instruction Set Summary ................................................................................................. 3-5

3.2.1 Classes of Instructions ................................................................................................. 3-6

3.2.2 Definition of Boundedly Undefined............................................................................ 3-6

3.2.3 Synchronization Requirements.................................................................................... 3-6

3.2.3.1 Synchronization Requirements for e500-Specific SPRs .........................................3-8

3.2.3.2 Synchronization with tlbwe and tlbivax Instructions...........................................3-10

3.2.3.3 Context Synchronization ....................................................................................... 3-11

3.2.3.4 Execution Synchronization.................................................................................... 3-11

3.2.3.5 Instruction-Related Interrupts................................................................................ 3-12

3.3 Instruction Set Overview ............................................................................................... 3-13

3.3.1 Book E User-Level Instructions ................................................................................ 3-13

3.3.1.1 Integer Instructions................................................................................................ 3-13

3.3.1.1.1 Integer Arithmetic Instructions.......................................................................... 3-13

3.3.1.1.2 Integer Compare Instructions ............................................................................ 3-15

3.3.1.1.3 Integer Logical Instructions............................................................................... 3-15

3.3.1.1.4 Integer Rotate and Shift Instructions................................................................. 3-16

3.3.1.2 Load and Store Instructions................................................................................... 3-17

3.3.1.2.1 Self-Modifying Code......................................................................................... 3-17

3.3.1.2.2 Integer Load and Store Address Generation......................................................3-18

3.3.1.2.3 Integer Load Instructions................................................................................... 3-20

3.3.1.2.4 Integer Store Instructions................................................................................... 3-21

3.3.1.2.5 Integer Load and Store with Byte-Reverse Instructions.................................... 3-22

3.3.1.2.6 Integer Load and Store Multiple Instructions.................................................... 3-22

3.3.1.3 Branch and Flow Control Instructions................................................................... 3-23

3.3.1.3.1 Conditional Branch Control............................................................................... 3-23

3.3.1.3.2 Branch Instructions............................................................................................ 3-24

3.3.1.3.3 Condition Register Logical Instructions............................................................ 3-25

3.3.1.3.4 Trap Instructions................................................................................................ 3-25

3.3.1.4 System Linkage Instruction................................................................................... 3-26

3.3.1.5 Processor Control Instructions............................................................................... 3-26

3.3.1.5.1 Move to/from Condition Register Instructions.................................................. 3-26

3.3.1.5.2 Move to/from Special-Purpose Register Instructions........................................ 3-26

3.3.1.6 Memory Synchronization Instructions .................................................................. 3-30

3.3.1.6.1 mbar (MO = 1).................................................................................................. 3-31

3.3.1.7 Atomic Update Primitives Using lwarx and stwcx............................................... 3-32

3.3.1.7.1 Reservations....................................................................................................... 3-34

3.3.1.7.2 Forward Progress............................................................................................... 3-36

3.3.1.7.3 Reservation Loss Due to Granularity ................................................................ 3-36

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3.3.1.8 Memory Control Instructions ................................................................................ 3-37

3.3.1.8.1 User-Level Cache Instructions .......................................................................... 3-37

3.3.2 Supervisor-Level Instructions.................................................................................... 3-39

3.3.2.1 System Linkage Instructions.................................................................................. 3-39

3.3.2.2 Supervisor-Level Memory Control Instructions.................................................... 3-40

3.3.2.2.1 Supervisor-Level Cache Instruction .................................................................. 3-40

3.3.2.2.2 Supervisor-Level TLB Management Instructions.............................................3-41

3.3.3 Recommended Simplified Mnemonics...................................................................... 3-42

3.3.4 Book E Instructions with Implementation-Specific Features.................................... 3-43

3.3.5 e500 Instructions........................................................................................................ 3-43

3.3.6 Context Synchronization............................................................................................ 3-44

3.4 Memory Access Alignment Support.............................................................................. 3-44

3.5 Using msync and mbar to Order Memory Accesses....................................................3-45

3.5.1 Lock Acquisition and Import Barriers....................................................................... 3-45

3.5.1.1 Acquire Lock and Import Shared Memory............................................................ 3-45

3.5.1.2 Obtain Pointer and Import Shared Memory .......................................................... 3-45

3.5.1.3 Lock Release and Export Barriers......................................................................... 3-46

3.5.1.3.1 Export Shared Memory and Release Lock........................................................3-46

3.5.1.3.2 Export Shared Memory and Release Lock using mbar (MO = 0).................... 3-47

3.5.2 Safe Fetch ..................................................................................................................3-47

3.6 Update Instructions........................................................................................................ 3-47

3.7 Memory Synchronization .............................................................................................. 3-48

3.8 EIS-Defined Instructions and APUs Implemented on the e500 .................................... 3-48

3.8.1 SPE and Embedded Floating-Point APUs................................................................. 3-49

3.8.1.1 SPE Operands: Signed Fractions........................................................................... 3-51

3.8.1.2 SPE Integer and Fractional Operations.................................................................. 3-52

3.8.1.3 SPE APU Instructions............................................................................................ 3-52

3.8.1.4 Embedded Floating-Point APU Instructions.........................................................3-58

3.8.2 Integer Select (isel) APU........................................................................................... 3-60

3.8.3 Performance Monitor APU........................................................................................ 3-60

3.8.4 Cache Locking APU.................................................................................................. 3-61

3.8.5 Machine Check APU ................................................................................................. 3-63

3.9 e500-Specific Instructions ............................................................................................. 3-63

3.9.1 Branch Target Buffer (BTB) Locking Instructions.................................................... 3-63

3.10 Instruction Listing.......................................................................................................... 3-66

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