Epson S5U13A04B00C Manuel utilisateur

Rev. 3.1

S1D13A04 LCD/USB Companion Chip

S5U13A04B00C Rev. 1.0

Evaluation Board User Manual

Document Number: X37A-G-004-03.1

NOTICE

No part of this material may be reproduced or duplicated in any form or by any means without the written permission

of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does

not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application

or use in any product or circuit and, further, there is no representation that this material is applicable to products

requiring high level reliability, such as, medical products. Moreover, no license to any intellectual property rights

is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance

with this material will be free from any patent or copyright infringement of a third party. When exporting the

products or technology described in this material, you should comply with the applicable export control laws and

regulations and follow the procedures required by such laws and regulations. You are requested not to use, to resell,

to export and/or to otherwise dispose of the products (and any technical information furnished, if any) for the devel-

opment and/or manufacture of weapon of mass destruction or for other military purposes.

All brands or product names mentioned herein are trademarks and/or registered trademarks of their respective

companies.

Evaluation Board/Kit and Development Tool Important Notice

1. This evaluation board/kit or development tool is designed for use for engineering evaluation, demonstration, or develop-

ment purposes only. Do not use it for other purposes. It is not intended to meet the requirements of design for finished

products.

2. This evaluation board/kit or development tool is intended for use by an electronics engineer and is not a consumer product.

The user should use it properly and in a safe manner. Seiko Epson does not assume any responsibility or liability of any

kind of damage and/or fire caused by the use of it. The user should cease to use it when any abnormal issue occurs even

during proper and safe use.

3. The part used for this evaluation board/kit or development tool may be changed without any notice.

2Seiko Epson Corporation S5U13A04B00C Rev 1.0 Evaluation Board

Rev. 3.1

S5U13A04B00C Rev 1.0 Evaluation Board Seiko Epson Corporation 3

Rev. 3.1

Table of Contents

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

3 Installation and Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3.1 Configuration DIP Switches . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3.2 Configuration Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

4 CPU Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

4.1 CPU Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . 12

4.2 CPU Bus Connector Pin Mapping . . . . . . . . . . . . . . . . . . . . . . 13

5 LCD Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

6 Technical Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

6.1 PCI Bus Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

6.2 Direct Host Bus Interface Support . . . . . . . . . . . . . . . . . . . . . . 18

6.3 S1D13A04 Embedded Memory . . . . . . . . . . . . . . . . . . . . . . . 18

6.4 Adjustable LCD Panel Negative Power Supply . . . . . . . . . . . . . . . . . 18

6.5 Adjustable LCD Panel Positive Power Supply . . . . . . . . . . . . . . . . . . 19

6.6 Software Adjustable LCD Backlight Intensity Support Using PWM . . . . . . . . . 19

6.7 LCD Panel Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

6.7.1 Direct LCD Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

6.7.2 Extended LCD Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

6.8 USB Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

6.8.1 USB IRQ Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

7 Clock Synthesizer and Clock Options . . . . . . . . . . . . . . . . . . . . . . . . 21

7.1 Clock Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

8 Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

9 Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

10 Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

11 Change Record . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

12 Sales and Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

4Seiko Epson Corporation S5U13A04B00C Rev 1.0 Evaluation Board

Rev. 3.1

Introduction

S5U13A04B00C Rev 1.0 Evaluation Board Seiko Epson Corporation 5

Rev. 3.1

1 Introduction

This manual describes the setup and operation of the S5U13A04B00C Rev. 1.0 Evaluation

Board. The board is designed as an evaluation platform for the S1D13A04 LCD/USB

Companion Chip.

This document is updated as appropriate. Please check for the latest revision of this

document before beginning any development. The latest revision can be downloaded at

vdc.epson.com.

We appreciate your comments on our documentation. Please contact us via email at

vdc-documentation@ea.epson.com.

Features

6Seiko Epson Corporation S5U13A04B00C Rev 1.0 Evaluation Board

Rev. 3.1

2 Features

Following are some features of the S5U13A04B00C Rev. 1.0 Evaluation Board:

• 121-pin PFBGA S1D13A04 Embedded Memory LCD Controller with 160K bytes of

embedded SRAM.

• PCI bus operation through onboard PCI bridge.

• CPU/Bus interface header strips for non-PCI bus operation.

• Configuration options.

• On-board adjustable positive LCD bias power supply from +23V to +40V.

• On-board adjustable negative LCD bias power supply from -14V to -24V.

• Software adjustable backlight intensity support using PWMOUT.

• 4/8-bit 3.3V or 5V single monochrome passive LCD panel support.

• 4/8/16-bit 3.3V or 5V single color passive LCD panel support.

• 9/12/18-bit 3.3V or 5V active matrix TFT LCD panel support.

• Direct interface for 18-bit Epson D-TFD LCD panel support.

• Direct interface for 18-bit Sharp HR-TFT LCD panel support.

• Programmable clock synthesizer to CLKI and CLKI2 for maximum clock flexibility.

• Connector for USB client support.

• Software initiated power save mode.

• Selectable clock source for CLKI and CLKI2.

• External oscillator support for CLKI and CLKI2.

Installation and Configuration

S5U13A04B00C Rev 1.0 Evaluation Board Seiko Epson Corporation 7

Rev. 3.1

3 Installation and Configuration

The S5U13A04B00C is designed to support as many platforms as possible. The

S5U13A04B00C incorporates a DIP switch and five jumpers which allow both the evalu-

ation board and the S1D13A04 LCD controller to be configured for a specified evaluation

platform.

3.1 Configuration DIP Switches

The S1D13A04 has configuration inputs (CNF[6:0]) which are read on the rising edge of

RESET#. In order to configure the S1D13A04 for multiple Host Bus Interfaces an eight-

position DIP switch (SW1) is required. The following figure shows the location of DIP

switch SW1 on the S5U13A04B00C.

Figure 3-1: Configuration DIP Switch (SW1) Location

DIP Switch - SW1

Installation and Configuration

8Seiko Epson Corporation S5U13A04B00C Rev 1.0 Evaluation Board

Rev. 3.1

The S1D13A04 has seven configuration inputs (CONF[6:0]) which are read on the rising

edge of RESET#. All S1D13A04 configuration inputs are fully configurable using an eight

position DIP switch as described below.

Table 3-1: Configuration DIP Switch Settings

Switch

(SW1)

S1D13A04

Signal

Value on this pin at rising edge of RESET# is used to configure:

Closed (On/1) Open (Off/0)

SW1-5,

SW1-[3:1]

CNF4,

CNF[2:0]

Select host bus interface as follows:

CNF4 CNF2 CNF1 CNF0 Host Bus Interface

1 0 0 0 SH-4/SH-3 interface, Big Endian

0 0 0 0 SH-4/SH-3 interface, Little Endian

1 0 0 1 MC68K #1, Big Endian

0 0 0 1 Reserved

1 0 1 0 MC68K #2, Big Endian

0 0 1 0 Reserved

1 0 1 1 Generic #1, Big Endian

0 0 1 1 Generic #1, Little Endian

1 1 0 0 Reserved

0 1 0 0 Generic #2, Little Endian

1 1 0 1 RedCap 2, Big Endian

0 1 0 1 Reserved

1 1 1 0 DragonBall, Big Endian

0 1 1 0 Reserved

X 1 1 1 Reserved

SW1-4 CNF3 Configure GPIO pins as inputs at power-on

Configure GPIO[7:6] and GPIO[4:0] as outputs

and GPIO5 as an input at power-on (for use

when USB is selected)

SW1-6 CNF5 WAIT# is active high WAIT# is active low

SW1-7 CNF6 CLKI to BCLK Divide ratio 2:1 CLKI to BCLK divide ratio 1:1

SW1-8 - Disable PCI bridge for non-PCI host Enable PCI bridge for PCI host

= Required settings when used with PCI Bridge FPGA

Installation and Configuration

S5U13A04B00C Rev 1.0 Evaluation Board Seiko Epson Corporation 9

Rev. 3.1

3.2 Configuration Jumpers

The S5U13A04B00C has five jumper blocks which configure various setting on the board.

The jumper positions for each function are shown below.

JP1 - CLKI Source

JP1 selects the source for the CLKI input pin.

Position 1-2 sets the CLKI source to VCLKOUT from the Cypress clock synthesizer

(default setting).

Position 2-3 sets the CLKI source to the external oscillator at U7.

When no jumper is installed, the CLKI source is set to the BUSCLK signal from Header

H4.

Figure 3-2: Configuration Jumper (JP1) Location

Table 3-2: Jumper Summary

Jumper Function Position 1-2 Position 2-3 No Jumper

JP1 CLKI Source VCLKOUT from clock

synthesizer External oscillator (U7) BUSCLK from Header H4

JP2 CLKI2 Source MCLKOUT from clock

synthesizer External oscillator (U8) —

JP3 LCD Panel Voltage +5V LCDVCC +3.3V LCDVCC —

JP4 GP0I0 Polarity on H1 Normal (Active High) Inverted (Active Low) GPIO0 not sent to H1

JP5 GPIO0 function select GPIO0 HR-TFT PS signal —

= recommended settings

JP1

VCLKOUT from

clock synthesizer

External

oscillator (U7)

BUSCLK from

Header H4

Installation and Configuration

10 Seiko Epson Corporation S5U13A04B00C Rev 1.0 Evaluation Board

Rev. 3.1

JP2 - CLKI2 Source

JP2 selects the source for the CLKI2 input pin.

Position 1-2 sets the CLKI2 source to MCLKOUT from the Cypress clock synthesizer

(default setting).

Position 2-3 sets the CLKI2 source to the external oscillator at U8.

Figure 3-3: Configuration Jumper (JP2) Location

JP3 - LCD Panel Voltage

JP3 selects the voltage level to the LCD panel.

Position 1-2 sets the voltage level to 5.0V (default setting).

Position 2-3 sets the voltage level to 3.3V.

Note

When configured for Sharp HR-TFT or Epson D-TFD panels, JP3 and JP5 must be set

to position 2-3.

Figure 3-4: Configuration Jumper (JP3) Location

JP2

MCLKOUT from

clock synthesizer

External

oscillator (U8)

+5 LCDVCC +3.3 LCDVCC

JP3

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