Cypress CY62157EV18 Manuel utilisateur

Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600

Document #: 38-05490 Rev. *D Revised March 30, 2007

CY62157EV18 MoBL®

8-Mbit (512K x 16) Static RAM

Features

• Very high speed: 55 ns

• Wide voltage range: 1.65V–2.25V

• Pin Compatible with CY62157DV18 and CY62157DV20

• Ultra low standby power

— Typical Standby current: 2 µA

— Maximum Standby current: 8 µA

• Ultra low active power

— Typical active current: 1.8 mA @ f = 1 MHz

• Easy memory expansion with CE1, CE2and OE features

• Automatic power down when deselected

• CMOS for optimum speed and power

• Available in Pb-free 48-ball VFBGA package

Functional Description [1]

The CY62157EV18 is a high performance CMOS static RAM

organized as 512K words by 16 bits. This device features

advanced circuit design to provide ultra low active current.

This is ideal for providing More Battery Life™ (MoBL®) in

portable applications such as cellular telephones. The device

also has an automatic power down feature that significantly

reduces power consumption when addresses are not toggling.

The device can also be put into standby mode when

deselected (CE1HIGH or CE2 LOW or both BHE and BLE are

HIGH). The input and output pins (IO0through IO15) are

placed in a high impedance state when:

• Deselected (CE1 HIGH or CE2LOW)

• Outputs are disabled (OE HIGH)

• Both Byte High Enable and Byte Low Enable are disabled

(BHE, BLE HIGH) or

• Write operation is active (CE1LOW, CE2HIGH and WE

LOW).

Write to the device by taking Chip Enables (CE1 LOW and CE2

HIGH) and Write Enable (WE) input LOW. If Byte Low Enable

(BLE) is LOW, then data from IO pins (IO0through IO7), is

written into the location specified on the address pins (A0

through A18). If Byte High Enable (BHE) is LOW, then data

from IO pins (IO8through IO15) is written into the location

specified on the address pins (A0through A18).

Read from the device by taking Chip Enables (CE1 LOW and

CE2HIGH) and Output Enable (OE) LOW while forcing the

Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,

then data from the memory location specified by the address

pins appear on IO0to IO7. If Byte High Enable (BHE) is LOW,

then data from memory appears on IO8to IO15. See the “Truth

Table” on page 9 for a complete description of read and write

modes.

Product Portfolio

Product VCC Range (V) Speed

(ns)

Power Dissipation

Operating ICC, (mA)

Standby, ISB2 (µA)

f = 1MHz f = fmax

Min Typ [2] Max Typ [2] Max Typ [2] Max Typ [2] Max

CY62157EV18 1.65 1.8 2.25 55 1.8 3 18 25 2 8

Notes

1. For best practice recommendations, refer to the Cypress application note “System Design Guidelines” located at http://www.cypress.com.

2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA= 25°C.

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CY62157EV18 MoBL®

Document #: 38-05490 Rev. *D Page 2 of 12

Logic Block Diagram

Pin Configuration [3]

512K x 16

RAM Array IO0–IO7

ROW DECODER

COLUMN DECODER

A11

A12

A13

A14

A15

SENSE AMPS

DATA IN DRIVERS

A3IO8–IO15

BLE

BHE

A16

A17

BHE

BLE

A10

A18

POWER DOWN

CIRCUIT CE2

CE1

CE2

CE1

Note

3. NC pins are not connected on the die.

A11

A10

A3CE1

IO10

IO8

IO9

IO11

IO13

IO12

IO14

IO15

VSS

IO0

BHE

CE2

A17

BLE

IO2

IO1

IO3

IO4

IO5IO6

IO7

A15

A14

A13

A12

A18 NC

326

A16

VCC

VCC VSS

48-ball VFBGA

Top View

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CY62157EV18 MoBL®

Document #: 38-05490 Rev. *D Page 3 of 12

Maximum Ratings

Exceeding maximum ratings may impair the useful life of the

device. These user guidelines are not tested.

Storage Temperature ................................ –65°C to + 150°C

Ambient Temperature with

Power Applied ........................................... –55°C to + 125°C

Supply Voltage to Ground

Potential...............................–0.2V to 2.45V (VCCmax + 0.2V)

DC Voltage Applied to Outputs

in High-Z State [4, 5]..............–0.2V to 2.45V (VCCmax + 0.2V)

DC Input Voltage [4, 5] ......... –0.2V to 2.45V (VCCmax + 0.2V)

Output Current into Outputs (LOW) ............................ 20 mA

Static Discharge Voltage ......................................... > 2001V

(in accordance with MIL-STD-883, Method 3015)

Latch-up Current ................................................... > 200 mA

Operating Range

Device Range Ambient

Temperature VCC [6]

CY62157EV18LL Industrial –40°C to +85°C 1.65V to 2.25V

Electrical Characteristics (Over the Operating Range)

Parameter Description Test Conditions

55 ns

Unit

Min Typ [2] Max

VOH Output HIGH Voltage IOH = –0.1 mA VCC = 1.65V 1.4 V

VOL Output LOW Voltage IOL = 0.1 mA VCC = 1.65V 0.2 V

VIH Input HIGH Voltage VCC = 1.65V to 2.25V 1.4 VCC + 0.2V V

VIL Input LOW Voltage VCC = 1.65V to 2.25V –0.2 0.4 V

IIX Input Leakage

Current

GND < VI< VCC –1 +1 µA

IOZ Output Leakage

Current

GND < VO <VCC, Output Disabled –1 +1 µA

ICC VCC Operating Supply

Current

f = fmax = 1/tRC VCC = VCC(max)

IOUT = 0 mA

CMOS levels

18 25 mA

f = 1 MHz 1.8 3 mA

ISB1 Automatic CEPower Down

Current–CMOS Inputs

CE1> VCC−0.2V or CE2 <0.2V

VIN >VCC – 0.2V, VIN <0.2V)

f = fmax (Address and Data Only),

f = 0 (OE, WE, BHE and BLE), VCC = VCC(max).

28µA

ISB2 [7] Automatic CE Power Down

Current–CMOS Inputs

CE1> VCC – 0.2V or CE2< 0.2V,

VIN > VCC – 0.2V or VIN < 0.2V,

f = 0, VCC = VCC(max).

28µA

Capacitance [8]

Parameter Description Test Conditions Max Unit

CIN Input Capacitance TA= 25°C, f = 1 MHz, VCC = VCC(typ) 10 pF

COUT Output Capacitance 10 pF

Notes

4. VIL(min) = –2.0V for pulse durations less than 20 ns.

5. VIH(max) = VCC + 0.5V for pulse durations less than 20 ns.

6. Full Device AC operation assumes a 100 µs ramp time from 0 to VCC (min) and 200 µs wait time after VCC stabilization.

7. Only chip enable (CE) and byte enables (BHE and BLE) need to be tied to CMOS levels to meet the ISB2 spec. Other inputs can be left floating.

8. Tested initially and after any design or process changes that may affect these parameters.

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Document #: 38-05490 Rev. *D Page 4 of 12

Thermal Resistance [8]

Parameter Description Test Conditions BGA Unit

ΘJA Thermal Resistance

(Junction to Ambient)

Still air, soldered on a 3 × 4.5 inch,

two-layer printed circuit board

72 °C/W

ΘJC Thermal Resistance

(Junction to Case)

8.86 °C/W

AC Test Loads and Waveforms

Parameters Value Unit

R1 13500 Ω

R2 10800 Ω

RTH 6000 Ω

VTH 0.80 V

Data Retention Characteristics (Over the Operating Range)

Parameter Description Conditions Min Typ [2] Max Unit

VDR VCC for Data Retention 1.0 V

ICCDR Data Retention Current VCC= VDR, CE1> VCC – 0.2V,

CE2< 0.2V,VIN > VCC – 0.2V or VIN < 0.2V

13µA

tCDR [8] Chip Deselect to Data Retention Time 0 ns

tR [9] Operation Recovery Time tRC ns

Data Retention Waveform [10]

VCC

OUTPUT

30 pF

INCLUDING

JIG AND

SCOPE

GND

90%

10%

90%

10%

Rise Time = 1 V/ns Fall Time = 1 V/ns

OUTPUT V

Equivalent to: THEVENIN EQUIVALENT

ALL INPUT PULSES

RTH

VCC(min)

tCDR

VDR >1.0V

DATA RETENTION MODE

VCC(min)

CE1or

VCC

BHE.BLE

Notes

9. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 µs or stable at VCC(min) > 100 µs.

10. BHE.BLE is the AND of both BHE and BLE. Deselect the chip by either disabling chip enable signals or by disabling both BHE and BLE.

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CY62157EV18 MoBL®

Document #: 38-05490 Rev. *D Page 5 of 12

Switching Characteristics (Over the Operating Range) [11, 12]

Parameter Description 55 ns Unit

Min Max

Read Cycle

tRC Read Cycle Time 55 ns

tAA Address to Data Valid 55 ns

tOHA Data Hold from Address Change 10 ns

tACE CE1LOW and CE2 HIGH to Data Valid 55 ns

tDOE OE LOW to Data Valid 25 ns

tLZOE OE LOW to Low-Z [13] 5ns

tHZOE OE HIGH to High-Z [13, 14] 18 ns

tLZCE CE1LOW and CE2 HIGH to Low-Z [13] 10 ns

tHZCE CE1HIGH and CE2 LOW to High-Z [13, 14] 18 ns

tPU CE1LOW and CE2 HIGH to Power Up 0 ns

tPD CE1HIGH and CE2 LOW to Power Down 55 ns

tDBE BLE/BHE LOW to Data Valid 55 ns

tLZBE [15] BLE/BHE LOW to Low-Z [13] 10 ns

tHZBE BLE/BHE HIGH to High-Z [13, 14] 18 ns

Write Cycle [16]

tWC Write Cycle Time 45 ns

tSCE CE1LOW and CE2 HIGH to Write End 35 ns

tAW Address Setup to Write End 35 ns

tHA Address Hold from Write End 0 ns

tSA Address Setup to Write Start 0 ns

tPWE WE Pulse Width 35 ns

tBW BLE/BHE LOW to Write End 35 ns

tSD Data Setup to Write End 25 ns

tHD Data Hold from Write End 0 ns

tHZWE WE LOW to High-Z [13, 14] 18 ns

tLZWE WE HIGH to Low-Z [13] 10 ns

Notes

11. Test conditions for all parameters other than tri-state parameters assume signal transition time of 1V/ns or less, timing reference levels of VCC(typ)/2, input pulse

levels of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in the “AC Test Loads and Waveforms” on page 4.

12. AC timing parameters are subject to byte enable signals (BHE or BLE) not switching when chip is disabled. Please see application note AN13842 for furthe

clarification.

13. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any

given device.

14. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the output enters a high impedance state.

15. If both byte enables are toggled together, this value is 10 ns.

16. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a

write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing must be referenced to the edge of the signal that

terminates the write.

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CY62157EV18 MoBL®

Document #: 38-05490 Rev. *D Page 6 of 12

Switching Waveforms

Read Cycle 1 (Address Transition Controlled) [17, 18]

Read Cycle 2 (OE Controlled) [18, 19]

PREVIOUS DATA VALID DATA VALID

tAA

tOHA

tRC

ADDRESS

DATA OUT

50%

DATA VALID

tRC

tACE

tDOE

tLZOE

tLZCE

tPU

HIGH IMPEDANCE

tHZOE

tPD

tHZBE

tLZBE

HZCE

tDBE

CE1

ADDRESS

CE2

BHE/BLE

DATA OUT

VCC

SUPPLY

CURRENT

HIGH

ICC

ISB

IMPEDANCE

Notes:

17. The device is continuously selected. OE, CE1 = VIL, BHE and/or BLE = VIL, and CE2 = VIH.

18. WE is HIGH for read cycle.

19. Address valid before or similar to CE1, BHE, BLE transition LOW and CE2transition HIGH.

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CY62157EV18 MoBL®

Document #: 38-05490 Rev. *D Page 7 of 12

Write Cycle 1 (WE Controlled) [16, 20, 21]

Write Cycle 2 (CE1or CE2 Controlled) [16, 20, 21]

Switching Waveforms (continued)

tHD

tSD

tPWE

tSA

tHA

tAW

tSCE

tWC

tHZOE

VALID DATA

tBW

NOTE 22

CE1

ADDRESS

CE2

DATA IO

BHE/BLE

tHD

tSD

tPWE

tHA

tAW

tSCE

tWC

tHZOE

VALID DATA

tBW

tSA

NOTE 22

CE1

ADDRESS

CE2

DATA IO

BHE/BLE

Notes:

20. Data IO is high impedance if OE = VIH.

21. If CE1goes HIGH and CE2goes LOW simultaneously with WE = VIH, the output remains in a high impedance state.

22. During this period, the IOs are in output state and input signals must not be applied.

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CY62157EV18 MoBL®

Document #: 38-05490 Rev. *D Page 8 of 12

Write Cycle 3 (WE Controlled, OE LOW) [21]

Write Cycle 4 (BHE/BLE Controlled, OE LOW) [21]

Switching Waveforms (continued)

VALID DATA

tHD

tSD

tLZWE

tPWE

tSA

tHA

tAW

tSCE

tWC

tHZWE

tBW

NOTE 22

ADDRESS

DATA IO

BHE

/BLE

tHD

tSD

tSA

tHA

tAW

tWC

VALID DATA

tBW

tSCE

tPWE

NOTE 22

ADDRESS

DATA IO

BHE

/BLE

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CY62157EV18 MoBL®

Document #: 38-05490 Rev. *D Page 9 of 12

Truth Table

CE1CE2WE OE BHE BLE Inputs/Outputs Mode Power

H X X X X X High-Z Deselect/Power Down Standby (ISB)

X L X X X X High-Z Deselect/Power Down Standby (ISB)

X X X X H H High-Z Deselect/Power Down Standby (ISB)

L H H L L L Data Out (IO0–IO15) Read Active (ICC)

L H H L H L Data Out (IO0–IO7);

High-Z (IO8–IO15)

Read Active (ICC)

L H H L L H High-Z (IO0–IO7);

Data Out (IO8–IO15)

Read Active (ICC)

L H H H L H High-Z Output Disabled Active (ICC)

L H H H H L High-Z Output Disabled Active (ICC)

L H H H L L High-Z Output Disabled Active (ICC)

L H L X L L Data In (IO0–IO15) Write Active (ICC)

L H L X H L Data In (IO0–IO7);

High-Z (IO8–IO15)

Write Active (ICC)

L H L X L H High-Z (IO0–IO7);

Data In (IO8–IO15)

Write Active (ICC)

Ordering Information

Speed

(ns) Ordering Code

Package

Diagram Package Type Operating

Range

55 CY62157EV18LL-55BVXI 51-85150 48-ball Very Fine Pitch Ball Grid Array (Pb-free) Industrial

Contact your local Cypress sales representative for availability of these parts

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Document #: 38-05490 Rev. *D Page 10 of 12

use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to

be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its

products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

CY62157EV18 MoBL®

Package Diagrams

Figure 1. 48-ball VFBGA (6 x 8 x 1 mm), 51-85150

MoBL is a registered trademark, and More Battery Life is a trademark of Cypress Semiconductor. All product and company names

mentioned in this document are the trademarks of their respective holders.

A1 CORNER

0.75

Ø0.30±0.05(48X)

Ø0.25 M C A B

Ø0.05 M C

0.15(4X)

0.21±0.05

1.00 MAX

SEATING PLANE

0.55 MAX.

0.25 C

0.10 C

A1 CORNER

TOP VIEW BOTTOM VIEW

234

3.75

5.25

465231

6.00±0.10

8.00±0.10

6.00±0.10

1.875

2.625

0.26 MAX.

51-85150-*D

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