Analog Devices SHARC ADSP-21065L Manuel utilisateur
ADSP-21065L SHARC User’s Manual 1-1
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Figure 1-0.
Table 1-0.
Listing 1-0.
The ADSP-21065L SHARC is a high-performance, 32-bit digital signal
processor for communications, digital audio, and industrial instrumenta-
tion applications.
Along with a high-performance, 180 MFLOPS core, the ADSP-21065L
has a dual-ported, on-chip SRAM and integrated I/O peripherals sup-
ported by a dedicated I/O processor. With its on-chip instruction cache,
the processor can execute every instruction in a single cycle. The
ADSP-21065L is code-compatible with other members of the SHARC
family.
Four independent buses for dual data, instructions, and I/O, and cross-
bar-switch memory connections implement the ADSP-21065L’s Super
Harvard Architecture.
The ADSP-21065L provides these features:
• 32-Bit IEEE floating-point computation units—Multiplier, ALU,
and Shifter—that support 180 MFLOPS or 180, 32-bit fixed-point
MOPS.
• Data Register File.
• Data Address Generators (DAG1, DAG2).
• Program Sequencer with Instruction Cache.
• 544 Kbits of user-configurable, dual-ported SRAM.
• External port for glueless interface to SDRAM and other off-chip
memory and peripherals.
1-2 ADSP-21065L SHARC User’s Manual
• Host port and multiprocessor interface.
• DMA controller to support ten DMA channels.
• Serial ports with two receivers and two transmitters that support
TDM and I2S.
• Two programmable timers and twelve programmable, general-pur-
pose I/O ports.
• JTAG test access port.
Figure 1-1 shows the ADSP-21065L’s Super Harvard Architecture, which
consists of a crossbar bus switch connecting the DSP core’s numeric pro-
cessor to an independent I/O processor, dual-ported memory, and parallel
system bus port.
Figure 1-1. Super Harvard Architecture
Dual-Ported,
Multiaccess
Memory
Numeric
Processor
I/O Processor
&
DMA Controller
Parallel System
Bus Port
Crossbar Bus
Interconnect
ADSP-21065L SHARC User’s Manual 1-3
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Figure 1-2, a detailed block diagram of the processor, shows its architec-
tural features.
Figure 1-2. ADSP-21065L block diagram
Figure 1-2 also shows the ADSP-21065L’s on-chip buses: the PM (Pro-
gram Memory) bus, made up of the PMA (Program Memory Address) and
PMD (Program Memory Data) buses; the DM (Data Memory) bus, made
up of the DMA (Data Memory Address) and DMD (Data Memory Data)
buses; and the I/O bus, made up of the IOA (I/O Address) and IOD (I/O
Data) buses.
The PM bus can access either instructions or data. During a single cycle,
the processor can access two data operands, one over the PM bus and one
over the DM bus, access an instruction from the cache, and perform a
DMA transfer.
The ADSP-21065L’s external port provides the processor’s interface to
external memory, which is glueless to an SDRAM; memory-mapped I/O;
DATA
ADDR DATA
ADDR
BLOCK 1
T
WO
I
NDEPENDENT
D
UAL
-P
ORTED
B
LOCKS
PROCESSOR
PORT I/O
PORT
ADDR DATA DATA
ADDR
BLOCK 0
IOP
Registers
Control,
Status, Timer,
&
Data Buffers
DMA
Controller
SPORT 0
SPORT 1
SDRAM Interface
HOST Port
Addr Bus
Mux
Data Bus
Mux
4
Multiprocessor
Interface
DAG1
8x4x32 DAG2
8x4x24 Program
Sequencer
Instruction
cache
32x48b
Bus
Connect
(PX)
Multiplier Barrel
Shifter ALU
Data
Register
File
16x40b
24
32
48
40
PM Address Bus
DM Data Bus
PM Data Bus
DM Address Bus
7
JTAG
Test &
Emulation
IOD
48 IOA
17 24
32
(2 Rx, 2 Tx)
(2 Rx, 2 Tx)
(I2S)
(I2S)
I/O Processor
DSP Core Dual-Ported SRAM
External Port
1-4 ADSP-21065L SHARC User’s Manual
a host processor; and another multiprocessing ADSP-21065L. The exter-
nal port performs internal and external bus arbitration and supplies
control signals to shared, global memory and I/O devices.
The documentation set, ADSP-21065L SHARC User’s Manual and
ADSP-21065L SHARC Technical Reference, contain ADSP-21065L archi-
tectural information and the processor’s instruction set, which developers
need to design and program ADSP-21065L-based systems. For timing,
electrical, and package specifications, see the processor’s data sheet.
ADSP-21065L SHARC User’s Manual 1-5
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The ADSP-21065L possesses the five central requirements for DSPs estab-
lished in the ADSP-2106x Family of 32-bit floating-point DSPs:
• Fast, flexible arithmetic computation units
• Unconstrained data flow to and from the computation units
• Extended precision and dynamic range in the computation units
• Dual address generators
• Efficient program sequencing
Fast, Flexible Arithmetic. The ADSP-21065L executes all instructions in
a single cycle. It provides fast cycle times, and, in addition to traditional
multiplication, addition, subtraction, and combined multiplication/addi-
tion, it also provides a complete set of arithmetic operations, including
Seed 1/X, Seed 1√X, Min, Max, Clip, Shift, and Rotate. The
ADSP-21065L is IEEE floating-point compatible and supports either
interrupt-on-arithmetic or latched-status exception handling.
Unconstrained Data Flow. The ADSP-21065L has an enhanced Super
Harvard architecture combined with a 10-port data register file. In every
cycle, the processor can:
• Read or write two operands to or from the Register File,
• Supply two operands to the ALU,
• Supply two operands to the multiplier, and
• Receive two results from the ALU and multiplier.
The processor’s 48-bit orthogonal instruction word supports fully parallel
data transfer and arithmetic operations in the same instruction.
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1-6 ADSP-21065L SHARC User’s Manual
40-Bit Extended Precision. The ADSP-21065L handles 32-bit IEEE
floating-point format, 32-bit integer and fractional formats (twos-comple-
ment and unsigned), and extended-precision, 40-bit IEEE floating-point
format. The processor carries extended precision throughout its computa-
tion units, limiting intermediate data truncation errors. When working
with data on-chip, the processor can transfer the extended-precision,
32-bit mantissa to and from all computation units. The fixed-point for-
mats have an 80-bit accumulator for true 32-bit fixed-point computations.
Dual Address Generators. The ADSP-21065L has two data address gener-
ators (DAGs) that provide immediate or indirect (pre- and postmodify)
addressing. It supports modulus and bit-reverse operations with no con-
straints on data buffer placement.
Efficient Program Sequencing. In addition to zero-overhead loops, the
ADSP-21065L supports single-cycle setup and exit for loops. Loops are
both nestable (six levels in hardware) and interruptible. The processors
support both delayed and non-delayed branches.
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The ADSP-21065L includes several enhancements that simplify system
development. The enhancements occur in three key areas:
• Architectural features supporting high-level languages and operat-
ing systems.
• IEEE 1149.1 JTAG serial scan path and on-chip emulation features.
• Support of IEEE floating-point formats.
ADSP-21065L SHARC User’s Manual 1-7
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High Level Languages. The ADSP-21065L’s architecture has several fea-
tures that directly support high-level language compilers and operating
systems:
• General purpose data and address register files.
• 32-bit native data types.
• Large address space.
• Pre- and postmodify addressing.
• Unconstrained circular data buffer placement.
• On-chip program, loop, and interrupt stacks.
Additionally, the ADSP-21065L architecture is designed specifically to
support ANSI-standard Numerical C extensions—the first compiled lan-
guage to support vector data types and operators for numeric and signal
processing.
Serial Scan and Emulation Features. The ADSP-21065L supports the
IEEE standard P1149.1 Joint Test Action Group (JTAG) standard for
system test. This standard defines a method for serially scanning the I/O
status of each component in a system. The ADSP-21065L EZ-ICE
in-circuit emulator also uses the JTAG serial port to access the processor’s
on-chip emulation features.
IEEE Formats. The ADSP-21065L supports IEEE floating-point data for-
mats. This means that algorithms developed on IEEE-compatible
processors and workstations are portable across processors without con-
cern for possible instability introduced by biased rounding or inconsistent
error handling.
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1-8 ADSP-21065L SHARC User’s Manual
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A digital signal processor’s data format determines its ability to handle sig-
nals of differing precision, dynamic range, and signal-to-noise ratios.
However, ease-of-use and time-to-market considerations are often equally
important.
Precision. The number of bits of precision of A/D converters has contin-
ued to increase, and the trend is for both precision and sampling rates to
increase.
Dynamic Range. Compression and decompression algorithms have tradi-
tionally operated on signals of known bandwidth. These algorithms were
developed to behave regularly, to keep costs down and implementations
easy. Increasingly, however, the trend in algorithm development is to
unconstrain the regularity and dynamic range of intermediate results.
Adaptive filtering and imaging are two applications that require a wide
dynamic range.
Signal-to-Noise Ratio. Audio, video, imaging, and speech recognition
require wide dynamic range to discern selected signals occurring in noisy
environments.
Ease-of-Use. In general, 32-bit, floating-point DSPs are easier to use and
enable a quicker time-to-market than 16-bit, fixed-point processors. The
extent to which this is true depends on the floating-point processor’s
architecture. Consistency with IEEE workstation simulations and the
elimination of scaling are two clear ease-of-use advantages. High-level lan-
guage programmability, large address spaces, and wide dynamic range
enable system development time to focus on algorithms and signal pro-
cessing concerns, rather than assembly language coding, code paging, and
error handling.
ADSP-21065L SHARC User’s Manual 1-9
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The rest of this chapter summarizes the architectural features of the
ADSP-21065L SHARC:
• DSP core
• Dual-ported memory
• External port interface
• Host processor interface
• I/O Processor
• Serial ports
• DMA controller
• Booting
• Development tools
The remaining chapters of this manual describe these features in detail.
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The ADSP-21065L’s DSP core consists of:
• Three computation units
• A data Register File
• A Program Sequencer and two Data Address Generators
• An Instruction Cache
• DSP core buses
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1-10 ADSP-21065L SHARC User’s Manual
• Two programmable timers and twelve general-purpose
I/Os
• Four external hardware interrupts
These additional features support and enhance the DSP core’s
components:
• Context switching
• Comprehensive instruction set
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The DSP core contains three independent computation units:
• ALU
Performs a standard set of arithmetic and logic operations in both
fixed-point and floating-point formats.
• Multiplier with a fixed-point accumulator
Performs floating-point and fixed-point multiplication, and
fixed-point multiply/add and multiply/subtract operations.
•Shifter
Performs logical and arithmetic shifts, bit manipulation, field
deposit and extraction, and exponent derivation operations on
32-bit operands.
For meeting a wide variety of processing needs, the computation units
process data in three formats
• 32-bit, fixed-point
• 32-bit, floating-point
• 40-bit, floating-point
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