Trenz Electronic TE0300 Manuel utilisateur

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Spartan-3E FPGA

Industrial Micromodule

Rev 1.19 as of 011-10-04 User Manual

Features

■High-density plug-in Xilinx Spartan-

3E module

■USB 2.0 interface with high speed

(480 Mbit/s) data rate

■Large SPI flash for configuration and

user storage accessible via USB or SPI

connector

■Large DDR-SDRAM

■FPGA configuration is implemented via

TAG, SPI Flash or USB

■3 on-board high-power, high-effi-

ciency, switch-mode DC-DC convert-

ers (1 A for each voltage rail: 1. V,

.5 V, 3.3 V)

■Power supply via USB or B B (carrier

board)

■Flexible expansion via high-density

shockproof B2B (board-to-board)

connectors

■Most I/O's on the B B connectors are

routed as LVDS pairs

■Evenly spread supply pins for good

signal integrity

■Industrial temperature grade avail-

able on request

■Low-cost, versatile and ruggedized

design

Specifications

■FPGA: Xilinx Spartan-3E XC3S500E –

XC3S1600E

■USB controller: Cypress EZ-USB FX

USB .0 microcontroller CY7C68013A-

56LFX

■Non volatile memory: 16 MBit - 64

Mbit SPI Flash for FPGA-configuration

and user data

■Volatile memory: 51 Mbit x 16 DDR

SDRAM with up to 666 Mbyte/s

■Up to 110 FPGA user I/Os

■Supply voltage range: 4.0 V – 5.5 V

■1 push-button

■1 LED

■Small size (only 40.5 mm x 47.5 mm)

Trenz Electronic GmbH 1

Trenz Electronic GmbH

[email protected]

www.trenz-electronic.de

Figure 2: TE0300: top view. Figure 1: TE0300: bottom view.

Table of Contents

Features........................................................................................................................1

Specifications................................................................................................................1

Applications...................................................................................................................3

Description....................................................................................................................3

Physical Features...........................................................................................................3

Power Supply.................................................................................................................5

FPGA User I/Os..............................................................................................................6

User Button and LED.......................................................................................................7

Configuration Switches...................................................................................................7

JTAG and SPI.................................................................................................................8

Clock Networks..............................................................................................................9

On-board Memories......................................................................................................10

Module Configuration....................................................................................................11

Changes from TE0300-00 to TE0300-01.......................................................................... 4

Ordering Information.................................................................................................... 4

Revision History........................................................................................................... 4

Legal Notices............................................................................................................... 5

Environmental protection............................................................................................... 6

Appendix..................................................................................................................... 7

Spartan-3E FPGA Industrial Micromodule User Manual

Applications

■IP (intellectual property) development

■Digital signal processing

■Image processing

■Cryptography

■Industrial control

■Low-power design

■General-purpose prototyping platform

Description

The FPGA industrial micromodule integ-

rates a leading edge Xilinx Spartan-3E

FPGA, an USB .0 microcontroller, config-

uration Flash, DDR SDRAM and power sup-

plies on a tiny footprint. A large number of

configurable I/Os are provided via B B

mini-connectors.

The module is intended to be used as an

OEM board, or to be combined with our

carrier boards. It is a powerful system

widely used for educational and research

activities.

Boards with other configurations, larger

FPGA's or equipped with industrial temper-

ature grade parts are available on request.

Software for SPI flash programming over

USB as well as reference designs for high

speed data transfer over USB are included.

Physical Features

Board Dimensions

The module measures 40.50 mm by 47.50

mm.

Board-to-Board Connectors

The module has two B B (board-to-board)

receptacle connectors (J4 and J5) for a

total of 160 contacts (Figure 5).

The ordering numbers of the connector re-

ceptacles are given in Table 1.

Trenz Electronic GmbH 3

Figure 5: micromodule receptacle.

Figure 4: connector receptacles 4

and 5 (bottom view).

Figure 3: module dimensions in mm

(top view).

Spartan-3E FPGA Industrial Micromodule User Manual

supplier header

Digikey

H11113CT-ND

H11113TR-ND

H11113DKR-ND

Hirose DF17(3.0)-80DS-0.5V(57)

Trenz Electronic 684

Table 1: equivalent part numbers of

the receptacle connectors 4 and 5.

The on-board receptacles mate with their

corresponding headers on the carrier board

(Figure 6).

The ordering number of the headers is giv-

en in Table .

supplier header

Digikey

H11148DKR-ND

H11148TR-ND

H11148CT-ND

Hirose DF17(4.0)-80DP-0.5V(57)

Trenz Electronic 938

Table 2: equivalent part numbers of

the mating connectors.

Figure 7 shows the definition of stacking

height featured by the combination of the

TE0300 receptacle with its corresponding

header.

The stacking height of the TE0300 B B

connectors is 7 (seven) mm. The stacking

height does not include the solder paste

thickness.

USB Connector

The micromodule uses a mini-USB (B type)

receptacle connector.

Power Supply

The module can be powered by the B B

connector or the USB connector. If both

power supplies are available, the B B con-

nector power supply takes precedence,

disabling the USB power supply automatic-

ally.

B2B Connector Power Supply

The B B connector power supply requires

a single nominal 5 V DC power supply. The

power is usually supplied to the module

through the 5 V contacts (5Vb b) of the

B B connectors J5 (see Appendix). The re-

commended minimum supply voltage is

Trenz Electronic GmbH 4

Figure 8: mini-USB (B type) receptacle

connector.

Figure 6: mating header.

Figure 7: stacking height (h).

Spartan-3E FPGA Industrial Micromodule User Manual

4 V. The maximum supply voltage is 5.5 V.

The recommended maximum continuous

supply current is 1.5 A.

USB Power Supply

The module is powered by the USB con-

nector if the following conditions are met:

■the module is equipped with an USB

connector,

■the module is connected to a USB bus,

■no power supply is provided by the B B

connectors.

In this case, other components (e.g. ex-

tension or carrier boards) may also be

(5V) of the B B connector J5.

On-board Power Rails

Three on-board voltage regulators provide

the following power supply rails needed by

the components on the micromodule:

■1. V, 1 A max

■.5 V, 1 A max

■3.3 V, 1 A max

The power rails are available for the FPGA

and can be shared with a baseboard by the

corresponding lines of the B B connect-

ors J4 and J5. Please note that the power

consumption of the FPGA is highly de-

pendent on the design actually loaded.

So please use a tool like Xilinx Xpower to

determine the expected power consump-

tion.

Even if the provided voltages of the mod-

ule are not used on the baseboard, it is re-

commended to bypass them to ground

with 10 nF - 100 nF capacitors.

I/O Banks Power Supply

The Spartan-3E architecture organizes

I/Os into four I/O banks (see Table 3).

Bank Supply

Voltage (V)

Min

(V)

Max

(V)

B0 VccIO 1. 3.3

B1 ,5 - -

B 3,3 - -

B3 3,3 - -

Table 3: I/O banks power supply.

Voltage for banks B1, B and B3 is fixed

respectively to ,5 V, 3,3 V and 3,3 V.

Voltage VccIO for bank B0 shall span from

1. V to 3.3 V. VccIO can be supplied

either externally or internally to the micro-

module.

Warning! Spartan-3 I/Os are not 5 V tol-

erant. Applying more than the recommen-

ded operating voltages at any pin, results

in a damaged FPGA (see Xilinx Answer

AR#19146).

Externally Supplied VccIO

VccIO can be externally supplied over the

B B connector J4. If bank B0 is not used,

then VccIO can be left open.

Internally Supplied VccIO

If VccIO is not externally supplied, it can

be internally supplied by one of the intern-

al power rails of .5 V and 3.3 V. This is

possible by short-circuiting one of the two

pad pairs placed on the right of connector

J4 at the top right corner of the bottom

side of the micromodule.

Figure 9 shows how to short-circuit VccIO

to internal 3.3 V power rail.

Figure 10 shows how to short-circuit VccIO

to internal .5 V power rail.

Trenz Electronic GmbH 5

Spartan-3E FPGA Industrial Micromodule User Manual

Two suitable ways of shirt-circuiting the

paid pair are by means of a zero-ohm

0603 (1608 metric) chip resistor or a

solder blob.

FPGA User I/Os

A total of 110 FPGA user I/Os are available

on corresponding contacts of B B connect-

ors J4 and J5 (see Appendix).

■37 differential digital I/O pairs:

each pair is configurable as single-en-

ded digital I/Os, corresponding to a

maximum of 74 single-ended digital

I/Os;

■4 differential clock input pairs:

each pair is configurable as differential

digital I/O pair or single-ended clock

inputs or single-ended digital I/Os (or

combination thereof), corresponding to

from a maximum of 8 independent clock

inputs to a maximum of 8 independent

digital I/Os;

■1 differential clock input pair:

the pair is configurable as differential

digital input pair or as single-ended

clock inputs or single-ended digital in-

puts (or combination thereof), corres-

ponding to from a maximum of inde-

pendent clock inputs to a maximum of

independent digital inputs;

■1 single-ended digital I/Os;

■5 single-ended inputs.

Table 4 summarizes the maximum avail-

able FPGA user I/Os divided by supply

voltage.

type VccIO 3.3 V

diff. I/O pairs ≤ 18 ≤ 3

diff inputs ≤ 1 none

diff. clocks ≤ 4 ≤ 1

s. e. I/Os ≤ 46 ≤ 58

s. e. inputs ≤ ≤ 4

s. e. clocks ≤ 8 ≤ 3

Table 4: maximum FPGA user I/Os by

supply voltage.

Differential Pairs

The micromodule has a total of 4 differ-

ential signal pairs routed pairwise with a

differential impedance of 100 ohm to adja-

cent connector pins. These lines can be

used for high speed signaling up to

666 Mbit/s per differential pair (see Xilinx

Application Note XAPP485).

User Button and LED

LED

The LED is lit when the U_LED line (pin

R10) is set high as detailed in the follow-

ing table.

Signal FPGA pin FPGA ball

U_LED IO_L15P_

(bank ) R10

Table 5: user led signal details.

Push Button

The push button is connected to the PB in-

put (pin V16). as detailed in the following

table.

Trenz Electronic GmbH 6

Figure 10: R103 pad pair (blue high-

light) for 2.5 V internal supply.

Figure 9: R102 pad pair (blue high-

light) for 3.3 V internal supply.

Spartan-3E FPGA Industrial Micromodule User Manual

Signal FPGA pin FPGA ball

PB IP

(bank ) V16

Table 6: user button signal details.

The input is normally low. The input is

pulled up when pressed.

Configuration Switches

The micromodule hosts 4 DIP switches on

the top side: S1; S , S3 and S4.

For customers requesting a sufficient

amount of units, the micromodules can be

manufactured replacing the switches by

fixed connections.

DIP Switch S1

S1 enables / disables the communication

between the Cypress EZ-USB FX micro-

controller and the I C CMOS Serial EEP-

ROM.

Turn S1 off when programming the USB

EEPROM (storing the USB vendor ID and

device ID). This will force the USB micro-

controller to provide its default vendor ID

and device ID.

S1 position

EEPROM (on)* EEPROM enabled

Off (off) EEPROM disabled

Table 7: S1 (* default: EEPROM).

For further information, please read para-

graph “Software Configuration”.

DIP Switch S2

S enables / disables the reset line. The

reset line (available also on contacts of

the B B connector) resets the USB micro-

controller and the FPGA.

S has to be turned off (Reset) if the user

wants to program the SPI Flash memory in

direct mode. For programming the SPI

Flash memory in indirect mode over JTAG,

S has to be turned on (Run).

S2 position

Run (on)* system running

Reset (off) system reset

Table 8: S2 (*default: Run).

For further information, please read para-

graph “Software Configuration”.

DIP Switch S3

S3 conditionally / unconditionally enables

the 1. V and .5 V power rails.

When S3 is turned on, the 1. V and .5 V

power rails are controlled by the USB mi-

crocontroller. At start-up, the USB micro-

controller switches off the 1. V and .5 V

power rails and starts up the module in

low-power mode. After enumeration, the

USB microcontroller firmware switches the

1. V and .5 V power rails on, if enough

current is available from the USB bus.

When S3 is turned off, the 1. V and .5 V

power rails are always enabled.

S3 position

FX PON (on)* rails controlled by FX

PON (off) rails always enabled

Table 9: S3 (* default: FX2 PON).

Warning! When S3 is turned on (FX2

PON), make sure that no signals are ap-

plied to the input pins when power-rails

are disabled by the USB microcontroller.

The 3.3 V power-rail though is out of the

control of the USB-microcontroller and is

supplied down-converting the 5 V power

supply provided by either the USB-bus or

the B B receptacle connector. In this case,

signals that are applied to the 3.3 V I/O

Trenz Electronic GmbH 7

Spartan-3E FPGA Industrial Micromodule User Manual

banks do not need to be disconnected

when power-rails are disabled by the USB

microcontroller.

DIP Switch S4

S4 enables / disables the FPGA configura-

tion through the SPI interface. The FPGA

configuration through the JTAG interface

cannot be disabled.

When S4 is turned on, the FPGA tries to

configure from the SPI Flash memory. The

FPGA can be configured by the JTAG inter-

face at any time.

When S4 is turned off, the FPGA waits to

be configured by the JTAG interface.

For further information about direct (pure

SPI) / indirect (SPI over JTAG) in-system

programming of SPI flash memories,

please see Xilinx Application Notes XAP-

P951 “Configuring Xilinx FPGAs with SPI

Serial Flash” and XAPP974 “Indirect Pro-

gramming of SPI Serial Flash PROMs with

Spartan-3A FPGAs”.

S4 position

SPI (on)* FPGA configuration: JTAG + SPI

JTAG (off) FPGA configuration: JTAG

Table 10: S4 (* default: SPI).

Warning! When downloading via parallel

JTAG programmer to FPGA, it can happen

that programming fails with Error: "'1' :

Programming terminated. DONE did not

go high." Try setting DIP switch S4 to

JTAG-only. A bug in certain Xilinx iMPACT

versions can cause this.

DIP Switches Overview

Figure 11 summarizes functions and loca-

tion of the four DIP switches.

TAG and SPI

The offset holes for J and J3 allow a re-

movable press fit of standard 0.100 inch

header pins to connect the fly wires

without any soldering necessary.

TAG Header

JTAG signals are available on the dedic-

ated header J through a JTAG program-

mer with flying leads as described in Table

11.

Trenz Electronic GmbH 8

Figure 11: DIP switches overview.

Spartan-3E FPGA Industrial Micromodule User Manual

TMS

TDI

TDO

TCK

GND

Vref (3.3 V)

Table 11: TAG header ( 2).

SPI Header

SPI signals are routed to / from bank of

the FPGA as detailed in Table 1 and made

available on the dedicated header J3 ac-

cessible through an SPI programmer with

flying leads as described in Table 13.

Signal FPGA pin FPGA ball

SPI /S IO_L01P_ U3

SPI D IO_L03N_ T4

SPI Q IO_L16N_ N10

SPI /C IO_L 6N_ U16

Table 12: SPI signal details (bank 2).

SPI /S

SPI D

SPI Q

SPI /C

GND

Vref (3.3 V)

Table 13: SPI header ( 3).

Clock Networks

24 MHz Clock Oscillator

The module has a 4 MHz SMD clock oscil-

lator providing a clock source for both the

USB microcontroller and the FPGA as de-

tailed in Table 14.

Trenz Electronic GmbH 9

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