Toradex Colibri T30 Mode d’emploi

Colibri Computer Module

Carrier Board Design Guide

Colibri Carrier Board Design Guide

Toradex AG l Altsagenstrasse 5 l 6048 Horw l Switzerland l +41 41 500 48 00 l www.toradex.com l info@toradex.com

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Issued by:

Toradex

Document Type:

Carrier Board Design Guide

Purpose:

This document is a guideline for developing a carrier board that confirms to the specifications

for the Colibri Computer Module

Document

Version:

1.3

Revision History

Date

Version

Remarks

13 April 2015

V1.0

Initial Release: Preliminary Version

28 Sept 2015

V1.1

Correct figure 3 and figure 4 in section 2.3.2 (positive and negative USB

signals where swapped in schematics)

22 October 2015

V1.2

Corrections in figure 4 in section 2.3.2 (pull up resistor of USB_OC# and

pull down of USBH_EN where swapped)

Correction in typical pull up value for I2C in section 2.9

15 June 2016

V1.3

Add section 2.1.4 “Pin Reset State”

Section 2.16: Update information to input voltage range

Section 2.17: Add note to the usage of PXA270

Section 3.1.3: insert information to nVDD_FAULT, nGPIO_RESET, and

nBATT_SENSE

Section 3.5: Add information to bulk capacitors.

 
 
Colibri Carrier Board Design Guide 
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1Introduction ....................................................................................................................... 5 
1 Overview............................................................................................................................. 5 
2 Additional Documents .......................................................................................................... 5 
2.1 Layout Design Guide.................................................................................................5 
2.2 Colibri Module Datasheets.........................................................................................5 
2.3 Toradex Developer Centre.........................................................................................5 
2.4 Colibri Evaluation Board Schematics ..........................................................................5 
2.5 Pinout Designer ........................................................................................................6 
3 Abbreviations....................................................................................................................... 6 
2Interfaces........................................................................................................................... 8 
1 Architecture......................................................................................................................... 8 
1.1 Standard Interfaces...................................................................................................8 
1.2 Interfaces on Alternative Functions.............................................................................8 
1.3 Pin Numbering ..........................................................................................................9 
2 Ethernet............................................................................................................................ 10 
2.1 Ethernet Signals......................................................................................................10 
2.2 Reference Schematics.............................................................................................10 
2.3 Unused Ethernet Signals Termination.......................................................................11 
3 USB.................................................................................................................................. 11 
3.1 USB Signals ...........................................................................................................11 
3.2 Reference Schematics.............................................................................................12 
3.3 Unused USB Signal Termination ..............................................................................13 
4 Parallel RGB LCD Interface................................................................................................ 13 
4.1 Parallel RGB LCD Signals .......................................................................................13 
4.2 Reference Schematics.............................................................................................14 
4.3 Unused Parallel RGB Interface Signal Termination....................................................16 
5 HDMI/DVI.......................................................................................................................... 17 
5.1 HDMI/DVI Signals ...................................................................................................17 
5.2 Reference Schematics.............................................................................................17 
5.3 Unused HDMI/DVI Signal Termination......................................................................19 
6 Analogue VGA................................................................................................................... 20 
6.1 VGA Signals ...........................................................................................................20 
6.2 Reference Schematics.............................................................................................20 
6.3 Unused VGA Interface Signal Termination ................................................................21 
7 Parallel Camera Interface................................................................................................... 21 
7.1 Parallel Camera Signals ..........................................................................................21 
7.2 Unused Parallel Camera Interface Signal Termination ...............................................22 
8 SD/MMC/SDIO .................................................................................................................. 22 
8.1 SD/MMC/SDIO Signals............................................................................................22 
8.2 Reference Schematics.............................................................................................23 
8.3 Unused SD/MMC/SDIO Interface Signal Termination.................................................23 
9 I2C.................................................................................................................................... 23 
9.1 I2C Signals..............................................................................................................23 
9.2 Real-Team Clock (RTC) recommendation.................................................................23 
9.3 Unused I2C Signal Termination.................................................................................24 
10 UART................................................................................................................................ 24 
10.1 UART Signals......................................................................................................25 
10.2 Reference Schematics .........................................................................................25 
10.3 Unused UART Signal Termination.........................................................................27 
11 SPI ................................................................................................................................... 27 
11.1 SPI Signals..........................................................................................................28 
11.2 Unused SPI Signal Termination ............................................................................28 
12 CAN.................................................................................................................................. 28 
12.1 Reference Schematics .........................................................................................28 
13 PWM................................................................................................................................. 28 
13.1 PWM Signals.......................................................................................................29 

 
 
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13.2 Reference Schematics .........................................................................................29 
13.3 Unused PWM Signal Termination..........................................................................29 
14 Analogue Audio ................................................................................................................. 29 
14.1 Analogue Audio Signals .......................................................................................29 
14.2 Reference Schematics .........................................................................................30 
14.3 Unused Analogue Audio Signal Termination ..........................................................31 
15 Touch Panel Interface ........................................................................................................ 31 
15.1 Resistive Touch Signals .......................................................................................31 
15.2 Reference Schematics .........................................................................................32 
15.3 Unused Touch Panel Interface Signal Termination .................................................32 
16 Analogue Inputs................................................................................................................. 32 
16.1 Analogue Input Signals.........................................................................................32 
16.2 Unused Analogue Inputs Signal Termination..........................................................32 
17 Parallel Memory Bus (External Memory Bus)....................................................................... 33 
17.1 Memory Bus Signals ............................................................................................33 
17.2 Unused Memory Bus Signals Termination .............................................................34 
18 GPIO ................................................................................................................................ 35 
18.1 Preferred GPIO Signals........................................................................................35 
18.2 Unused GPIO Termination....................................................................................35 
3Power Management........................................................................................................... 36 
1 Power Signals ................................................................................................................... 36 
1.1 Digital Supply Signals..............................................................................................36 
1.2 Analogue Supply Signals .........................................................................................36 
1.3 Power Management Signals ....................................................................................36 
2 Power Block Diagram......................................................................................................... 37 
3 Power States..................................................................................................................... 39 
4 Power-Up Sequence.......................................................................................................... 39 
5 Reference Schematics ....................................................................................................... 40 
4Mechanical and Thermal Consideration............................................................................... 42 
1 Module Connector.............................................................................................................. 42 
2 Fixation of the Module........................................................................................................ 42 
3 Thermal Solution................................................................................................................ 44 
4 Module Size ...................................................................................................................... 44 
5Appendix A –Physical Pin Definition and Location............................................................... 45 
 

Colibri Carrier Board Design Guide

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1 Introduction

1.1 Overview

This document guides the development of a customized carrier board for the Colibri computer

module. It describes the different interfaces and contains reference schematics. This document

reflects only the standardized primary function of the Colibri modules. The alternative functions are

not guaranteed to be compatible between different Colibri modules. These interfaces are described

in the datasheet of each computer module. Some Colibri modules do not feature the full set of

standard interfaces. Therefore, it is strongly recommended to read the datasheets of the modules

that are intended to be used with the carrier board.

Some of the Colibri computer module interfaces such as High-Speed USB, Ethernet, etc. require

special layout considerations regarding trace impedance and length matching. Please carefully

read the Toradex Layout Design Guide for additional information related to the routing of these

interfaces.

1.2 Additional Documents

1.2.1 Layout Design Guide

This document contains layout requirement specifications for the high-speed signals and helps in

avoiding problems related to the layout.

http://developer.toradex.com/hardware-resources/arm-family/carrier-board-design

1.2.2 Colibri Module Datasheets

There is a datasheet available for every Colibri module. Amongst other things, this document

describes the type-specific interfaces and the alternative function of the pins. Before starting the

development of a customized carrier board, please check this document to find out whether the

required interfaces are really available on the selected modules.

https://www.toradex.com/products/apalis-arm-computer-modules

1.2.3 Toradex Developer Centre

You can find a lot of additional information at the Toradex Developer Centre, which is updated

with the latest product support information on a regular basis.

Please note that the Developer Centre is common for all Toradex products. You should always

check to ensure if the information is valid or relevant for the specific Colibri modules.

http://www.developer.toradex.com

1.2.4 Colibri Evaluation Board Schematics

We provide the complete schematics plus the Altium project file for the Colibri Evaluation Board for

free. This is a great help when designing your own Carrier Board.

http://developer.toradex.com/hardware-resources/arm-family/carrier-board-design

Colibri Carrier Board Design Guide

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1.2.5 Pinout Designer

This is an interactive and useful tool for configuring the pin muxing of the Colibri and Apalis

modules. It can be really helpful in custom carrier board development on Toradex modules and for

checking the compatibility of existing carrier boards with our modules.

http://developer.toradex.com/knowledge-base/pinout-designer

1.3 Abbreviations

Abbreviation

Explanation

ADC

Analogue to Digital Converter

AGND

Analogue Ground - separate ground for analogue signals

Auto-MDIX

Automatically Medium Dependent Interface Crossing - a PHY with Auto-MDIX f is able to detect whether

RX and TX need to be crossed (MDI or MDIX)

CAD

Computer-Aided Design - in this document is referred to PCB Layout tools

CAN

Controller Area Network - a bus that is manly used in automotive and industrial environment

CDMA

Code Division Multiplex Access - abbreviation often used for a mobile phone standard for data

communication

CEC

Consumer Electronic Control - HDMI feature that allows to control CEC compatible devices

CPU

Central Processor Unit

CSI

Camera Serial Interface

DAC

Digital to Analogue Converter

DDC

Display Data Channel - interface for reading out the capability of a monitor, in this document DDC2B

(based on I2C) is always meant

DRC

Design Rule Check - a tool for checking whether all design rules are satisfied in a CAD tool

DSI

Display Serial Interface

DVI

Digital Visual Interface - digital signals are electrical compatible with HDMI

DVI-A

Digital Visual Interface Analogue only - signals are compatible with VGA

DVI-D

Digital Visual Interface Digital only - signals are electrical compatible with HDMI

DVI-I

Digital Visual Interface Integrated - combines digital and analogue video signals in one connector

EDA

Electronic Design Automation - software for schematic capture and PCB layout (CAD or ECAD)

EDID

Extended Display Identification Data - timing setting information provided by the display in a PROM

EMI

Electromagnetic Interference - high frequency disturbances

eMMC

Embedded Multi Media Card - flash memory combined with MMC interface controller in a BGA package,

used as internal flash memory

ESD

Electrostatic Discharge - high voltage spike or spark that can damage electrostatic- sensitive devices

FPD-Link

Flat Panel Display Link - high-speed serial interface for liquid crystal displays. In this document also called

LVDS interface.

GBE

Gigabit Ethernet - Ethernet interface with a maximum data rate of 1000Mbit/s

GND

Ground

GPIO

General Purpose Input/Output pin that can be configured to be either an input or output

GSM

Global System for Mobile Communications

HDA

High Definition Audio (HD Audio) - digital audio interface between CPU and audio codec

HDCP

High-Bandwidth Digital Content Protection - copy protection system that is used by HDMI beside others

HDMI

High-Definition Multimedia Interface - combines audio and video signal for connecting monitors, TV sets

or Projectors, electrical compatible with DVI-D

I2C

Inter-Integrated Circuit - two wire interface for connecting low speed peripherals

I2S

Integrated Interchip Sound - serial bus for connecting PCM audio data between two devices

IrDA

Infrared Data Association - infrared interface for connecting peripherals

JTAG

Joint Test Action Group - widely used debug interface

LCD

Liquid Crystal Display

LSB

Least Significant Bit

LVDS

Low-Voltage Differential Signaling - electrical interface standard that can transport very high-speed

signals over twisted-pair cables. Many standard interfaces like PCIe or SATA use this interface standard.

Colibri Carrier Board Design Guide

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Abbreviation

Explanation

Since the first successful application was the Flat Panel Display Link, LVDS has become synonymous for

this interface. In this document, the term LVDS is used for the FPD-Link interface.

MIPI

Mobile Industry Processor Interface Alliance

MDI

Medium Dependent Interface - physical interface between Ethernet PHY and cable connector

MDIX

Medium Dependent Interface Crossed - an MDI interface with crossed RX and TX interfaces

mini PCIe

PCI Express Mini Card - card form factor for internal peripherals. The interface features PCIe and USB

2.0 connectivity

MMC

MultiMediaCard - flash memory card

MSB

Most Significant Bit

mSATA

Mini-SATA - a standardized form factor for small solid state drive, similar dimensions as mini PCIe

N/A

Not Available

N/C

Not Connected

Open Drain

OTG

USB On-The-Go - a USB host interface that can also act as USB client when connected to another host

interface

OWR

One Wire (1-Wire) - low speed interface which needs just one data wire plus ground

PCB

Printed Circuit Board

PCI

Peripheral Component Interconnect - parallel computer expansion bus for connecting peripherals

PCIe

PCI Express - high-speed serial computer expansion bus, replaces the PCI bus

PCM

Pulse-Code Modulation - digital representation of analogue signals and a standard interface for digital

audio

Pull Down Resistor

PHY

Physical Layer of the OSI model

PMIC

Power Management IC - integrated circuit that manages amongst others the power sequence of a system

Pull-up Resistor

PWM

Pulse-Width Modulation

RGB

Red Green Blue - color channels in common display interfaces

RJ45

Registered Jack - common name for the 8P8C modular connector that is used for Ethernet wiring

RS232

Single ended serial port interface

RS422

Differential signaling serial port interface - full duplex

RS485

Differential signaling serial port interface - half duplex, multi drop configuration possible

R-UIM

Removable User Identity Module - identifications card for CDMA phones and networks, an extension of

the GSM SIM card

S/PDIF

Sony/Philips Digital Interconnect Format - optical or coaxial interface for audio signals

SATA

Serial ATA, high-speed differential signaling interface for hard drives and SSD

Secure Digital - flash memory card

SDIO

Secure Digital Input Output - an external bus for peripherals that uses the SD interface

SIM

Subscriber Identification Module - identification card for GSM phones

SMBus

System Management Bus (SMB) - two wire bus based on the I2C specifications, used specially in x86

design for system management.

SoC

System on a Chip - IC which integrates the main component of a computer on a single chip

SO-DIMM

Small Outline Dual Inline Memory Module - form factor for mobile RAM modules, the Colibri module uses

the SO-DIMM (DDR, 2.5V variant) connector as main interface

SPI

Serial Peripheral Interface Bus - synchronous four wire full duplex bus for peripherals

TIM

Thermal Interface Material - thermal conductive material between CPU and heat spreader or heat sink

TMDS

Transition-Minimized Differential Signaling - serial high-speed transmitting technology that is used by DVI

and HDMI

TVS Diode

Transient-Voltage-Suppression Diode - diode that is used to protect interfaces against voltage spikes

UART

Universal Asynchronous Receiver/Transmitter - serial interface, in combination with a transceiver a

RS232, RS422, RS485, IrDA or similar interface can be achieved

USB

Universal Serial Bus - serial interface for internal and external peripherals

VCC

Positive supply voltage

VGA

Video Graphics Array - analogue video interface for monitors

Table 1: Abbreviations

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2 Interfaces

2.1 Architecture

2.1.1 Standard Interfaces

The standard interfaces on the Colibri module family intent to provide electrical and functional

compatibility between module family members. The table below shows an overview of the

standard interfaces that are provided by a Colibri module. The “GPIO Capable” column indicates

whether the assigned pins are intent to be also used as GPIOs. “Yes”and “No”are self-

Explanatory. “Optional”indicates that it may be possible for some modules, but not all.

The “Standard” column indicates the number of interfaces that the specification allows for in the

standard pin-out. Customers should consult the datasheet for specific Colibri module variants to

check which of the interfaces are available for that module.

Description

Standard

Note

GPIO

Capable

4/5 Wire Resistive Touch

Touch wiper shared with analogue input 4

Analogue Inputs

Minimum 8 bit resolution, 0-3.3V nominal range

Analogue Audio

Line in L&R, Microphone in, Headphone out L&R

Fast Ethernet

HDMI (TDMS)

Located on dedicated FFC connector

(availability depending on Module)

I2C

Additional dedicated DDC available on FFC connector

Yes

Parallel Camera

8 bit BT.656 (other modes may available)

Yes

Parallel LCD

18 bit resolution (additional bits may available)

Yes

Parallel Memory Bus

Supported bus width depends on Module

Optional

PWM

Yes

SDIO

4 bit

Yes

SPI

Yes

UART

1x Full Featured, 1x CTS/RTS, 1x RXD/TXD only

Yes

USB

1x shared host/client, 1x host only

VGA

Located on dedicated FFC connector

(availability depending on Module)

Table 2: Standard Interfaces

2.1.2 Interfaces on Alternative Functions

Many SoC pins can be used for more than one function. This allows the modules provide many

additional interfaces to the standard set. For example, in the Colibri standard there is only one SPI

interface listed. Nevertheless, some modules can provide up to 6 SPI interfaces.

Please note that there are a few restrictions of using the interfaces that are provided as alternative

functions of the pins. There is limited compatibility between their availability at different modules.

For a design to be compatible with a wide range of Colibri modules, it is recommended to mainly

use the standard interfaces. The various pins can be used for only one function each

simultaneously.

The configuration of the alternative function interfaces can be quite complex. Toradex provides a

powerful tool which helps the development engineer to resolve pin muxing conflicts. The tool is

called Pinout Designer. It reduces the complexity of this important task. More information including

its download link can be found here: http://developer.toradex.com/knowledge-base/pinout-

designer.

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The interfaces on the alternative functions are not described in this document since they differ

between the modules. Information related to these functions can be found in the datasheets of the

modules.

2.1.3 Pin Numbering

The diagrams in the figures below show the pin numbering schema on both sides of the module.

The schema is equals to the JEDEC MO-224 DDR SO-DIMM standard. The odd pin numbers are

located on the top side of the module.

Figure 1: Colibri Module Pin Numbering Schema

2.1.4 Pin Reset State

The datasheets of the Colibri module provide information about the default reset status of the IO

pins. Please be aware, the pin reset status is only guaranteed during the release of the reset

signal. Some of the modules switches the IO bank voltages in order to follow the power up

sequence of the SoC. This means, the IO pins can have an undefined state between applying the

main power to the module until the nRESET_OUT is released. For carrier board designs that do not

allow undefined pin states, it is recommended to make sure that the peripheral devices are not

getting powered before the nRESET_OUT is released. Another solution can be gating the according

IO signals with the nRESET_OUT signal.

Pin1 Pin47Pin39 Pin199

Pin2 Pin42Pin40 Pin200

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2.2 Ethernet

The Colibri module standard features a fast 10/100Mbit Ethernet (10/100Base-TX) interface port.

The required center tap circuit can differ between the modules. Different assembly options might

be needed for supporting the complete Colibri module family. Some modules support Auto MDIX,

which means they can swap the transmitting with the receiving lanes. Read the corresponding

datasheet of the module for more information about the availability of the Auto MDIX function.

2.2.1 Ethernet Signals

Colibri

Signal Name

I/O

Type

Power

Rail

Description

189

ETH_1_TXO+

Analogue

100BASE-TX: Transmit + (Auto MDIX: Receive +)

187

ETH_1_TXO-

Analogue

100BASE-TX: Transmit - (Auto MDIX: Receive -)

195

ETH_1_RXI+

Analogue

100BASE-TX: Receive + (Auto MDIX: Transmit +)

193

ETH_1_RXI-

Analogue

100BASE-TX: Receive - (Auto MDIX: Transmit -)

191

AGND_LAN

Ethernet ground, on some modules connected to common GND

183

ETH_1_LINK_AKT

CMOS

3.3V

LED indication output for link activity on the Ethernet port

185

ETH_1_SPEED100

CMOS

3.3V

LED indication output for 100Mbit/s

Table 3: Ethernet Signals

2.2.2 Reference Schematics

Ethernet connectors with integrated magnetics are preferable. If a design with external magnetics

is chosen, additional care has to be taken to route the signals between the magnetics and Ethernet

connector.

The LED output signals ETH_1_LINK_AKT and ETH_1_SPEED100 can be connected directly to the

LED of the Ethernet jack with suitable serial resistors. There is no need for additional buffering if

the current drawn does not exceeds 10mA.

The Fast Ethernet interface uses the ETH_1_TXO as transmitting lanes and the ETH_1_RXI as

receiving lane. If the Ethernet PHY features Auto-MDIX, the signal lanes RX and TX could be

swapped. We strongly recommend not swapping the RX and TX lanes in order to keep the

compatibility with all Colibri modules.

The required center tap circuit depends on the supported modules. Currently, the Ethernet

controller on the PXA270 module is the only one which requires a different center tap circuit since

it does not support Auto-MDIX. All the other currently available modules feature a current control

PHY which requires 3.3V supply at the center tap of the RX and TX lanes. Since all the Ethernet PHY

manufacturer are tending to change from current mode to voltage mode which requires leaving

the center tab pins of the magnetics unconnected, we recommend to add additional 0R resistors

into the center tab lines. This ensures that the carrier board design is ready for any future Colibri

module with voltage mode PHY.

Table des matières

Autres manuels Toradex Unité de contrôle

Toradex

Toradex Apalis Series Mode d’emploi

Toradex

Toradex Verdin Manuel utilisateur

Toradex

Toradex Colibri PXA270 Manuel utilisateur

Manuels Unité de contrôle populaires d'autres marques

Festo

Festo Compact Performance CP-FB6-E Manuel de la liste des pièces

Elo TouchSystems

Elo TouchSystems DMS-SA19P-EXTME Manuel utilisateur

JS Automation

JS Automation MPC3034A Manuel utilisateur

JAUDT

JAUDT SW GII 6406 Series Guide rapide

Spektrum

Spektrum Air Module System Manuel utilisateur

BOC Edwards

BOC Edwards Q Series Manuel utilisateur

KHADAS

KHADAS BT Magic Manuel utilisateur

Etherma

Etherma eNEXHO-IL Manuel utilisateur

PMFoundations

PMFoundations Attenuverter Manuel utilisateur

GEA

GEA VARIVENT Manuel utilisateur

Walther Systemtechnik

Walther Systemtechnik VMS-05 Manuel utilisateur

Altronix

Altronix LINQ8PD Instructions de montage

Eaton

Eaton Powerware Series Manuel utilisateur

WAGO

WAGO 750-407/040-000 Manuel utilisateur

Sony

Sony CCU-590 Manuel utilisateur

Graco

Graco 25D614 Manuel utilisateur

Task Force Tips

Task Force Tips YE-RF-900 Manuel de programmation

Shini

Shini SPV-U Series Manuel utilisateur