Texas Instruments UCC21551CQEVM-079 Manuel utilisateur
EVM User's Guide: UCC21551CQEVM-079
UCC21551CQEVM-079 Evaluation Module
Description
The UCC21551CQEVM-079 is a two copper layer
PCB containing multiple test points and jumpers
to fully evaluate the functionality of the UCC21551
gate driver. The EVM features PWM input control,
onboard adjustable power supply, sockets for discrete
FETs, external active clamp for low side protection,
bootstrapped high side power supply, negative gate
voltage capability, configurable deadtime switches,
EN/DIS jumpers, and socket for Wolfspeed XM3 SiC-
based half bridge power modules. The layout has
been optimized to minimize gate loop area for each
channel and placement of bypass capacitors allow for
clean and sharp signal reading with minimal noise
interference.
Features
• Variety of test points to help evaluate all of the gate
driver functions
• Onboard isolated adjustable bias supply
configured for 20 V
• Selectable dead time modes: overlap, interlock,
programmable
• Low side external active clamping circuit
• 16 V/-3V Zener negative voltage pulldown circuit
for SiC FETs
• Socket for Wolfspeed XM3 module
PCB Top Side
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UCC21551CQEVM-079 Evaluation Module 1
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1 Evaluation Module Overview
1.1 Introduction
The UCC21551CQEVM evaluation module is designed for evaluating TI’s UCC2155XX family of gate drivers.
The UCC2155XX is a 5.7-kVrms isolated dual-channel gate driver with 4-A source and 6-A sink peak current for
driving Si MOSFETs, IGBTs and WBG devices such as SiC and GaN transistors. This guide provides a complete
EVM schematic diagram, printed circuit board layout, bill of materials, test setup, and feature descriptions for
the UCC21551C. To evaluate other Iso-Drivers in the UCC2155XX family, TI recommends that the user read the
data sheet thoroughly before switching the part in the EVM covered by this user guide.
CAUTION
!
Caution Read the user's guide before use.
CAUTION
Caution Hot surface. Contact can cause
burns. Do not touch!
WARNING
Danger
Do not use EVM to test isolation
above VIOWM = 1414 VDC.
High voltage.
1.2 Kit Contents
• UCC21551CQEVM-079 two layer PCB
1.3 Specification
UCC21551CQEVM-079 primary function is to evaluate the UCC2155xx dual channel gate driver family. Multiple
test points enable monitoring of the different input and outputs of the gate driver for thorough performance
evaluation. The gate driver output can be configured to drive a capacitive loads for low voltage testing as well as
discrete MOSFETs in a halfbridge configuration.
1.4 Device Information
The UCC21551x-Q1 is an isolated dual channel gate driver family with programmable dead time and wide
temperature range. The device is designed with 4-A peak- source and 6-A peak-sink current to drive power
MOSFET, SiC, and IGBT transistors.
The UCC21551x-Q1 can be configured as two low- side drivers, two high-side drivers, or a half-bridge driver.
The input side is isolated from the two output drivers by a 5-kVRMS isolation barrier, with a minimum of 125-V/ns
common-mode transient immunity (CMTI).
Protection features include: resistor programmable dead time, disable feature to shut down both outputs
simultaneously, and integrated de-glitch filter that rejects input transients shorter than 5 ns. All supplies have
UVLO protection.
With all these advanced features, the UCC21551x- Q1 device enables high efficiency, high power density, and
robustness in a wide variety of power applications.
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1.5 General TI High Voltage Evaluation User Safety Guidelines
WARNING
Always follow TI’s set-up and application instructions, including use of all interface components within the
recommended electrical rated voltage and power limits. Always use electrical safety precautions to help ensure
your personal safety and the safety of those working around you. Contact TI’s Product Information Center http://
support/ti./com for further information.
Save all warnings and instructions for future reference.
Failure to follow warnings and instructions can result in personal injury, property damage, or death due
to electrical shock and/or burn hazards.
The term TI HV EVM refers to an electronic device typically provided as an open framed, unenclosed printed
circuit board assembly. It is intended strictly for use in development laboratory environments, solely for qualified
professional users having training, expertise, and knowledge of electrical safety risks in development and
application of high-voltage electrical circuits. Any other use and/or application are strictly prohibited by Texas
Instruments. If you are not suitably qualified, you must immediately stop from further use of the HV EVM.
•Work Area Safety:
– Maintain a clean and orderly work area .
– Qualified observers must be present anytime circuits are energized.
– Effective barriers and signage must be present in the area where the TI HV EVM and the interface
electronics are energized, indicating operation of accessible high voltages can be present, for the purpose
of protecting inadvertent access.
– All interface circuits, power supplies, evaluation modules, instruments, meters, scopes and other related
apparatus used in a development environment exceeding 50 VRMS/75 VDC must be electrically located
within a protected Emergency Power Off (EPO) protected power strip.
– Use a stable and non-conductive work surface.
– Use adequately insulated clamps and wires to attach measurement probes and instruments. No freehand
testing whenever possible.
•Electrical Safety:
As a precautionary measure, a good engineering practice is to assume that the entire EVM can have fully
accessible and active high voltages.
– De-energize the TI HV EVM and all the inputs, outputs, and electrical loads before performing any
electrical or other diagnostic measurements. Confirm that TI HV EVM power has been safely de-
energized.
– With the EVM confirmed de-energized, proceed with required electrical circuit configurations, wiring,
measurement equipment hook-ups and other application needs, while still assuming the EVM circuit and
measuring instruments are electrically live.
– When EVM readiness is complete, energize the EVM as intended.
WARNING
WARNING: While the EVM is energized, never touch the EVM or the electrical circuits as
the EVM or electrical circuits can be at high voltages capable of causing electrical shock
hazard.
•Personal Safety:
– Wear personal protective equipment, for example, latex gloves and/or safety glasses with side shields or
protect EVM in an adequate lucent plastic box with interlocks from accidental touch.
•Limitation for Safe Use:
– EVMs are not to be used as all or part of a production unit.
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The EVM is designed for professionals who have received the appropriate technical training, and is designed
to operate from an AC power supply or a high-voltage DC supply. Please read this user guide and the safety-
related documents that come with the EVM package before operating this EVM.
CAUTION
!
Do not leave the EVM powered when unattended.
WARNING
High Voltage! Electric shock is possible when connecting board to live wire. Board must be handled
with care by a professional.
For safety, use of isolated test equipment with overvoltage and overcurrent protection is highly
recommended.
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2 Hardware
2.1 Power Requirements
Table 2-1. UCC21551CQEVM-079 Electrical Specifications
Description Min Typ Max Units
VIN Enable for UCC21551 and UCC14240 3.3 5 5 V
VBIAS Primary side input voltage UCC14240 21 24 27 V
VDDB
VDDA
UCC21551C output bias supply voltage
See data sheet for UCC2155XX variants 13.5 25 V
Fs Switching frequency 0 500 KHz
DC Voltage on DC+ for half bridge application 0 800 V
Tj Operating junction temperature -40 150 °C
2.2 Header Information
Table 2-2. Headers Description
Header Marker Description
J5 Dead time setting
J7 Gate driver enable/disable
J20 Bias supply enable/disable
J22 Unused
J23 PWM mode toggle
2.3 Jumper Information
Table 2-3. Jumper Configurations
Header Jumper Settings Default
J5
VCC1-DT
DT-GND
Unconnected
DT-GND: enables gate driver interlock mode
J7 XEN-GND
XEN-VCC1
XEN-VCC1: connects VCC1 to UCC21551 EN pin,
enabling gate driver
J20 VCC1-ENA
ENA-GND VCC1-ENA: enables UCC14240 bias supply
J23 Connected
Unconnected Unconnected: disables single input PWM mode
2.4 Connectors Information
Table 2-4. Connectors Description
Connector Description
J18 VCC1 Input for UCC14240 3.3-5V
J21 VIN Input for UCC14240 21-27V
2.5 Interfaces Information
Table 2-5. Interfaces Description
Interface Description
J8 DC+
J9 Switch node
J12 DC-
J16A XM3 Wolfspeed Socket CHA Gate
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Table 2-5. Interfaces Description (continued)
Interface Description
J16B XM3 Wolfspeed Socket CHA VSSA
J17A XM3 Wolfspeed Socket CHB Gate
J17B XM3 Wolfspeed Socket CHB VSSB
Q1 Socket for discrete FET1
Q2 Socket for discrete FET2
2.6 Test Points
Table 2-6. Test Point Description
Test Point Test Point Board Marker Description
TP1 VBIAS/VCC1 EN for UCC14240
TP2 INA Input for channel A
TP3 INB Input for channel B
TP4 VDDA Output side channel A supply
TP5 GND Input side ground
TP6 GND Input side ground
TP7 GND Input side ground
TP8 VSSA Output side channel A ground
TP9 VSSB Output side channel B ground
TP11 XEN Test point to apply an external enable signal
TP12 PG Fault pin for detecting fault status for UCC14240
TP15 ENA Test point for measuring UCC14240 enable signal
TP16 VDDB Output side channel B supply
TP17 VIN Test point for primary supply for UCC14240 (21V-27V)
TP18 GND Input side ground
TP19 VGA Q1 FET gate
TP21 VGB Q2 FET gate
J1 VIN MMCX pad for primary supply for UCC14240 (21V-27V)
J2 VDDA MMCX pad for output side channel A supply
J3 OUTA MMCX pad for channel A output
J4 VGA MMCX pad for Q1 gate
J6 DT MMCX pad for Deadtime pin
J10 INA MMCX pad for input to channel A
J11 INB MMCX pad for input to channel B
J13 VDDB MMCX pad for output side channel B supply
J14 OUTB MMCX pad for channel B output
J15 VGB MMCX pad for Q2 gate
J19 VDDB MMCX pad for output low side supply
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3 Implementation Results
3.1 Evaluation Setup
This section describes the default EVM configurations and recommended test set up for the UCC21551-Q1
EVM.
Equipment
The following equipment is recommended for testing the EVM:
• One DC supply capable of 5 V/0.5A, for example: Keysight E3634A.
• One DC supply capable of 24 V/0.5A, for example: Keysight E3634A.
• One Arbitrary Function Generator, dual channel, for example: Tektronix AFG3102A
• One Oscilloscope, at least 3 channels, bandwidth 200 MHz or above, for example, Tektronix MDO3054 or
TDS3054C.
• Three passive oscilloscope probes, bandwidth 200 MHz or above. For example, TPP1000 like probe with a
ground spring.
• 4X BNC to Grabber Cables for input and supply connections.
• Banana plug connector.
Equipment Configurations
•DC Power Supply Settings
–DC Supply 1:
• Voltage setting: 5 V
• Current limit: 0.5A
–DC Supply 2:
• Voltage setting: 24 V
• Current limit: 0.5A
•Function Generator Settings
–Function: Pulse
–CH1: High: 5 V, Low: 0 V
–CH2: High: 5 V, Low: 0 V
•Oscilloscope Settings
–CH1-CH3:
• DC coupling
• Highest bandwidth setting available
• Termination 1M or automatic
• Probe scale: 10X or auto
Equipment Setup
•Jumper Connections
–J7: Shunt XEN to VCC
–J20: Shunt ON to EN
–J5: Shunt DT to GND
–SDT_DT1: All switches in the left most position
•Oscilloscope Connections
–CH1: VGA to VSSA
–CH2: VGB to VSSB
–CH3: VDDB to VSSB
•Function Generator
–CH1: INB to GND
–CH2: INA to GND
•Power Supply
–DC Supply 1: J18
–DC Supply 2: J21
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If testing the EVM with FETs, then populate Q1 and Q2 or the XM3 connector. If testing the EVM without FETs,
then place a banana plug connector between SW and DC-. See Figure 3-1 for a visual of the default test
connections.
Figure 3-1. Default Connections Without Load
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3.2 Performance Data and Results
Test Procedure
•Power Up
1. Before proceeding make sure the EVM and all equipment is setup as described in section Equipment
Configurations and Equipment Setup.
2. Turn on the 5 V and 24 V power supply. Probing VDDB(TP16)-VSSB(TP9) measures 20 V. Probing
VCC1(TP1)-GND(TP6) measures 5 V.
3. Turn on both channels of the function generator.
4. Use any probe of choice to verify that there is a 5 KHz, 5 V, pulse on INA and INB each with respect to
GND.
5. Probing VGA-VSSA and VGB-VSSB shows a PWM output signal from the gate driver going up to +16V
when HIGH and -3V when LOW as shown in Figure 3-2.
Figure 3-2. Power-up Test: Switching at 5 kHz
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Deadtime Configuration
The UCC21551 has 3 dead time modes that are selectable with the UCC21551CQEVM. Those modes are
Interlock, Programmable, and Overlap.
•Interlock Mode: Interlock mode sets a minimum delay of approximately 5 ns between gate driver outputs to
prevent the channels from overlapping. This mode is initiated when the dead time pin is grounded (Shunting
J5 to DT-GND). The dead time is defined as the delay between 90% of the falling edge of the first output and
10% of the rising edge of the second output. Timing is illustrated in Figure 3-3. See Figure 3-4for an example
of Interlock mode.
Figure 3-3. Timing Diagram
Figure 3-4. Interlock Mode
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