Texas Instruments DS160PR810EVM-RSC Manuel utilisateur
User’s Guide
DS160PR810EVM-RSC Evaluation Module (EVM)
ABSTRACT
The DS160PR810EVM-RSC evaluation modules provides a complete high-bandwidth platform for evaluating the
signal conditioning features of the Texas Instruments DS160PR810 Octal-Channel PCI-Express 4.0 Linear
Redriver. This evaluation board can be used for standard compliance testing, performance evaluation, and initial
system prototyping.
Figure 1-1. DS160PR810EVM-RSC - Top Side View
Table of Contents
1 Introduction.............................................................................................................................................................................2
1.1 Features............................................................................................................................................................................. 2
1.2 Applications........................................................................................................................................................................2
2 Description.............................................................................................................................................................................. 3
2.1 DS160PR810 4-Level I/O Control Inputs........................................................................................................................... 3
2.2 DS160PR810 Modes of Operation.....................................................................................................................................3
2.3 DS160PR810 SMBus or I2C Register Control Interface....................................................................................................4
2.4 DS160PR810 Equalization Control.................................................................................................................................... 5
2.5 DS160PR810 RX Detect State Machine............................................................................................................................6
2.6 DS160PR810 DC Gain Control..........................................................................................................................................6
2.7 DS160PR810 EVM Global Controls ..................................................................................................................................7
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2.8 DS160PR810EVM Downstream Devices Control..............................................................................................................8
2.9 DS160PR810EVM Upstream Devices Control.................................................................................................................. 9
2.10 Quick-Start Guide (Pin Mode)........................................................................................................................................ 10
2.11 Quick-Start Guide (SMBus Slave Mode)........................................................................................................................10
3 Test Setup and Results........................................................................................................................................................ 12
4 Schematics............................................................................................................................................................................13
5 Board Layout.........................................................................................................................................................................21
6 Bill of Materials..................................................................................................................................................................... 23
7 References............................................................................................................................................................................ 27
Trademarks
All trademarks are the property of their respective owners.
1 Introduction
The DS160PR810EVM-RSC evaluation module features four DS160PR810 linear redrivers that can extend the
transmission distance of a PCIe Gen-4 x16 bus. It can directly be plugged into a PCIe slot on a server or PC
motherboard using one end of the board, and paired up with a PCIe add-in card using the straddle mount
connector attached to the other end of the board.
1.1 Features
• PCIe x16 Riser Card option with four 8-channel unidirectional linear redrivers operating at rates up to 25
Gbps
• Linear equalization for seamless support of link training and PCIe channel extension
• CTLE boosts up to 18 dB at 8 GHz
• Programmable device configuration through GPIO or I2C, SMBus
• Onboard 12-V to 3.3-V, 2-A step-down DC/DC converter
• Industrial temperature range: –40°C to 85°C
• Flow-through layout in 5.5 mm × 10 mm, 64-pin, leadless WQFN 0.4-mm pitch package
1.2 Applications
• PCI Express Gen-1, 2, 3, and 4
• High-speed interfaces up to 25 Gbps
• Enterprise server motherboard, workstation
• Enterprise storage
• Enterprise add-in card, end-point
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2 Description
2.1 DS160PR810 4-Level I/O Control Inputs
Each DS160PR810 features 4-level input pins (MODE, GAIN0, GAIN1, RX_DET, EQ0_0/ADDR0, EQ1_0/
ADDR1, EQ0_1, and EQ1_1) that are used to control the configuration of the device. These 4-level inputs use a
resistor divider to help set the four valid levels to provide a wider range of control settings.
Table 2-1. Four-Level Control Pin Settings
PIN LEVEL PIN SETTING
L0 1 kΩ to GND
L1 13 kΩ to GND
L2 59 kΩ to GND
L3 Float
2.2 DS160PR810 Modes of Operation
Each DS160PR810 can be configured to operate in either Pin Mode, SMBus with I2C Slave Mode, or SMBus
with I2C Master Mode. The mode of operation of the DS160PR810 is determined by the pin strap setting on the
MODE pin as shown in Table 2-2.
Table 2-2. Modes of Operation
MODE PIN LEVEL MODE OF OPERATION
L0 Pin Mode
L1 SMBus Mode or I2C Master
Mode
L2 SMBus Mode or I2C Slave Mode
L3 RESERVED
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2.3 DS160PR810 SMBus or I2C Register Control Interface
The DS160PR810 internal registers can be accessed through standard SMBus protocol. The DS160PR810
features two banks of channels, Bank 0 (Channels 0–3) and Bank 1 (Channels 4–7), each featuring a separate
register set and requiring a unique SMBus slave address. The SMBus slave address pairs (one for each channel
bank) are determined at power up based on the configuration of the EQ0_0/ADDR1 and EQ1_0/ADDR0 pins.
The pin state is read on power up, after the internal power-on reset signal is deasserted.
There are 16 unique SMBus slave address pairs (one address for each channel bank) that can be assigned to
the device by placing external resistor straps on the EQ0_0/ADDR1 and EQ1_0/ADDR0 pins as shown in Table
2-3. When multiple DS160PR810 devices are on the same SMBus interface bus, each channel bank of each
device must be configured with a unique SMBus slave address pair.
Table 2-3. DS160PR810 SMBus Address Map
ADDR1 Pin Level ADDR0 Pin Level Bank 0: Channels 0-3:
7-Bit Address [HEX]
Bank 1 Channels 4-7:
7-Bit Address [HEX]
L0 L0 0x18 0x19
L0 L1 0x1A 0x1B
L0 L2 0x1C 0x1D
L0 L3 0x1E 0x1F
L1 L0 0x20 0x21
L1 L1 0x22 0x23
L1 L2 0x24 0x25
L1 L3 0x26 0x27
L2 L0 0x28 0x29
L2 L1 0x2A 0x2B
L2 L2 0x2C 0x2D
L2 L3 0x2E 0x2F
L3 L0 0x30 0x31
L3 L1 0x32 0x33
L3 L2 0x34 0x35
L3 L3 0x36 0x37
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2.4 DS160PR810 Equalization Control
Each channel of the DS160PR810 features a continuous-time linear equalizer (CTLE) that applies high-
frequency boost and low-frequency attenuation to help equalize the frequency-dependent insertion loss effects
of the passive channel. Table 2-4 shows available equalization boost through EQ control pins (EQ1_0 and
EQ0_0 for channels 0–3 and EQ1_1 and EQ0_1 for channels 4–7) when in Pin Control mode (MODE = L0).
Table 2-4. Equalization Control Settings
EQ INDEX EQ1 PIN LEVEL EQ0 PIN LEVEL CTLE BOOST AT 4 GHz
(dB)
CTLE BOOST AT 8 GHz
(dB)
0 L0 L0 –0.25 –0.5
1 L0 L1 2.0 4.0
2 L0 L2 2.5 5.0
3 L0 L3 3.0 6.0
4 L1 L0 4.0 7.0
5 L1 L1 4.5 7.5
6 L1 L2 5.0 8.0
7 L1 L3 6.0 9.5
8 L2 L0 7.0 10
9 L2 L1 8.0 11
10 L2 L2 8.5 12.5
11 L2 L3 9.0 13
12 L3 L0 9.5 14.5
13 L3 L1 10.0 15
14 L3 L2 10.5 16.0
15 L3 L3 12 18
The equalization gain of each channel of each device can also be set by writing to SMBus, I2C registers in I2C
Mode. Refer to the DS160PR810 Programming Guide (SNLU268) for details.
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2.5 DS160PR810 RX Detect State Machine
Each DS160PR810 deploys an RX Detect state machine that governs the RX detection cycle as defined in the
PCI Express specification. At power up or after a manually triggered event, the redriver determines whether or
not a valid PCI Express termination is present at the far end of the link. The RX_DET pin of DS160PR810
provides additional flexibility to system designers to appropriately set the device in their desired mode, according
to Table 2-5.
Table 2-5. Four-Level Control Pin Settings
PD PIN LEVEL RX_DET/SCL PIN LEVEL DESCRIPTION
L L0 PCI Express RX detection state machine is disabled. Recommended
for non-PCI Express use cases. Inputs are always 50 Ω.
L L1
PCI Express RX detection state machine is enabled. Recommended
for PCI Express use cases. Pre Detect: Hi-Z, Post Detect: 50 Ω.
Outputs poll every approximate 150 μs until 3 consecutive valid RX
termination detections.
L L2
PCI Express RX detection state machine is enabled. Recommended
for PCI Express use cases. Pre Detect: Hi-Z, Post Detect: 50 Ω.
Outputs poll every approximate 150 μs until 2 consecutive valid RX
termination detections.
L L3 (Float)
PCI Express RX detection state machine is enabled. Recommended
for PCI Express use cases. Pre Detect: Hi-Z, Post Detect: 50 Ω.
Outputs poll every approximate 150 μs until a valid RX termination
detection.
H X Manual reset, inputs are Hi-Z
2.6 DS160PR810 DC Gain Control
When operating in Pin Mode, the GAIN pins can be used to set the overall datapath DC (low frequency) gain of
the DS160PR810 as shown in Table 2-6.
Table 2-6. GAIN Control
GAIN/SDA PIN
LEVEL GAIN SETTING
L0 –6 dB
L1 –3 dB
L2 3 dB
L3 0 dB (Recommended for most use cases)
The DC gain of each channel of each device can also be set by writing to SMBus, I2C registers in Slave or
Master Modes. Refer to the DS160PR810 Programming Guide (SNLU268) for details.
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2.7 DS160PR810 EVM Global Controls
Table 2-7 shows DS160PR810EVM-RSC global controls that affect all devices on the board.
Table 2-7. EVM Global Controls
COMPONENT NAME FUNCTION / DESCRIPTION
J1 3x2 Header
MODE control tied to MODE pins of all four DS160PR810 devices on the EVM
L0: All devices set to Pin Mode (Default)
L1: All devices set to SMBus, I2C Maseter Mode
L2: SMBus, I2C Slave Mode
L3: Reserved
J2 3x2 Header
RX DET control tied to RX DET pins of all four DS160PR810 devices on the EVM
L0: RX Detect state machine disabled on all devices
L1: RX Detect state machine enabled on all devices (3 valid detections needed)
L2: RX Detect state machine enabled on all devices (2 valid detections needed)
L3: RX Detect state machine enabled on all devices (1 valid detection needed) -
Default
J3 5x2 Header SMBus, I2C interface. All four DS160PR810 devices on the EVM are on the same
bus and can be accessed through this interface.
J4 3x1 Header
PWDN control tied to PD1 and PD2 pins of all four DS160PR810 devices on the
EVM PWDN tied to GND: All devices enabled (Default) PWDN tied to 3.3V_REG:
All devices disabled.
PWDN floating: Tie PCIe system PRSNT signal to PWDN using J6 for the PWDN
control (optional for PCIe use case)
J5 3x1 Header
Access point to the WP (write protect) pin of the onboard EEPROM devices WP
tied to GND: I2C Access to the EEPROM enabled WP floating: I2C Access to the
EEPROM disabled (default)
J6 2x1 Header Alternative PWDN Control PWDN floating: Use J3 for the PWDN control PWDN
tied to PRSNT: PRSNT signal controls PWDN (optional for PCIe use case)
J7, J8, J9, J10 3x1 Headers
PCIe PRSNT Signal Controls Tie pins 1-2 on J7, J8, J9, and J10: Allow support
any PCIe bus width (default) Tie pins 2-3 of J7, leave J8, J9, and J10 floating:
Force x1 PCIe bus width Tie pins 2-3 of J8, leave J7, J9, and J10 floating: Force x4
PCIe bus width Tie pins 2-3 of J9, leave J7, J8, and J10 floating: Force x8 PCIe
bus width Tie pins 2-3 of J10, leave J7, J8, and J9 floating: Force x16 PCIe bus
width
J11 2x1 Header
Onboard regulator input. Apply 12 V when using the EVM as a standalone system.
DO NOT APPLY power if plugging the EVM into a system as the power is provided
through the gold finger connector (CONN1).
J12 2x1 Header Access point to the GND reference
J13 2x1 Header Onboard 3.3-V output
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2.8 DS160PR810EVM Downstream Devices Control
Table 2-8 shows the DS160PR810EVM downstream device controls that affect DS1 and DS2 devices on the
board.
Table 2-8. EVM Downstream Devices Controls
COMPONENT NAME FUNCTION / DESCRIPTION
J14 3x2 Header
Gain Controls tied to GAIN pins of all downstream device banks
L0: –6 dB Gain Setting
L1: –3 dB Gain Setting
L2: 3 dB Gain Setting
L3: 0 dB Gain Setting (default)
J15 12x2 Header
Pin Mode: EQ1 controls for each downstream device and device bank.
Use pins 1–6 for configuring EQ1_0 pin of Bank 0 of DS1 device.
Use pins 7–12 for configuring EQ1_1 pin of Bank 1 of DS1 device.
Use pins 13–18 for configuring EQ1_0 pin of Bank 0 of DS2 device.
Use pins 19–24 for configuring EQ1_1 pin of Bank 1 of DS2 device.
SMBus, I2C Modes: ADDR1 controls for each downstream device.
Use pins 1–6 for configuring ADDR1 pin of DS1 device.
Use pins 13–18 for configuring ADDR1 pin of DS2 device.
Install a shunt to achieve L0, L1, or L2 level on the pin. Leave floating to achieve
L3 level on the pin.
J16 12x2 Header
Pin Mode: EQ0 controls for each downstream device and device bank.
Use pins 1–6 for configuring EQ0_0 pin of Bank 0 of DS1 device.
Use pins 7–12 for configuring EQ0_1 pin of Bank 1 of DS1 device.
Use pins 13–18 for configuring EQ0_0 pin of Bank 0 of DS2 device.
Use pins 19–24 for configuring EQ0_1 pin of Bank 1 of DS2 device.
SMBus, I2C Modes: ADDR0 controls for each downstream device.
Use pins 1–6 for configuring ADDR0 pin of DS1 device.
Use pins 13–18 for configuring ADDR0 pin of DS2 device.
Install a shunt to achieve L0, L1, or L2 level on the pin. Leave floating to achieve
L3 level on the pin.
J17 3x1 Header
GAIN / SDA Dual Function Pin Provision for DS1 Device Install shunt across pins
1-2 for operation in Pin Mode (default) Install shunt across pins 2-3 for operation in
SMBus, I2C Modes
J18 3x1 Header
RX DET / SCL Dual Function Pin Provision for DS1 Device Install shunt across
pins 1-2 for operation in Pin Mode (default) Install shunt across pins 2-3 for
operation in SMBus, I2C Modes
J19 3x1 Header
GAIN / SDA Dual Function Pin Provision for DS2 Device Install shunt across pins
1-2 for operation in Pin Mode (default) Install shunt across pins 2-3 for operation in
SMBus, I2C Modes
J20 3x1 Header RX DET / SCL Dual Function Pin Provision for DS2 Device Install shunt across
pins 1-2 for operation in Pin Mode (default) Install shunt across pins 2-3 for
operation in SMBus, I2C Modes
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2.9 DS160PR810EVM Upstream Devices Control
Table 2-9 shows DS160PR810EVM upstream devices controls that affect US1-US2 devices on the board.
Table 2-9. EVM Upstream Devices Controls
COMPONENT NAME FUNCTION / DESCRIPTION
J21 3x2 Header Gain Controls tied to GAIN pins of all upstream device banks L0: -6 dB Gain
Setting L1: -3 dB Gain Setting L2: 3 dB Gain Setting L3: 0 dB Gain Setting (default)
J22 12x2
Pin Mode: EQ1 controls for each upstream device and device bank.
Use pins 1–6 for configuring EQ1_0 pin of Bank 0 of US1 device.
Use pins 7–12 for configuring EQ1_1 pin of Bank 1 of US1 device.
Use pins 13–18 for configuring EQ1_0 pin of Bank 0 of US2 device.
Use pins 19–24 for configuring EQ1_1 pin of Bank 1 of US2 device.
SMBus, I2C Modes: ADDR1 controls for each upstream device.
Use pins 1–6 for configuring ADDR1 pin of US1 device.
Use pins 13–18 for configuring ADDR1 pin of US2 device.
Install a shunt to achieve L0, L1, or L2 level on the pin. Leave floating to achieve
L3 level on the pin.
J23 12x2 Header
Pin Mode: EQ0 controls for each upstream device and device bank.
Use pins 1–6 for configuring EQ0_0 pin of Bank 0 of US1 device.
Use pins 7–12 for configuring EQ0_1 pin of Bank 1 of US1 device.
Use pins 13–18 for configuring EQ0_0 pin of Bank 0 of US2 device.
Use pins 19–24 for configuring EQ0_1 pin of Bank 1 of US2 device.
SMBus, I2C Modes: ADDR0 controls for each upstream device.
Use pins 1–6 for configuring ADDR0 pin of US1 device.
Use pins 13–18 for configuring ADDR0 pin of US2 device.
Install a shunt to achieve L0, L1, or L2 level on the pin. Leave floating to achieve
L3 level on the pin.
J24 3x1 Header
GAIN / SDA Dual Function Pin Provision for US1 Device Install shunt across pins
1-2 for operation in Pin Mode (default) Install shunt across pins 2-3 for operation in
SMBus, I2C Modes
J25 3x1 Header
RX DET / SCL Dual Function Pin Provision for US1 Device Install shunt across
pins 1-2 for operation in Pin Mode (default) Install shunt across pins 2-3 for
operation in SMBus, I2C Modes
J26 3x1 Header
GAIN / SDA Dual Function Pin Provision for US2 Device Install shunt across pins
1-2 for operation in Pin Mode (default) Install shunt across pins 2-3 for operation in
SMBus, I2C Modes
J27 3x1 Header RX DET / SCL Dual Function Pin Provision for US2 Device Install shunt across
pins 1-2 for operation in Pin Mode (default) Install shunt across pins 2-3 for
operation in SMBus, I2C Modes
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2.10 Quick-Start Guide (Pin Mode)
Check that the shunts are at the following positions as shown in Figure 1-1:
1. The redrivers are configured to operate in Pin Mode (MODE pins tied to L0 using J1 header).
2. RX_Detect state machine of all redrivers is enabled by leaving J2 open.
3. The redrivers are enabled (PWDN pins tied to GND using J4 header). Alternatevely, for PCIe applications,
the PWDN pins may be driven by PCIe Present (PRSNT) signal by leaving J4 open and placing a shunt
across pins 1 and 2 of J6.
4. The board is configured for any PCIe bus width (PRSNT signal controls set as shown in Figure 1-1 using J7,
J8, J9 and J10 headers).
5. DC Gain of all redrivers is set to 0 dB by leaving J14 open for the downstream redrivers and by leaving J21
open for the upstream redrivers.
6. EQ level of the RX CTLEs of all redrivers is set to 8.4 dB at 8 GHz by using J15 and J16 for the downstream
redrivers and J22 and J23 for the upstream redrivers.
7. If necessary, adjust EQ levels of the downstream redrivers, or upstream redrivers, or both, by arranging
shunts on J15 and J16 for downstream redrivers and J22 and J23 for the upstream redrivers.
8. Plug the EVM into a PCIe x16 server motherboard slot. Ensure the motherboard is powered down before
installing the EVM or configured for hot-plug operation.
9. Install a compatible PCIe endpoint card into the straddle connector of the EVM.
10.Power-up the motherboard.
2.11 Quick-Start Guide (SMBus Slave Mode)
1. Configure all devices to operate in the SMBus Slave Mode by setting their MODE pins to the L2 level. This is
accomplished by placing a shunt on J1 L2 location.
2. Set a unique SMBus Slave address for each device by placing shunts in the following arrangement:
• On J15 connector, place shunts in L0 locations for all downstream devices (DS1_0 and DS2_0; DS1_1
and DS2_1 are a Don't Care).
• On J16 connector, place shunts in L0 locations for the DS1_0 and in L1 locations for DS2_0 (DS1_1 and
DS2_1 are a Don't Care).
• On J22 connector, place shunts in L0 locations for all upstream devices (US1_0 and US2_0; DS1_1 and
DS2_1 are a Don't Care).
• On J23 connector, place a shunt in L2 location for the US1_0 and remove shunts for US2_0 to achieve L3
level (US1_1 and US2_1 are a Don't Care).
3. Move shunts from pins 1-2 to pins 2-3 on J17, J18, J19, J20, J24, J25, J26, and J27 to connect the dual
function redriver pins to the SMBus, I2C bus.
4. Enable all devices by pulling their PWDN pins to GND. This is accomplished by placing a shunt on J4
between PWDN and GND.
5. Connect the USB2ANY Adapter to J3 (Note that the USB2ANY Adapter is not supplied with the
DS160PR810EVM-RSC).
6. Install SigCon Architect Version 3.0.0.14 application and the DS160PR810 profile.
7. Plug the EVM into a PCIe x16 server motherboard slot. Ensure the motherboard is powered down before
installing the EVM or configured for hot-plug operation.
8. Install a compatible PCIe endpoint card into the straddle connector of the EVM.
9. Power-up the motherboard.
10.Start the SigCon Architect application.
11.Select the DS160PR810 Configuration Page and click on "Apply" box to enable the device profile. If
necessary, edit devices addresses in the Edit Device Addresses box.
12.In the DS160PR810 High Level Page, select Block Diagram as shown in Figure 2-1.
13.Select the desired EQ Settings and Driver VOD.
14.Select devices to which you want to apply the selected settings and click "Apply to All Channels".
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