Texas Instruments MSP430F5638 Manuel utilisateur

MSP430F5638, MSP430F5637, MSP430F5636

MSP430F5635, MSP430F5634, MSP430F5633

MSP430F5632, MSP430F5631, MSP430F5630

www.ti.com

SLAS650D –JUNE 2010–REVISED AUGUST 2013

Mixed Signal Microcontroller

Check for

Samples: MSP430F5638,MSP430F5637,MSP430F5636,MSP430F5635,MSP430F5634,MSP430F5633,MSP430F5632,MSP430F5631,

MSP430F5630

1FEATURES

23• Low Supply Voltage Range: 1.8 V to 3.6 V • Four 16-Bit Timers With 3, 5, or 7

Capture/Compare Registers

• Ultralow-Power Consumption • Two Universal Serial Communication

– Active Mode (AM): Interfaces

All System Clocks Active:

270 µA/MHz at 8 MHz, 3.0 V, Flash Program – USCI_A0 and USCI_A1 Each Support:

Execution (Typical) – Enhanced UART Supports Auto-

– Standby Mode (LPM3): Baudrate Detection

Watchdog With Crystal and Supply – IrDA Encoder and Decoder

Supervisor Operational, Full RAM – Synchronous SPI

Retention, Fast Wake-Up: – USCI_B0 and USCI_B1 Each Support:

1.8 µA at 2.2 V, 2.1 µA at 3.0 V (Typical) – I2C

– Shutdown RTC Mode (LPM3.5): – Synchronous SPI

Shutdown Mode, Active Real-Time Clock

With Crystal: • Full-Speed Universal Serial Bus (USB)

1.1 µA at 3.0 V (Typical) – Integrated USB-PHY

– Shutdown Mode (LPM4.5): – Integrated 3.3-V and 1.8-V USB Power

0.3 µA at 3.0 V (Typical) System

• Wake Up From Standby Mode in 3 µs (Typical) – Integrated USB-PLL

• 16-Bit RISC Architecture, Extended Memory, – Eight Input and Eight Output Endpoints

Up to 20-MHz System Clock • 12-Bit Analog-to-Digital Converter (ADC) With

• Flexible Power Management System Internal Shared Reference, Sample-and-Hold,

– Fully Integrated LDO With Programmable and Autoscan Feature

Regulated Core Supply Voltage • Dual 12-Bit Digital-to-Analog Converters

– Supply Voltage Supervision, Monitoring, (DACs) With Synchronization

and Brownout • Voltage Comparator

• Unified Clock System • Hardware Multiplier Supporting 32-Bit

– FLL Control Loop for Frequency Operations

Stabilization • Serial Onboard Programming, No External

– Low-Power Low-Frequency Internal Clock Programming Voltage Needed

Source (VLO) • Six-Channel Internal DMA

– Low-Frequency Trimmed Internal Reference • Real-Time Clock Module With Supply Voltage

Source (REFO) Backup Switch

– 32-kHz Crystals (XT1) • Family Members are Summarized in Table 1

– High-Frequency Crystals Up to 32 MHz • For Complete Module Descriptions, See the

(XT2) MSP430x5xx and MSP430x6xx Family User's

Guide (SLAU208)

1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2MSP430, Code Composer Studio are trademarks of Texas Instruments.

3All other trademarks are the property of their respective owners.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

MSP430F5638, MSP430F5637, MSP430F5636

MSP430F5635, MSP430F5634, MSP430F5633

MSP430F5632, MSP430F5631, MSP430F5630

SLAS650D –JUNE 2010–REVISED AUGUST 2013

www.ti.com

APPLICATIONS

• Analog and Digital Sensor Systems

• Digital Motor Control

• Remote Controls

• Thermostats

• Digital Timers

• Hand-Held Meters

DESCRIPTION

The Texas Instruments MSP430™ family of ultralow-power microcontrollers consists of several devices featuring

different sets of peripherals targeted for various applications. The architecture, combined with five low-power

modes, is optimized to achieve extended battery life in portable measurement applications. The device features a

powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency.

The digitally controlled oscillator (DCO) allows the device to wake up from low-power modes to active mode in

3 µs (typical).

The MSP430F563x series are microcontroller configurations with a high-performance 12-bit analog-to-digital

converter (ADC), comparator, two universal serial communication interfaces (USCIs), USB 2.0, a hardware

multiplier, DMA, four 16-bit timers, a real-time clock module with alarm capabilities, and up to 74 I/O pins.

Typical applications for this device include analog and digital sensor systems, digital motor control, remote

controls, thermostats, digital timers, and hand-held meters.

Table 1 summarizes the available family members.

Table 1. Family Members(1)(2)

USCI

Flash SRAM ADC12_A DAC12_A Comp_B Package

Channel A: Channel B:

Device Timer_A(4) Timer_B(5) I/O

(KB) (KB)(3) (Ch) (Ch) (Ch) Type

UART, SPI, I2C

IrDA, SPI

12 ext, 100 PZ,

MSP430F5638 256 16 + 2 5, 3, 3 7 2 2 2 12 74

4 int 113 ZQW

12 ext, 100 PZ,

MSP430F5637 192 16 + 2 5, 3, 3 7 2 2 2 12 74

4 int 113 ZQW

12 ext, 100 PZ,

MSP430F5636 128 16 + 2 5, 3, 3 7 2 2 2 12 74

4 int 113 ZQW

12 ext, 100 PZ,

MSP430F5635 256 16 + 2 5, 3, 3 7 2 2 - 12 74

4 int 113 ZQW

12 ext, 100 PZ,

MSP430F5634 192 16 + 2 5, 3, 3 7 2 2 - 12 74

4 int 113 ZQW

12 ext, 100 PZ,

MSP430F5633 128 16 + 2 5, 3, 3 7 2 2 - 12 74

4 int 113 ZQW

100 PZ,

MSP430F5632 256 16 + 2 5, 3, 3 7 2 2 - - 12 74 113 ZQW

100 PZ,

MSP430F5631 192 16 + 2 5, 3, 3 7 2 2 - - 12 74 113 ZQW

100 PZ,

MSP430F5630 128 16 + 2 5, 3, 3 7 2 2 - - 12 74 113 ZQW

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

web site at http://www.ti.com.

(2) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at

http://www.ti.com/packaging.

(3) The additional 2 KB USB SRAM that is listed can be used as general purpose SRAM when USB is not in use.

(4) Each number in the sequence represents an instantiation of Timer_A with its associated number of capture compare registers and PWM

output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_A, the first

instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output generators, respectively.

(5) Each number in the sequence represents an instantiation of Timer_B with its associated number of capture compare registers and PWM

output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_B, the first

instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output generators, respectively.

Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634 MSP430F5633

MSP430F5632 MSP430F5631 MSP430F5630

Unified

Clock

System

256KB

192KB

128KB

Flash

16KB

RAM

+2KB RAM

USB Buffer

+8B Backup

RAM

MCLK

ACLK

SMCLK

I/O Ports

P1/P2

2×8 I/Os

Interrupt

Capability

1×16 I/Os

CPUXV2

and

Working

Registers

EEM

(L: 8+2)

XIN XOUT

JTAG/

Interface/

Port PJ

SBW

PA PB PC PD

DMA

6 Channel

XT2IN

XT OUT2

Power

Management

LDO

SVM/

Brownout

SVS

SYS

Watchdog

P2 Port

Mapping

Controller

I/O Ports

P3/P4

2×8 I/Os

Interrupt

Capability

1×16 I/Os

I/O Ports

P5/P6

2×8 I/Os

1×16 I/Os

I/O Ports

P7/P8

1×6 I/Os

1×14 I/Os

1×8 I/Os

I/O Ports

1×8 I/Os

MPY32

TA0

Timer_A

5 CC

Registers

TA1 and

TA2

2 Timer_A

each with

3 CC

Registers

TB0

Timer_B

7 CC

Registers

CRC16

USCI0,1

Ax: UART,

IrDA, SPI

Bx: SPI, I2C

ADC12_A

200 KSPS

16 Channels

(12 ext/4 int)

Autoscan

12 Bit

DVCC DVSS AVCC AVSS

P1.x P2.x P3.x P4.x P5.x P6.x P7.x P8.x P9.x

RST/NMI

REF

Reference

1.5V, 2.0V,

2.5V

USB

Full-speed

Comp_B

PJ.x

RTC_B

Battery

Backup

System

Unified

Clock

System

256KB

192KB

128KB

Flash

MCLK

ACLK

SMCLK

I/O Ports

P1/P2

2×8 I/Os

Interrupt

Capability

1×16 I/Os

CPUXV2

and

Working

Registers

EEM

(L: 8+2)

XIN XOUT

JTAG/

Interface/

Port PJ

SBW

PA PB PC PD

DMA

6 Channel

XT2IN

XT OUT2

Power

Management

LDO

SVM/

Brownout

SVS

SYS

Watchdog

P2 Port

Mapping

Controller

I/O Ports

P3/P4

2×8 I/Os

Interrupt

Capability

1×16 I/Os

I/O Ports

P5/P6

2×8 I/Os

1×16 I/Os

I/O Ports

P7/P8

1×6 I/Os

1×14 I/Os

1×8 I/Os

I/O Ports

1×8 I/Os

MPY32

TA0

Timer_A

5 CC

Registers

TA1 and

TA2

2 Timer_A

each with

3 CC

Registers

TB0

Timer_B

7 CC

Registers

RTC_B

Battery

Backup

System

CRC16

USCI0,1

Ax: UART,

IrDA, SPI

Bx: SPI, I2C

ADC12_A

200 KSPS

16 Channels

(12 ext/4 int)

Autoscan

12 Bit

DVCC DVSS AVCC AVSS

P1.x P2.x P3.x P4.x P5.x P6.x P7.x P8.x P9.x

RST/NMI

REF

Reference

1.5V, 2.0V,

2.5V

DAC12_A

12 bit

2 channels

voltage out

USB

Full-speed

Comp_B

PJ.x

16KB

RAM

+2KB RAM

USB Buffer

+8B Backup

RAM

MSP430F5638, MSP430F5637, MSP430F5636

MSP430F5635, MSP430F5634, MSP430F5633

MSP430F5632, MSP430F5631, MSP430F5630

www.ti.com

SLAS650D –JUNE 2010–REVISED AUGUST 2013

Functional Block Diagram, MSP430F5638, MSP430F5637, MSP430F5636

Functional Block Diagram, MSP430F5635, MSP430F5634, MSP430F5633

Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634 MSP430F5633

MSP430F5632 MSP430F5631 MSP430F5630

Unified

Clock

System

256KB

192KB

128KB

Flash

MCLK

ACLK

SMCLK

I/O Ports

P1/P2

2×8 I/Os

Interrupt

Capability

1×16 I/Os

CPUXV2

and

Working

Registers

EEM

(L: 8+2)

XIN XOUT

JTAG/

Interface/

Port PJ

SBW

PA PB PC PD

DMA

6 Channel

XT2IN

XT OUT2

Power

Management

LDO

SVM/

Brownout

SVS

SYS

Watchdog

P2 Port

Mapping

Controller

I/O Ports

P3/P4

2×8 I/Os

Interrupt

Capability

1×16 I/Os

I/O Ports

P5/P6

2×8 I/Os

1×16 I/Os

I/O Ports

P7/P8

1×6 I/Os

1×14 I/Os

1×8 I/Os

I/O Ports

1×8 I/Os

MPY32

TA0

Timer_A

5 CC

Registers

TA1 and

TA2

2 Timer_A

each with

3 CC

Registers

TB0

Timer_B

7 CC

Registers

CRC16

USCI0,1

Ax: UART,

IrDA, SPI

Bx: SPI, I2C

DVCC DVSS AVCC AVSS

P1.x P2.x P3.x P4.x P5.x P6.x P7.x P8.x P9.x

RST/NMI

REF

Reference

1.5V, 2.0V,

2.5V

USB

Full-speed

Comp_B

PJ.x

RTC_B

Battery

Backup

System

16KB

RAM

+2KB RAM

USB Buffer

+8B Backup

RAM

MSP430F5638, MSP430F5637, MSP430F5636

MSP430F5635, MSP430F5634, MSP430F5633

MSP430F5632, MSP430F5631, MSP430F5630

SLAS650D –JUNE 2010–REVISED AUGUST 2013

www.ti.com

Functional Block Diagram, MSP430F5632, MSP430F5631, MSP430F5630

Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634 MSP430F5633

MSP430F5632 MSP430F5631 MSP430F5630

100

P6.4/CB4/A4

P6.5/CB5/A5

P6.6/CB6/A6/DAC0

P6.7/CB7/A7/DAC1

P7.4/CB8/A12

P7.5/CB9/A13

P7.6/CB10/A14/DAC0

P7.7/CB11/A15/DAC1

P5.0/VREF+/VeREF+

P5.1/VREF−/VeREF−

AVCC1

AVSS1

XIN

XOUT

DVCC1

DVSS1

VCORE

P5.2

DVSS

DNC

P5.3

P9.7

P9.6

P9.5

P9.4

P9.3

P9.2

P9.1

P9.0

P8.7

P8.6/UCB1SOMI/UCB1SCL

P8.5/UCB1SIMO/UCB1SDA

DVCC2

DVSS2

P2.0/P2MAP0

MSP430F5638

MSP430F5637

MSP430F5636

PZ PACKAGE

(TOP VIEW)

P6.3/CB3/A3

P6.2/CB2/A2

P6.1/CB1/A1

P6.0/CB0/A0

RST/NMI/SBWTDIO

PJ.3/TCK

PJ.2/TMS

PJ.1/TDI/TCLK

PJ.0/TDO

TEST/SBWTCK

P7.3/XT2OUT

P7.2/XT2IN

VBUS

VUSB

PU.1/DM

PUR

PU.0/DP

VSSU

V18

AVSS3

P1.3/TA0.2

P1.4/TA0.3

AVSS2

P5.6/ADC12CLK/DMAE0

P5.4

P5.5

P1.0/TA0CLK/ACLK

P3.0/TA1CLK/CBOUT

P3.1/TA1.0

P3.2/TA1.1

P1.6/TA0.1

P1.7/TA0.2

P1.1/TA0.0

P1.2/TA0.1

P1.5/TA0.4

P3.3/TA1.2

P3.4/TA2CLK/SMCLK

P3.5/TA2.0

P3.6/TA2.1

P3.7/TA2.2

P4.0/TB0.0

P4.2/TB0.2

P4.1/TB0.1

P4.4/TB0.4

P4.3/TB0.3

P4.6/TB0.6

P4.5/TB0.5

P8.0/TB0CLK

P4.7/TB0OUTH/SVMOUT

P8.4/UCB1CLK/UCA1STE

VBAK

P2.1/P2MAP1

P2.2/P2MAP2

P2.3/P2MAP3

P2.4/P2MAP4

P2.5/P2MAP5

P2.6/P2MAP6

P2.7/P2MAP7

DVCC3

DVSS3

VBAT

P5.7/RTCCLK

P8.1/UCB1STE/UCA1CLK

P8.2/UCA1TXD/UCA1SIMO

P8.3/UCA1RXD/UCA1SOMI

MSP430F5638, MSP430F5637, MSP430F5636

MSP430F5635, MSP430F5634, MSP430F5633

MSP430F5632, MSP430F5631, MSP430F5630

www.ti.com

SLAS650D –JUNE 2010–REVISED AUGUST 2013

Pin Designation, MSP430F5638IPZ, MSP430F5637IPZ, MSP430F5636IPZ

NOTE: DNC = Do not connect

Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634 MSP430F5633

MSP430F5632 MSP430F5631 MSP430F5630

100

P6.4/CB4/A4

P6.5/CB5/A5

P6.6/CB6/A6

P6.7/CB7/A7

P7.4/CB8/A12

P7.5/CB9/A13

P7.6/CB10/A14

P7.7/CB11/A15

P5.0/VREF+/VeREF+

P5.1/VREF−/VeREF−

AVCC1

AVSS1

XIN

XOUT

DVCC1

DVSS1

VCORE

P5.2

DVSS

DNC

P5.3

P9.7

P9.6

P9.5

P9.4

P9.3

P9.2

P9.1

P9.0

P8.7

P8.6/UCB1SOMI/UCB1SCL

P8.5/UCB1SIMO/UCB1SDA

DVCC2

DVSS2

P2.0/P2MAP0

MSP430F5635

MSP430F5634

MSP430F5633

PZ PACKAGE

(TOP VIEW)

P6.3/CB3/A3

P6.2/CB2/A2

P6.1/CB1/A1

P6.0/CB0/A0

RST/NMI/SBWTDIO

PJ.3/TCK

PJ.2/TMS

PJ.1/TDI/TCLK

PJ.0/TDO

TEST/SBWTCK

P7.3/XT2OUT

P7.2/XT2IN

VBUS

VUSB

PU.1/DM

PUR

PU.0/DP

VSSU

V18

AVSS3

P1.3/TA0.2

P1.4/TA0.3

AVSS2

P5.6/ADC12CLK/DMAE0

P5.4

P5.5

P1.0/TA0CLK/ACLK

P3.0/TA1CLK/CBOUT

P3.1/TA1.0

P3.2/TA1.1

P1.6/TA0.1

P1.7/TA0.2

P1.1/TA0.0

P1.2/TA0.1

P1.5/TA0.4

P3.3/TA1.2

P3.4/TA2CLK/SMCLK

P3.5/TA2.0

P3.6/TA2.1

P3.7/TA2.2

P4.0/TB0.0

P4.2/TB0.2

P4.1/TB0.1

P4.4/TB0.4

P4.3/TB0.3

P4.6/TB0.6

P4.5/TB0.5

P8.0/TB0CLK

P4.7/TB0OUTH/SVMOUT

P8.4/UCB1CLK/UCA1STE

VBAK

P2.1/P2MAP1

P2.2/P2MAP2

P2.3/P2MAP3

P2.4/P2MAP4

P2.5/P2MAP5

P2.6/P2MAP6

P2.7/P2MAP7

DVCC3

DVSS3

VBAT

P5.7/RTCCLK

P8.1/UCB1STE/UCA1CLK

P8.2/UCA1TXD/UCA1SIMO

P8.3/UCA1RXD/UCA1SOMI

MSP430F5638, MSP430F5637, MSP430F5636

MSP430F5635, MSP430F5634, MSP430F5633

MSP430F5632, MSP430F5631, MSP430F5630

SLAS650D –JUNE 2010–REVISED AUGUST 2013

www.ti.com

Pin Designation, MSP430F5635IPZ, MSP430F5634IPZ, MSP430F5633IPZ

NOTE: DNC = Do not connect

Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634 MSP430F5633

MSP430F5632 MSP430F5631 MSP430F5630

100

P6.4/CB4

P6.5/CB5

P6.6/CB6

P6.7/CB7

P7.4/CB8

P7.5/CB9

P7.6/CB10

P7.7/CB11

P5.0/VREF+/VeREF+

P5.1/VREF−/VeREF−

AVCC1

AVSS1

XIN

XOUT

DVCC1

DVSS1

VCORE

P5.2

DVSS

DNC

P5.3

P9.7

P9.6

P9.5

P9.4

P9.3

P9.2

P9.1

P9.0

P8.7

P8.6/UCB1SOMI/UCB1SCL

P8.5/UCB1SIMO/UCB1SDA

DVCC2

DVSS2

P2.0/P2MAP0

MSP430F5632

MSP430F5631

MSP430F5630

PZ PACKAGE

(TOP VIEW)

P6.3/CB3

P6.2/CB2

P6.1/CB1

P6.0/CB0

RST/NMI/SBWTDIO

PJ.3/TCK

PJ.2/TMS

PJ.1/TDI/TCLK

PJ.0/TDO

TEST/SBWTCK

P7.3/XT2OUT

P7.2/XT2IN

VBUS

VUSB

PU.1/DM

PUR

PU.0/DP

VSSU

V18

AVSS3

P1.3/TA0.2

P1.4/TA0.3

AVSS2

P5.6/DMAE0

P5.4

P5.5

P1.0/TA0CLK/ACLK

P3.0/TA1CLK/CBOUT

P3.1/TA1.0

P3.2/TA1.1

P1.6/TA0.1

P1.7/TA0.2

P1.1/TA0.0

P1.2/TA0.1

P1.5/TA0.4

P3.3/TA1.2

P3.4/TA2CLK/SMCLK

P3.5/TA2.0

P3.6/TA2.1

P3.7/TA2.2

P4.0/TB0.0

P4.2/TB0.2

P4.1/TB0.1

P4.4/TB0.4

P4.3/TB0.3

P4.6/TB0.6

P4.5/TB0.5

P8.0/TB0CLK

P4.7/TB0OUTH/SVMOUT

P8.4/UCB1CLK/UCA1STE

VBAK

P2.1/P2MAP1

P2.2/P2MAP2

P2.3/P2MAP3

P2.4/P2MAP4

P2.5/P2MAP5

P2.6/P2MAP6

P2.7/P2MAP7

DVCC3

DVSS3

VBAT

P5.7/RTCCLK

P8.1/UCB1STE/UCA1CLK

P8.2/UCA1TXD/UCA1SIMO

P8.3/UCA1RXD/UCA1SOMI

MSP430F5638, MSP430F5637, MSP430F5636

MSP430F5635, MSP430F5634, MSP430F5633

MSP430F5632, MSP430F5631, MSP430F5630

www.ti.com

SLAS650D –JUNE 2010–REVISED AUGUST 2013

Pin Designation, MSP430F5632IPZ, MSP430F5631IPZ, MSP430F5630IPZ

NOTE: DNC = Do not connect

Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634 MSP430F5633

MSP430F5632 MSP430F5631 MSP430F5630

A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12

B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12

C1 C2 C3 C11 C12

D1 D2 D4 D5 D6 D7 D8 D9 D11 D12

E1 E2 E4 E5 E6 E7 E8 E9 E11 E12

F1 F2 F4 F5 F8 F9 F11 F12

G1 G2 G4 G5 G8 G9 G11 G12

J1 J2 J4 J5 J6 J7 J8 J9 J11 J12

H1 H2 H4 H5 H6 H7 H8 H9 H11 H12

K1 K2 K11 K12

L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12

M1 M2 M3 M5 M6 M7 M8 M9 M10 M11 M12

ZQW PACKAGE

(TOP VIEW)

MSP430F5638, MSP430F5637, MSP430F5636

MSP430F5635, MSP430F5634, MSP430F5633

MSP430F5632, MSP430F5631, MSP430F5630

SLAS650D –JUNE 2010–REVISED AUGUST 2013

www.ti.com

Pin Designation, MSP430F5638IZQW, MSP430F5637IZQW, MSP430F5636IZQW,

MSP430F5635IZQW, MSP430F5634IZQW, MSP430F5633IZQW, MSP430F5632IZQW,

MSP430F5631IZQW, MSP430F5630IZQW

NOTE: For terminal assignments, see Table 2

Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634 MSP430F5633

MSP430F5632 MSP430F5631 MSP430F5630

MSP430F5638, MSP430F5637, MSP430F5636

MSP430F5635, MSP430F5634, MSP430F5633

MSP430F5632, MSP430F5631, MSP430F5630

www.ti.com

SLAS650D –JUNE 2010–REVISED AUGUST 2013

Table 2. Terminal Functions

TERMINAL

NO. I/O(1) DESCRIPTION

NAME PZ ZQW

General-purpose digital I/O

P6.4/CB4/A4 1 A1 I/O Comparator_B input CB4

Analog input A4 – ADC(not available on F5632, F5631, F5630 devices)

General-purpose digital I/O

P6.5/CB5/A5 2 B2 I/O Comparator_B input CB5

Analog input A5 – ADC(not available on F5632, F5631, F5630 devices)

General-purpose digital I/O

Comparator_B input CB6

P6.6/CB6/A6/DAC0 3 B1 I/O Analog input A6 – ADC (not available on F5632, F5631, F5630 devices)

DAC12.0 output (not available on F5635, F5634, F5633, F5632, F5631, F5630

devices)

General-purpose digital I/O

Comparator_B input CB7

P6.7/CB7/A7/DAC1 4 C2 I/O Analog input A7 – ADC (not available on F5632, F5631, F5630 devices)

DAC12.1 output (not available on F5635, F5634, F5633, F5632, F5631, F5630

devices)

General-purpose digital I/O

P7.4/CB8/A12 5 C1 I/O Comparator_B input CB8

Analog input A12 –ADC (not available on F5632, F5631, F5630 devices)

General-purpose digital I/O

P7.5/CB9/A13 6 C3 I/O Comparator_B input CB9

Analog input A13 – ADC (not available on F5632, F5631, F5630 devices)

General-purpose digital I/O

Comparator_B input CB10

P7.6/CB10/A14/DAC0 7 D2 I/O Analog input A14 – ADC (not available on F5632, F5631, F5630 devices)

DAC12.0 output (not available on F5635, F5634, F5633, F5632, F5631, F5630

devices)

General-purpose digital I/O

Comparator_B input CB11

P7.7/CB11/A15/DAC1 8 D1 I/O Analog input A15 – ADC (not available on F5632, F5631, F5630 devices)

DAC12.1 output (not available on F5635, F5634, F5633, F5632, F5631, F5630

devices)

General-purpose digital I/O

P5.0/VREF+/VeREF+ 9 D4 I/O Output of reference voltage to the ADC

Input for an external reference voltage to the ADC

General-purpose digital I/O

P5.1/VREF-/VeREF- 10 E4 I/O Negative terminal for the ADC's reference voltage for both sources, the internal

reference voltage, or an external applied reference voltage

E1,

AVCC1 11 Analog power supply

AVSS1 12 F2 Analog ground supply

XIN 13 F1 I Input terminal for crystal oscillator XT1

XOUT 14 G1 O Output terminal of crystal oscillator XT1

AVSS2 15 G2 Analog ground supply

(1) I = input, O = output, N/A = not available on this package offering

Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634 MSP430F5633

MSP430F5632 MSP430F5631 MSP430F5630

MSP430F5638, MSP430F5637, MSP430F5636

MSP430F5635, MSP430F5634, MSP430F5633

MSP430F5632, MSP430F5631, MSP430F5630

SLAS650D –JUNE 2010–REVISED AUGUST 2013

www.ti.com

Table 2. Terminal Functions (continued)

TERMINAL

NO. I/O(1) DESCRIPTION

NAME PZ ZQW

General-purpose digital I/O

P5.6/ADC12CLK/DMAE0 16 H1 I/O Conversion clock output ADC (not available on F5632, F5631, F5630 devices)

DMA external trigger input

General-purpose digital I/O with port interrupt and mappable secondary function

P2.0/P2MAP0 17 G4 I/O Default mapping: USCI_B0 SPI slave transmit enable; USCI_A0 clock input/output

General-purpose digital I/O with port interrupt and mappable secondary function

P2.1/P2MAP1 18 H2 I/O Default mapping: USCI_B0 SPI slave in/master out; USCI_B0 I2C data

General-purpose digital I/O with port interrupt and mappable secondary function

P2.2/P2MAP2 19 J1 I/O Default mapping: USCI_B0 SPI slave out/master in; USCI_B0 I2C clock

General-purpose digital I/O with port interrupt and mappable secondary function

P2.3/P2MAP3 20 H4 I/O Default mapping: USCI_B0 clock input/output; USCI_A0 SPI slave transmit enable

General-purpose digital I/O with port interrupt and mappable secondary function

P2.4/P2MAP4 21 J2 I/O Default mapping: USCI_A0 UART transmit data; USCI_A0 SPI slave in/master out

General-purpose digital I/O with port interrupt and mappable secondary function

P2.5/P2MAP5 22 K1 I/O Default mapping: USCI_A0 UART receive data; USCI_A0 slave out/master in

General-purpose digital I/O with port interrupt and mappable secondary function

P2.6/P2MAP6 23 K2 I/O Default mapping: no secondary function

General-purpose digital I/O with port interrupt and mappable secondary function

P2.7/P2MAP7 24 L2 I/O Default mapping: no secondary function

DVCC1 25 L1 Digital power supply

DVSS1 26 M1 Digital ground supply

VCORE(2) 27 M2 Regulated core power supply (internal use only, no external current loading)

P5.2 28 L3 I/O General-purpose digital I/O

DVSS 29 M3 Digital ground supply

DNC 30 J4 Do not connect. It is strongly recommended to leave this terminal open.

P5.3 31 L4 I/O General-purpose digital I/O

P5.4 32 M4 I/O General-purpose digital I/O

P5.5 33 J5 I/O General-purpose digital I/O

General-purpose digital I/O with port interrupt

P1.0/TA0CLK/ACLK 34 L5 I/O Timer TA0 clock signal TACLK input

ACLK output (divided by 1, 2, 4, 8, 16, or 32)

General-purpose digital I/O with port interrupt

P1.1/TA0.0 35 M5 I/O Timer TA0 CCR0 capture: CCI0A input, compare: Out0 output

BSL transmit output

General-purpose digital I/O with port interrupt

P1.2/TA0.1 36 J6 I/O Timer TA0 CCR1 capture: CCI1A input, compare: Out1 output

BSL receive input

General-purpose digital I/O with port interrupt

P1.3/TA0.2 37 H6 I/O Timer TA0 CCR2 capture: CCI2A input, compare: Out2 output

General-purpose digital I/O with port interrupt

P1.4/TA0.3 38 M6 I/O Timer TA0 CCR3 capture: CCI3A input compare: Out3 output

(2) VCORE is for internal use only. No external current loading is possible. VCORE should only be connected to the recommended

capacitor value, CVCORE.

Product Folder Links: MSP430F5638 MSP430F5637 MSP430F5636 MSP430F5635 MSP430F5634 MSP430F5633

MSP430F5632 MSP430F5631 MSP430F5630

Ce manuel convient aux modèles suivants

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