Texas Instruments TMS320C6000 DSP Manuel utilisateur

TMS320C6000 DSP Multichannel BufferedSerial Port (McBSP)

Reference Guide

Literature Number: SPRU580EDecember 2005

2 SPRU580E – December 2005

Contents
Preface ............................................................................................................................... 9
1 Multichannel Buffered Serial Port (McBSP) .................................................................. 111.1 Features ............................................................................................................ 12
2 McBSP Interface ....................................................................................................... 132.1 McBSP Interface .................................................................................................. 14
3 McBSP Overview ...................................................................................................... 173.1 Resetting the Serial Port: RRST, XRST, GRST, and RESET ............................................... 183.2 Determining Ready Status ....................................................................................... 193.2.1 Receive Ready Status: REVT, RINT, and RRDY .................................................... 193.2.2 Transmit Ready Status: XEVT, XINT, and XRDY ................................................... 193.3 CPU Interrupts: RINT, XINT ..................................................................................... 193.4 Frame and Clock Configuration ................................................................................. 20
4 Clocks, Frames, and Data .......................................................................................... 214.1 Frame and Clock Operation ..................................................................................... 224.2 Sample Rate Generator Clocking and Framing ............................................................... 234.3 Data Clock Generation ........................................................................................... 244.3.1 Input Clock Source Mode: CLKSM .................................................................... 244.3.2 Sample Rate Generator Data Bit Clock Rate: CLKGDV ............................................ 254.3.3 Bit Clock Polarity: CLKSP ............................................................................... 254.3.4 Bit Clock and Frame Synchronization ................................................................. 254.3.5 Digital Loopback Mode: DLB ........................................................................... 274.3.6 Receive Clock Selection: DLB, CLKRM ............................................................... 274.3.7 Transmit Clock Selection: CLKXM ..................................................................... 274.3.8 Stopping Clocks .......................................................................................... 274.4 Frame Sync Generation .......................................................................................... 284.4.1 Frame Period (FPER) and Frame Width (FWID) .................................................... 284.4.2 Receive Frame Sync Selection: DLB, FSRM, GSYNC ............................................. 294.4.3 Transmit Frame Sync Selection: FSXM, FSGM ..................................................... 304.4.4 Frame Detection for Initialization ....................................................................... 304.5 Data and Frames .................................................................................................. 304.5.1 Frame Synchronization Phases ........................................................................ 304.5.2 Frame Length: RFRLEN1/2, XFRLEN1/2 ............................................................. 314.5.3 Element Length: RWDLEN1/2, XWDLEN1/2 ......................................................... 314.5.4 Data Packing using Frame Length and Element Length ........................................... 324.5.5 Data Delay: RDATDLY, XDATDLY .................................................................... 334.5.6 Receive Data Justification and Sign Extension: RJUST ............................................ 344.5.7 32-Bit Bit Reversal: RWDREVRS, XWDREVRS ..................................................... 344.6 Clocking and Framing Examples ................................................................................ 354.6.1 Multiphase Frame Example: AC97 .................................................................... 354.6.2 Double-Rate ST-BUS Clock ............................................................................ 354.6.3 Single-Rate ST-BUS Clock ............................................................................. 374.6.4 Double-Rate Clock ....................................................................................... 38
5 McBSP Standard Operation ....................................................................................... 39
SPRU580E – December 2005 Contents 3

1 Receive Operation ................................................................................................ 405.2 Transmit Operation ................................................................................................ 415.3 Maximum Frame Frequency ..................................................................................... 415.4 Frame Synchronization Ignore................................................................................... 425.4.1 Frame Sync Ignore and Unexpected Frame Sync Pulses .......................................... 425.4.2 Data Packing using Frame Sync Ignore Bits ......................................................... 435.5 Serial Port Exception Conditions ................................................................................ 445.5.1 Receive Overrun: RFULL ............................................................................... 445.5.2 Unexpected Receive Frame Synchronization: RSYNCERR ....................................... 455.5.3 Transmit With Data Overwrite .......................................................................... 475.5.4 Transmit Empty: XEMPTY .............................................................................. 475.5.5 Unexpected Transmit Frame Synchronization: XSYNCERR ....................................... 48
µ-Law/A-Law Companding Hardware Operation ........................................................... 516.1 Companding Internal Data ....................................................................................... 526.2 Bit Ordering ........................................................................................................ 53
McBSP Initialization Procedure .................................................................................. 557.1 General Initialization Procedure ................................................................................. 567.2 Special Case: External Device is the Transmit Frame Master .............................................. 57
Multichannel Selection Operation ............................................................................... 618.1 Enabling Multichannel Selection ................................................................................ 628.2 Enabling and Masking of Channels in Normal Multichannel Selection Mode ............................. 628.3 Changing Element Selection ..................................................................................... 658.4 End-of-Subframe Interrupt ....................................................................................... 658.5 Enhanced Multichannel Selection Mode (C64x and C645x DSPs only) ................................... 658.6 DX Enabler: DXENA .............................................................................................. 67
SPI Protocol: CLKSTP ............................................................................................... 699.1 McBSP Operation as the SPI Master ........................................................................... 729.2 McBSP Operation as the SPI Slave ............................................................................ 729.3 McBSP Initialization for SPI Mode .............................................................................. 73
McBSP Pins as General-Purpose I/O ........................................................................... 75
Registers ................................................................................................................. 7711.1 Data Receive Register (DRR) ................................................................................... 8111.2 Data Transmit Register (DXR) ................................................................................... 8211.3 Serial Port Control Register (SPCR) ............................................................................ 8311.4 Receive Control Register (RCR) ................................................................................ 8611.5 Transmit Control Register (XCR) ................................................................................ 8811.6 Sample Rate Generator Register (SRGR) ..................................................................... 9011.7 Multichannel Control Register (MCR)........................................................................... 9111.8 Receive Channel Enable Register (RCER) .................................................................... 9311.9 Transmit Channel Enable Registers (XCER) .................................................................. 9411.10 Enhanced Receive Channel Enable Registers (RCERE0-3) ............................................... 9511.10.1 RCEREs Used in the Receive Multichannel Selection Mode ................................... 9611.11 Enhanced Transmit Channel Enable Registers (XCERE0-3) .............................................. 9811.11.1 XCEREs Used in a Transmit Multichannel Selection Mode ..................................... 9811.12 Pin Control Register (PCR) .................................................................................... 101
A Revision History ..................................................................................................... 103
Contents 4 SPRU580E – December 2005

List of Figures
2-1 McBSP Block Diagram .................................................................................................... 143-1 Frame and Clock Operation .............................................................................................. 204-1 Clock and Frame Generation ............................................................................................. 224-2 Receive Data Clocking .................................................................................................... 234-3 Transmit Data Clocking .................................................................................................... 234-4 Sample Rate Generator ................................................................................................... 244-5 CLKG Synchronization and FSG Generation When GSYNC = 1 and CLKGDV = 1 .............................. 264-6 CLKG Synchronization and FSG Generation When GSYNC = 1 and CLKGDV = 3 .............................. 264-7 Programmable Frame Period and Width ................................................................................ 294-8 Dual-Phase Frame Example .............................................................................................. 314-9 Single-Phase Frame and Four 8-Bit Elements ......................................................................... 324-10 Single-Phase Frame of One 32-Bit Element ............................................................................ 334-11 Data Delay .................................................................................................................. 334-12 Bit Data Delay Used to Discard Framing Bit ............................................................................ 344-13 AC97 Dual-Phase Frame Format ........................................................................................ 354-14 AC97 Bit Timing Near Frame Synchronization ......................................................................... 354-15 McBSP to ST-BUS Block Diagram ....................................................................................... 364-16 Double-Rate ST-BUS Clock Example ................................................................................... 364-17 Single-Rate ST-BUS Clock Example .................................................................................... 374-18 Double-Rate Clock Example .............................................................................................. 385-1 McBSP Standard Operation .............................................................................................. 405-2 Receive Operation ......................................................................................................... 405-3 Transmit Operation ......................................................................................................... 415-4 Maximum Frame Frequency for Transmit and Receive ............................................................... 415-5 Unexpected Frame Synchronization With (R/X) FIG = 0 ............................................................. 425-6 Unexpected Frame Synchronization With (R/X)FIG = 1 .............................................................. 435-7 Maximum Frame Frequency Operation with 8-Bit Data ............................................................... 435-8 Data Packing at Maximum Frame Frequency With (R/X)FIG = 1 ................................................... 445-9 Serial Port Overrun ......................................................................................................... 455-10 Serial Port Receive Overrun Avoided ................................................................................... 455-11 Decision Tree Response to Receive Frame Synchronization Pulse ................................................ 465-12 Unexpected Receive Synchronization Pulse ........................................................................... 465-13 Transmit With Data Overwrite ............................................................................................ 475-14 Transmit Empty ............................................................................................................. 485-15 Transmit Empty Avoided .................................................................................................. 485-16 Decision Tree Response to Transmit Frame Synchronization Pulse ................................................ 495-17 Unexpected Transmit Frame Synchronization Pulse .................................................................. 496-1 Companding Flow .......................................................................................................... 526-2 Companding Data Formats ............................................................................................... 526-3 Transmit Data Companding Format in DXR ............................................................................ 526-4 Companding of Internal Data ............................................................................................. 538-1 Element Enabling by Subframes in Partitions A and B ................................................................ 638-2 XMCM = 00b FOR XMCM Operation .................................................................................... 648-3 XMCM - 01b, XPABLK = 00b, XCER = 1010b for XMCM Operation ............................................... 648-4 XMCM = 10b, XPABLK = 00b, XCER = 1010b for XMCM Operation ............................................... 648-5 XMCM = 11b, RPABLK = 00b, XPABLK = X, RCER = 1010b, XCER = 1000b for XMCM Operation .......... 658-6 DX Timing for Multichannel Operation ................................................................................... 679-1 SPI Configuration: McBSP as the Master ............................................................................... 709-2 Configuration: McBSP as the Slave ..................................................................................... 709-3 SPI Transfer with CLKSTP = 10b ........................................................................................ 719-4 SPI Transfer with CLKSTP = 11b ........................................................................................ 7111-1 Data Receive Register (DRR) ............................................................................................ 81
SPRU580E – December 2005 List of Figures 5

11-2 Data Transmit Register (DXR) ............................................................................................ 8211-3 Serial Port Control Register (SPCR) ..................................................................................... 8311-4 Receive Control Register (RCR) ......................................................................................... 8611-5 Transmit Control Register (XCR) ......................................................................................... 8811-6 Sample Rate Generator Register (SRGR) .............................................................................. 9011-7 Multichannel Control Register (MCR).................................................................................... 9111-8 Receive Channel Enable Register (RCER) ............................................................................. 9311-9 Transmit Channel Enable Registers (XCER) ........................................................................... 9411-10 Enhanced Receive Channel Enable Registers (RCERE0-3) ......................................................... 9511-11 Enhanced Transmit Channel Enable Registers (XCERE0-3) ........................................................ 9811-12 Pin Control Register (PCR) .............................................................................................. 101

List of Figures6 SPRU580E – December 2005

List of Tables
1-1 Enhanced Features on TMS320C6000 McBSP ........................................................................ 122-1 McBSP Interface Pins ..................................................................................................... 153-1 Reset State of McBSP Pins ............................................................................................... 184-1 Receive Clock Selection ................................................................................................... 274-2 Transmit Clock Selection .................................................................................................. 274-3 Receive Frame Synchronization Selection.............................................................................. 294-4 Transmit Frame Synchronization Selection ............................................................................. 304-5 RCR/XCR Fields Controlling Elements per Frame and Bits per Element .......................................... 314-6 Receive/Transmit Frame Length Configuration ........................................................................ 314-7 Receive/Transmit Element Length Configuration ...................................................................... 324-8 Effect of RJUST Bit Values With 12-Bit Example Data ABCh ........................................................ 344-9 Effect of RJUST Bit Values With 20-Bit Example Data ABCDEh .................................................... 346-1 Justification of Expanded Data in DRR .................................................................................. 527-1 Receiver Clock and Frame Configurations ............................................................................. 567-2 Transmitter Clock and Frame Configurations .......................................................................... 569-1 SPI-Mode Clock Stop Scheme ........................................................................................... 7010-1 Configuration of Pins as General Purpose I/O ......................................................................... 7511-1 McBSP Registers for C620x/C670x DSP ............................................................................... 7711-2 McBSP Registers for C621x/C671x DSP ............................................................................... 7811-3 McBSP Registers for C64x DSP ......................................................................................... 7911-4 McBSP Registers for the C645x DSP ................................................................................... 8011-5 Data Receive Register (DRR) Field Descriptions ...................................................................... 8111-6 Data Transmit Register (DXR) Field Descriptions ..................................................................... 8211-7 Serial Port Control Register (SPCR) Field Descriptions .............................................................. 8311-8 Receive Control Register (RCR) Field Descriptions .................................................................. 8611-9 Transmit Control Register (XCR) Field Descriptions ................................................................. 8811-10 Sample Rate Generator Register (SRGR) Field Descriptions ........................................................ 9011-11 Multichannel Control Register (MCR) Field Descriptions ............................................................ 9111-12 Receive Channel Enable Register (RCER) Field Descriptions ....................................................... 9311-13 Transmit Channel Enable Register (XCER) Field Descriptions ...................................................... 9411-14 Enhanced Receive Channel Enable Registers (RCERE0-3) Field Descriptions ................................... 9511-15 Use of the Enhanced Receive Channel Enable Registers ............................................................ 9611-16 Enhanced Transmit Channel Enable Registers (XCERE0-3) Field Descriptions .................................. 9811-17 Use of the Enhanced Transmit Channel Enable Registers ........................................................... 9911-18 Pin Control Register (PCR) Field Descriptions ....................................................................... 101A-1 Document Revision History ............................................................................................. 103
SPRU580E – December 2005 List of Tables 7

List of Tables8 SPRU580E – December 2005

PrefaceSPRU580E – December 2005

Read This First

About This Manual

This document describes the operation of the multichannel buffered serial port (McBSP) in the digitalsignal processors (DSPs) of the TMS320C6000™ DSP family.

Notational Conventions

This document uses the following conventions.•Hexadecimal numbers are shown with the suffix h. For example, the following number is 40hexadecimal (decimal 64): 40h.•Registers in this document are shown in figures and described in tables.– Each register figure shows a rectangle divided into fields that represent the fields of the register.Each field is labeled with its bit name, its beginning and ending bit numbers above, and itsread/write properties below. A legend explains the notation used for the properties.– Reserved bits in a register figure designate a bit that is used for future device expansion.

Related Documentation From Texas InstrumentsThe following documents describe the C6000™ devices and related support tools. Copies of thesedocuments are available on the Internet at www.ti.com. Tip: Enter the literature number in the search boxprovided at www.ti.com.

TMS3206000 CPU and Instruction Set Reference Guide (literature number SPRU189) describes theTMS320C6000™ CPU architecture, instruction set, pipeline, and interrupts for these digital signalprocessors.

TMS320C6000 Technical Brief (literature number SPRU197) gives an introduction to the TMS320C62x™and TMS320C67x™ DSPs, development tools, and third-party support.

TMS320C64x Technical Overview (SPRU395) gives an introduction to the TMS320C64x™ DSP anddiscusses the application areas that are enhanced by the TMS320C64x VelociTI™.

TMS320C6455 Technical Reference (literature number SPRU965) gives an introduction to theTMS320C6455™ DSP and discusses the application areas that are enhanced.

TMS320C6000 Programmer's Guide (literature number SPRU198 ) describes ways to optimize C andassembly code for the TMS320C6000™ DSPs and includes application program examples.

TMS320C6000 Code Composer Studio Tutorial (literature number SPRU301 ) introduces the CodeComposer Studio™ integrated development environment and software tools.

Code Composer Studio Application Programming Interface Reference Guide (literature numberSPRU321 ) describes the Code Composer Studio™ application programming interface (API), which allowsyou to program custom plug-ins for Code Composer.

TMS320C6000 Chip Support Library API Reference Guide (literature number SPRU401 ) describes aset of application programming interfaces (APIs) used to configure and control the on-chip peripherals.

TMS320C64x+ Megamodule Reference Guide (literature number SPRU871 ) describes theTMS320C64x+ digital signal processor (DSP) megamodule. Included is a discussion on the internal directmemory access (IDMA) controller, the interrupt controller, the power-down controller, memory protection,bandwidth management, and the memory and cache.

TMS320C6000 DSP Peripherals Overview Reference Guide (literature number SPRU190 ) provides abrief description of the peripherals available on the TMS320C6000 digital signal processors (DSPs).

SPRU580E – December 2005 Read This First 9

www.ti.com

Related Documentation From Texas Instruments

TMS320C6455 Chip Support Libraries (CSL) (literature number SPRC234 ) is a download with the latestchip support libraries.

Read This First10 SPRU580E – December 2005

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