ST STM8 Manuel utilisateur

August 2016 DocID14024 Rev 4 1/39

UM0470

User manual

STM8 SWIM communication protocol and debug module

Introduction

This manual is addressed to developers who build programming, testing or debugging tools

for the STM8 8-bit MCUs family. This document explains the debug architecture of the

STM8 core.

The STM8 8-bit MCUs debug system includes two modules:

•DM: debug module

•SWIM: single wire interface module

Related documentation:

How to program STM8S and STM8A Flash program memory and data EEPROM (PM0051)

How to program STM8L and STM8AL Flash program memory and data EEPROM

(PM0054).

www.st.com

Contents UM0470

2/39 DocID14024 Rev 4

Contents

1 Debug system overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2 Communication layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3 Single wire interface module (SWIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3.1 Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3.2 SWIM entry sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3.3 Bit format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

3.3.1 High speed bit format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3.3.2 Low speed bit format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

3.4 SWIM communication protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

3.5 SWIM commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.5.1 SRST: system reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.5.2 ROTF: read on-the-fly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.5.3 WOTF: write on-the-fly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.6 SWIM communication reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.7 CPU register access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.8 SWIM communication in Halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3.9 Physical layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3.10 STM8 MCUs SWIM registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3.10.1 SWIM control status register (SWIM_CSR) . . . . . . . . . . . . . . . . . . . . . . 18

3.10.2 SWIM clock control register (CLK_SWIMCCR) . . . . . . . . . . . . . . . . . . . 19

4 Debug module (DM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4.2 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4.3 Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.3.1 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.3.2 Breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.3.3 Abort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.3.4 Watchdog control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.3.5 Interaction with SWIM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4.4 Breakpoint decoding table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

DocID14024 Rev 4 3/39

UM0470 Contents

4.5 Software breakpoint mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.6 Timing description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.7 Abort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.8 Data breakpoint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.9 Instruction breakpoint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.10 Step mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.11 Application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

4.11.1 Illegal memory access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

4.11.2 Forbidden stack access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

4.11.3 DM break . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

4.12 DM registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

4.12.1 DM breakpoint register 1 extended byte (DM_BKR1E) . . . . . . . . . . . . . 28

4.12.2 DM breakpoint register 1 high byte (DM_BKR1H) . . . . . . . . . . . . . . . . . 28

4.12.3 DM breakpoint register 1 low byte (DM_BKR1L) . . . . . . . . . . . . . . . . . . 28

4.12.4 DM breakpoint register 2 extended byte (DM_BKR2E) . . . . . . . . . . . . . 29

4.12.5 DM breakpoint register 2 high byte (DM_BKR2H) . . . . . . . . . . . . . . . . . 29

4.12.6 DM breakpoint register 2 low byte (DM_BKR2L) . . . . . . . . . . . . . . . . . . 29

4.12.7 DM control register 1 (DM_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

4.12.8 DM control register 2 (DM_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

4.12.9 DM control/status register 1 (DM_CSR1) . . . . . . . . . . . . . . . . . . . . . . . 32

4.12.10 DM control/status register 2 (DM_CSR2) . . . . . . . . . . . . . . . . . . . . . . . 33

4.12.11 DM enable function register (DM_ENFCTR) . . . . . . . . . . . . . . . . . . . . . 34

4.12.12 Summary of SWIM, DM and core register maps . . . . . . . . . . . . . . . . . . 35

Appendix A Description of the DM_ENFCTR register

for each STM8 product . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

List of tables UM0470

4/39 DocID14024 Rev 4

List of tables

Table 1. SWIM command summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 2. CPU register memory mapping in STM8 MCUs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 3. SWIM pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 4. Decoding table for breakpoint interrupt generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 5. STM8 MCU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 6. Peripherals which are frozen by the bits of the DM_ENFCTR register

for each STM8 product . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 7. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

DocID14024 Rev 4 5/39

UM0470 List of figures

List of figures

Figure 1. Debug system block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 2. SWIM pin external connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 3. SWIM activation sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 4. SWIM activation timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 5. SWIM entry sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 6. High speed bit format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 7. Low speed bit format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 8. Command format (host -> target) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 9. Data format (target -> host) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 10. Timings on the SWIM pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 11. Debug module block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 12. STM8 MCU instruction model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 13. STM8 Debug module stall timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 14. STM8 DM data breaktiming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 15. STM8 DM instruction break timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 16. STM8 DM step timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Debug system overview UM0470

6/39 DocID14024 Rev 4

1 Debug system overview

The STM8 MCUs debug system interface allows a debugging or programming tool to be

connected to the MCU through a single wire. This connection results in a bidirectional

communication based on an open-drain line and provides a non-intrusive read/write access

to RAM and peripherals during the program execution.

The block diagram is shown in Figure 1.

Figure 1. Debug system block diagram

The debug module uses the two internal clock sources present in the device:

•the low speed internal clock (LSI clock): usually in the range of 30 kHz to 200 kHz

depending on the product

•the high speed internal clock (HSI clock): usually in the range of 10 MHz to 25 MHz

depending on the device.

The clocks are automatically started when necessary.

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DocID14024 Rev 4 7/39

UM0470 Communication layer

2 Communication layer

The SWIM is a single wire interface based on asynchronous, high sink (8 mA), open-drain,

bidirectional communication. While the CPU is running, the SWIM allows a non-intrusive

read/write accesses to be performed on-the-fly to the RAM and peripheral registers, for

debug purposes.

In addition, while the CPU is stalled, the SWIM allows read/write accesses to be performed

to any other part of the MCU’s memory space (data EEPROM and program memory).

The CPU registers (A, X, Y, CC, SP) can also be accessed. These registers are mapped in

the memory and can be accessed in the same way as any other memory addresses. It is

important to note that:

•Register, peripherals and memory can be accessed only when the SWIM_DM bit is set.

•When the system is in HALT, WFI or readout protection mode, the NO_ACCESS flag in

the SWIM_CSR register is set. In this case, it is forbidden to perform any accesses

because parts of the device may not be clocked and a read access could return

garbage or a write access might not succeed.

The SWIM can perform a MCU device software reset. The SWIM pin can also be used by

the MCU target application as a standard I/O port with some restrictions if the user also want

to use it for debug. The safest way is to provide a strap option on the application PCB.

Figure 2. SWIM pin external connections

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Single wire interface module (SWIM) UM0470

8/39 DocID14024 Rev 4

3 Single wire interface module (SWIM)

3.1 Operating modes

After a power-on reset (powering of the device) the SWIM is reset and enters in its OFF

mode.

1. OFF: in this mode the SWIM pin must not be used as an I/O by the application. It is

waiting for the SWIM entry sequence or to be switched to I/O mode by the software

application.

2. I/O: this state is entered by the software application by setting the SWIM disable bit

(SWD) in the core configuration register (CFG_GCR). In this state, the user application

can use the SWIM pin as a standard I/O pin, the only drawback is that there is no way

to debug the functionality of this pin with the built-in debug capabilities.

In case of a reset, the SWIM goes back to OFF mode.

3. ACTIVE: this mode is entered when a specific sequence is detected on the SWIM pin

while it is in the OFF state. In this state, the SWIM pin is used by the host tool to control

the STM8 device with three commands: SRST (system reset), ROTF (read on-the-fly)

and WOTF (write on-the-fly).

Note: Please note that the SWIM can be set as ACTIVE and communicate while the device is in

RESET state (NRST pin forced low).

Figure 3. SWIM activation sequence

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DocID14024 Rev 4 9/39

UM0470 Single wire interface module (SWIM)

3.2 SWIM entry sequence

After a POR (power on reset), and as long as the SWIM is in OFF mode, the SWIM pin is

sampled for entry sequence detection. In order to do this, the internal LSI (low speed RC -

resistor/capacitor) clock is automatically turned ON after the POR and remains forced ON

as long as the SWIM is in OFF mode.

If the register that forces the SWIM in I/O mode is written before the entry sequence is

finalized, the SWIM enters in I/O mode. Once the SWIM is ACTIVE, writing this bit has no

influence on communication and the SWIM interface remains in ACTIVE mode.

If an application uses the SWIM pin as standard I/O, it puts the SWIM interface in I/O mode

in the initialization section of the software code (typically, this is performed just after the

reset). However, even in this case, it is still possible to put the SWIM interface in ACTIVE

mode by forcing the RESET pin to 0 and keep it low for the duration of the SWIM entry

sequence.

As long as the SWIM is in OFF mode, the SWIM entry sequence is detected at any moment,

during reset or when the application is running.

If both the SWIM pin and the reset pin are multiplexed with I/Os, the way to enter the SWIM

in ACTIVE state is to power down the MCU device, power up and to maintain the reset until

the end of the SWIM entry sequence.

Figure 4. SWIM activation timing diagram

The SWIM activation is shown in Figure 4 and each segment of the diagram is described

below:

1. To make the SWIM active, the SWIM pin must be forced low during a period of 16 µs.

2. After this first pulse at 0, the SWIM detects a specific sequence to guarantee the

robustness in the SWIM active state entry. The SWIM entry sequence is: four pulses at

1kHz followed by four pulses at 2 kHz. The frequency ratio is detected and allows the

SWIM entry. The ratio can be easily detected regardless of the internal LSI frequency

value. The waveform of the entry sequence is shown in Figure 5. Note that the

sequence starts and ends with the SWIM pin at 1.

3. After the entry sequence, the SWIM enters in SWIM active state, and the HSI oscillator

is automatically turned ON.

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Single wire interface module (SWIM) UM0470

10/39 DocID14024 Rev 4

4. After this delay, the SWIM sends a synchronization frame to the host.

Synchronization frame description: a synchronization frame of 128 x SWIM clocks

periods with the SWIM line at 0 is sent out by the MCU device to allow the

measurement of the HSI by the debug host. An advanced debug host can re-calibrate

its clock to adapt to the frequency of the internal HSI RC oscillator.

5. Before starting a SWIM communication, the SWIM line must be released at 1 to

guarantee that the SWIM is ready for communication (at least 300 ns).

6. Write 0A0h in the SWIM_CSR:

- setting the bit 5 allows the whole memory range and the SRST command to be

accessed.

- setting the bit 7 masks the internal reset sources

7. Release the reset which starts the option byte loading sequence. Wait 1 ms for

stabilization.

8. Once the option byte loading has occurred and that the stabilization time is reached,

the CPU is in phase 8:

- STM8 is stalled and HSI = 16 Mhz (see STM8 datasheets for HSI clock accuracy)

- SWIM clock is at HSI/2 = 8 Mhz

- SWIM is active in low speed bit format (see Section 3.3.2)

9. After the HSI is calibrated internally, a copy of the factory calibration value is uploaded

from the option bytes and stored into the HSI calibration register at the RAM, then a

SWIM communication reset command can be generated to get the synchronization

frame again but with greater reliability than in step 4. Depending on the target context

since power on, the HSI clock could be not well calibrated in step 4, because at that

moment the HSI calibration register in the RAM is not yet initialized with the proper

value.

Figure 5. SWIM entry sequence

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