Silicon Laboratories Si4010 Series Mode d'emploi

AN370

Si4010 SOFTWARE PROGRAMMING GUIDE

1. Purpose

This document defines the application programming interface (API) for the Si4010 firmware. It is intended to serve

as a guide for application development.

The document is related to the device revision 0x02 as returned by bSys_GetRevId() function and Trim version

0x09 as returned by the Device Information in the NVM Programming Utility. It describes files needed to build

customer application and the details of the implemented API functions in ROM. There are also additional API

functions not present in ROM, provided in the form of a linkable library for the Keil toolchain. For a description of

this additional library, see “AN526: Si4010 API Additional Library Description”.

2. Known Issues

These are known issues related to the current version of the Si4010 device hardware revision 0x02 as returned by

bSys_GetRevId() function and Trim version 0x09 as returned by the Device Information in the NVM Programming

Utility.

There is an issue related to the LED driver, which demonstrates itself only under the following circumstances

when all three conditions are satisfied:

The device programming level is Factory or User. For those levels the C2 debugging interface is enabled after the boot by

a boot routine.

The device has been disconnected from the Silicon Labs IDE. The "disconnected" means in a software sense, not

physically, using the Connect/Disconnect buttons on IDE. Or, the device is running the User code automatically after the

boot without ever being connected to the IDE.

The device is running a code which turns the LED on and off.

If all the conditions are satisfied then after the first LED blink when the LED is turned off the GPIO4 stops working

and is no longer visible to the application.

If the device programming level is Run or the C2 debugging interface is internally disabled there is no issue. The

LED can be turned on and off without affecting the device GPIO4 functionality.

The issue can be summarized as follows: Whenever the C2 debugging interface is enabled, the device is not

connected to IDE, and the LED is turned on and off, then the GPIO4 will stop functioning. Since in Run mode the

C2 is disabled after the boot process finishes, the GPIO4 is not affected.

Therefore, this issue only effects software development process and inconveniences the developer. After the

application is finalized and the chip is programmed as Run there is no issue. See suggested solution scenarios and

workarounds in the section related to debugging with LED.

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2 Rev. 1.0

AN370

Rev. 1.0 3

TABLE OF CONTENTS

Section Page

1. Purpose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

2. Known Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

3. Memory Regions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

3.1. 8051 Internal Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

3.2. Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

3.3. CODE/XDATA RAM Reserved Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

3.4. DATA/IDATA Internal Memory Reserved Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

4. Building an Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

4.1. Type Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

4.2. Naming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

4.3. Included Library Routines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

4.4. Stack Size Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

4.5. Hardware Thread Safety . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

4.6. Non-ISR Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

4.7. Function Calling Convention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

4.8. Files Needed for Building an Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

4.9. Compiling an Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

5. User Application Required Interrupt Service Routines . . . . . . . . . . . . . . . . . . . . . . . . .20

6. Interrupt and System Impact of Some Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

6.1. Interrupt Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

6.2. Interrupt Enable Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

6.3. System Clock Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

6.4. Transmission Chain Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

6.5. Infinite Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

7. Module Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

7.1. AES Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

7.2. Button Service Module and Master Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

7.3. Demodulator Temperature Sensor Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

7.4. Encoding Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48

7.5. Frequency Counter Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

7.6. Frequency Casting Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56

7.7. HVRAM Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

7.8. Multi-time Programmable (MTP) Memory Module . . . . . . . . . . . . . . . . . . . . . . . . . .61

7.9. Battery Voltage Measurement Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

7.10. Non-Volatile Memory (NVM) Copy Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69

7.11. Output Data Serializer (ODS) Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74

7.12. Power Amplifier (PA) Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77

7.13. Single Transmission Loop (STL) Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80

7.14. System Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85

7.15. Sleep Timer Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95

8. Simple Application Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98

Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102

Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104

AN370

4 Rev. 1.0

3. Memory Regions

The following table lists some key terms for writing firmware for the Si4010:

Term Definition

8051 Internal

Memory 256 bytes of RAM internal to the 8051 MCU. Fastest for MCU to access. It is broken into

three categories, DATA, IDATA and SFR space. See below for a description of these.

DATA Portion of the internal memory at addresses 0x00 through 0x7F. This memory can be

accessed both directly and indirectly.

DATA is a recognized Keil compiler keyword.

IDATA Portion of the internal memory occupying addresses 0x80 through 0xFF. This memory can

only be accessed indirectly. IDATA is a recognized Keil compiler keyword.

SFR Space Special Function Register Space is located in internal memory at addresses 0x80 through

0xFF. This memory can only be accessed directly.

CODE

XDATA This is both user code memory (CODE) and external data memory (XDATA). Residing at

addresses 0x0000 through 0x11FF. In the Si4010 this space is equivalent to the 4.5 kB of

on chip RAM. CODE/XDATA RAM is where the user application is run from.

CODE and XDATA are recognized Keil compiler keywords.

XREG Refers to the set of hardware registers located in XDATA address space at addresses

0x4000 through 0x40FF. More information on XREGs can be found in the Si4010 data

sheet.

This is not a recognized Keil compiler keyword.

ROM Read only memory containing all the API functions. Residing at CODE addresses 0x8000

through 0xAFFF. The CPU executes ROM code directly. ROM is not readable by the user

application.

NVM Non-Volatile Memory. Each bit can only be written as 1 once (One Time Programmable,

OTP). Code stored in this memory is intended to be loaded into RAM upon boot. It is also

possible for the application to copy code from NVM using the NVM Copy Module. Virtually

mapped to addresses 0xE000 through 0xFFFF. Only accessible by using API functions.

Only formatted data programmed by the NVM composer/programmer are available to be

loaded at boot time or at runtime by bNvm_CopyBlock() function. There is not byte by byte

direct access to NVM.

MTP 128 bits of Multi-Time Programmable Memory (EEPROM). This memory is mapped as read

only at XDATA addresses 0x4040 to 0x404F. Writing to MTP can only be done through the

MTP API Module. User should use the MTP API for read access as well.

HVRAM HVRAM in the Si4010 consists of 64 bits (8 bytes) of battery backed RAM. As long as the

power is connected to the chip, the HVRAM keeps its content. The content of the HVRAM

is not affected by shutting down the chip by vSys_Shutdown() function. Only accessible by

using the HVRAM API module functions.

AN370

Rev. 1.0 5

3.1. 8051 Internal Memory

Figure 1 shows the Si4010 memory which is internal to the 8051 MCU.

Figure 1. CPU Internal Memory Organization

3.2. Memory Map

After the chip boots, the memory on the Si4010 is mapped as shown in Figure 2. The 4.5 kB RAM section is

accessible both as CODE and XDATA (MOVC and MOVX instructions). The XREG region is accessible only as

XDATA (MOVX). The ROM is not accessible as data, but the code residing in ROM can be executed. The NVM is

virtually mapped into this region, but is not directly accessible by CPU. The NVM API functions must be used to

access the NVM.

Figure 2. Si4010 Unified CODE/XDATA Memory Organization

Indirect addressing only

by @Ri pointers

DATA

IDATA

SFR

(DATA)

0x00

0x7F

0x80

0xFF

0x80

0xFF

MOV A, @Ri

Direct addressing only

MOV A, addr

Both direct and indirect addressing

Internal Memory

0x0000 RAM 4.5K

0xFFFF

CODE/

XDATA

0x8000

0x4000

64KB

16KB

ROM 12K

XREG

0xE000 NVM 8K

0x11FF

0x40FF

0xAFFF

Virtual mapping, not directly

accessible by CPU

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6 Rev. 1.0

3.3. CODE/XDATA RAM Reserved Area

Part of CODE/XDATA space at the end of the RAM (highest addresses) is reserved for the ROM API. This area

must not be used by the application. The following diagram gives an outline of the used space. The area used by

the API and other factory settings may change dynamically per chip. The user should read (through Silicon Labs

IDE, for example) the value of the wBoot_DpramTrimBeg variable, which points to the first used address in the

CODE/XDATA RAM. Any location at lower address then the one pointed to by the content of the

wBoot_DpramTrimBeg variable is available for customer user. See the Boot section in the Si4010 data sheet.

Figure 3. CODE/XDTA RAM Organization

Important: The user application must not overwrite the Factory and Boot XDATA region during runtime. There is

no hardware protection of that region, so it is up to the customer discipline not to place any CODE nor XDATA

variables. If that happens, the behavior of the chip becomes unpredictable.

3.4. DATA/IDATA Internal Memory Reserved Area

Portions of the 8051 MCU internal memory are also used by ROM API code. The following diagram shows DATA

and IDATA used by ROM API code. The provided file si4010_link.c must be compiled and link with the

application. The file contains dummy arrays at fixed addresses to notify the linker not to put any data into the

reserved regions.

The user must set the stack pointer such that the stack will never overwrite the reserved regions.

Boot_AfterTrimExe

Boot_PatchExe

Reserved

Boot XDATA

0x0000

Factory

XDATA

bBoot_BootStat

wBoot_NvmCopyAddr

wBoot_NvmUserBeg

wBoot_DpramTrimBeg

User

CODE/

XDATA

0x11FF

0x11FD

0x11F3

0x11F5

CODE/XDATA

RAM 4.5KB

0x11F7

AN370

Rev. 1.0 7

Figure 4. DATA/IDATA Reserved Spaces

Note that the region used by the ROM API is split in between the DATA and IDATA to allow the continuous region

of 128 bytes, split evenly in between DATA and IDATA regions. This will allow for a byte array of that size. The bit

addressable region of 16 bytes is not used by the API. All four register banks are shown as available. However, the

user should assume that the API functions destroy all the registers R0 .. R7 of the currently selected bank.

API functions use the register bank currently selected by the user application. The API functions do not access

RB0 directly. User is free to choose any register bank for main application and any register bank for interrupt

service routines.

API

Reserved

(16B)

0x20

Registers

RB1 .. RB3

Available

(24B)

Bit Addr

Available

(16B)

0x2F

0x30

0x3F

DATA/IDATA

MCU Internal RAM

DATA .. lower 128

RAM bytes, Direct

and Indirect

Addressing

Available

(64B)

0x40

0x7F

Available

(64B)

0x80

API

Reserved

(64B)

0xC0

0xFF

0xBF

0x08

0x1F

Reg RB0

Available

(8B)

0x00

0x07

IDATA ..

upper128 RAM

bytes, Indirect

Addressing only

DATA/IDATA ..continuous

128 RAM bytes user

region

AN370

8 Rev. 1.0

4. Building an Application

4.1. Type Definitions

The following table lists types that are defined or expected for use with the Si4010 API. The custom types are

defined in the header file si4010_types.h.

All variables are stored in big endian fashion, which means that the most significant byte is stored on the lowest

(smallest) address location.

4.2. Naming

Strict naming conventions are used for the API. Each function belonging to the same software module is prefixed

by the module name or module name abbreviation. Before the module name, the function name is prefixed by the

type of the return value.

All variables are prefixed by their type. Defined types, pointers, input and output variables, and pointers to input/

output function variables are also prefixed accordingly. In addition to the prefixes for the basic types in the table in

section 4.1, the following prefixes are used. The dot in the prefix specification means that the letter cannot stand on

its own and must be preceded or succeeded by another prefix letter or letters:

Type Bit Width Type Definition Prefix

unsigned char 8 BYTE b

unsigned int 16 WORD w

unsigned long int 32 LWORD l

signed char 8 CHAR c

int 16 i

long int 32 j

float 32 f

Prefix Description Example

t Type definition of a structure tBsr_Setup

r Structure variable definition rSetup

p. Pointer to prSetup

v Void vBsr_Setup()

.i Input function variable biTstCtrl

..o Output function variable. Make sense if used

as a pointer to output. The pointed content is

generated by the function.

*pboOutput

..io Input/output function variables. Make sense

if used as a pointer. The pointed content is

used as input and modified by a function.

*pbioState

AN370

Rev. 1.0 9

The module naming prefixes used are as follows:

Example:

void vAes_Cipher /* AES 128 bit key encryption .. works

on global IDATA State and RoundKey */

(

BYTE idata *pbioState,

BYTE idata *pbioRoundKey

);

The function returns void (v) and is a part of the AES (Aes) module. It has two input pointer variables (p), both

pointing into the DATA/IDATA internal memory at a BYTE (b). The area pointed to is both input to the function and

is modified by the function (io).

Module Prefix Module Name

Aes AES

Bsr Button service routine

DmdTs Temperature sensor and its demodulator

Enc Encoding of data for transmission

Fc Frequency counter

FCast Frequency casting and fine tuning

Hvram HVRAM

Mtp MTP (EEPROM) memory

MVdd Battery VDD measurement

Nvm NVM memory for copying data to RAM

Ods Output data serializer

Pa Power amplifier

Sys System functions

SleepTim Sleep timer

Stl Single Tx loop

AN370

10 Rev. 1.0

4.3. Included Library Routines

Following is a list of all Keil library routines included in ROM. They are available for use by the application via the

ROM symbol map file for Keil toolchain (si4010_rom_keil.a51).

The library routines cannot be used with other toolchains. If the user does not desire to link these library routines to

the application (they take precedence over the actual library provided by the toolchain), then it is necessary to use

si4010_rom_all.a51 instead of the Keil specific toolchain during the application building.

?C?ULSHR

?C?LSHL

?C?OFFXADD

?C?FPSUB

?C?FPADD

?C?FPMUL

?C?FCASTL

?C?FCASTC

?C?FCASTI

?C?CASTF

?C?FPGETOPN2

?C?FPNANRESULT

?C?FPOVERFLOW

?C?FPRESULT

?C?FPRESULT2

?C?FPUNDERFLOW

?C?LNEG

?C?LLDIDATA

?C?LLDXDATA

?C?LLDIDATA0

?C?LLDXDATA0

?C?LSTIDATA

?C?LSTXDATA

?C?LMUL

?C?ULCMP

?C?LOR

?C?LADD

?C?IMUL

?C?LSUB

?C?LXOR

?C?FPDIV

?C?ULDIV

?C?SIDIV

?C?PCMP3

?C?FPCMP

?C?UIDIV

?C?SLDIV

_ABS

?C?ICALL

?C?ICALL2

?C?IILDX

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