Silicon Laboratories Si5397 Series Manuel utilisateur

Si5397/96 Reference Manual

Quad/Dual DSPLL Any-frequency, Any-output Jitter

Attenuators Si5397/96 Family Reference Manual

This Family Reference Manual is intended to provide system, PCB de-

sign, signal integrity, and software engineers the necessary technical

information to successfully use the Si5397/96 devices in end applica-

tions. The official device specifications can be found in the Si5397/96

data sheets.

The Si5397 is a high-performance, jitter-attenuating clock multiplier

that integrates four any-frequency DSPLLs for applications that require

maximum integration and independent timing paths. The Si5396 is a

dual DSPLL version in a smaller package. Each DSPLL has access to

any of the four inputs and can provide low-jitter clocks on any of the

device outputs. Based on 4th generation DSPLL technology, these de-

vices provide any-frequency conversion with superior jitter perform-

ance. Each DSPLL supports independent free-run, holdover modes of

operation, and offers automatic and hitless input clock switching. The

Si5397/96 is programmable via a serial interface with in-circuit pro-

grammable non-volatile memory so that it always powers up with a

known configuration. Programming the Si5397/96 is made easy with

Silicon Labs’ ClockBuilder Pro software. Factory preprogrammed devi-

ces are available.

All devices of the 9x family offer the option of an external reference or

an internal reference. Please refer to the datasheet for the different de-

vice ordering options and restrictions.

RELATED DOCUMENTS

•Si5397/96 Data Sheet

•UG353: Si5397 Evaluation Board User's Guide

•UG336: Si5396 Evaluation Board User's Guide

•Recommended Crystal, TCXO, and OCXO Reference

Manual for High-Performance Jitter Attenuators and Clock

Generators

•AN1178: Frequency-On-the-Fly for Silicon Labs Jitter

Attenuators and Clock Generators

•AN1155: Differences between Si5342-47 and Si5392-97

silabs.com | Building a more connected world. Rev. 0.9

Table of Contents

1. Work Flow Using ClockBuilder Pro and the Register Map...............

1.1 Field Programming ............................6

2. Family Product Comparison..........................7

3. Functional Description............................8

3.1 DSPLL and MultiSynth ...........................8

3.1.1 Dividers ...............................9

3.1.2 DSPLL Loop Bandwidth .........................10

4. Modes of Operation ............................12

4.1 Reset and Initialization ...........................13

4.2 Dynamic PLL Changes ...........................14

4.3 NVM Programming ............................15

4.4 Free Run Mode ..............................16

4.5 Lock Acquisition Mode ...........................16

4.6 Locked Mode ..............................16

4.7 Holdover Mode ..............................17

5. Clock Inputs............................... 20

5.1 Input Source Selection ...........................20

5.1.1 Manual Input Switching..........................21

5.1.2 Automatic Input Switching .........................21

5.2 Types of Inputs ..............................22

5.2.1 Unused Inputs.............................24

5.2.2 Hitless Input Switching with Phase Buildout ...................25

5.2.3 Ramped Input Switching .........................26

5.2.4 Hitless Switching, LOL (Loss of Lock) and Fastlock ................26

5.2.5 External Clock Switching .........................26

5.2.6 Synchronizing to Gapped Input Clocks ....................27

5.2.7 Rise Time Considerations .........................28

5.3 Fault Monitoring .............................29

5.3.1 Input Loss of Signal (LOS) Fault Detection ...................30

5.3.2 Out of Frequency (OOF) Fault Detection ....................31

5.3.3 Loss of Lock (LOL) Fault Monitoring .....................33

5.3.4 Interrupt Pin (INTR) ...........................35

6. Outputs ................................37

6.1 Output Crosspoint Switch ..........................38

6.2 Output Divider (R) Synchronization .......................39

6.3 Performance Guidelines for Outputs .......................39

6.4 Output Signal Format ............................40

6.4.1 Differential Output Terminations.......................41

6.4.2 Differential Output Swing Modes ......................42

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6.4.3 Programmable Common Mode Voltage for Differential Outputs ............43

6.4.4 LVCMOS Output Terminations .......................43

6.4.5 LVCMOS Output Impedance and Drive Strength Selection..............43

6.4.6 LVCMOS Output Signal Swing .......................44

6.4.7 LVCMOS Output Polarity .........................45

6.4.8 Output Driver Settings for LVPECL, LVDS, HCSL, and CML .............46

6.4.9 Setting the Differential Output Driver to Non-Standard Amplitudes ...........47

6.5 Output Enable/Disable ...........................48

6.5.1 Output Driver State When Disabled .....................49

6.5.2 Synchronous Output Enable/Disable Feature ..................50

6.6 Output Buffer Supply Voltage Selection......................50

7. Digitally-Controlled Oscillator (DCO) Mode ...................51

7.1 Frequency Increment/Decrement Using Pin Controls .................52

7.2 Frequency Increment/Decrement Using the Serial Interface ...............54

7.2.1 DCO with Direct Register Writes ......................56

8. Frequency-On-The-Fly for Si5397/96 .....................57

9. Serial Interface .............................. 59

9.1 I2C Interface ...............................61

9.2 SPI Interface...............................63

10. XAXB References ............................68

10.1 External References ...........................68

10.2 Recommended Crystals and Oscillators .....................68

10.3 Register Settings to Configure for External XTAL Reference ..............69

10.3.1 XAXB_EXTCLK_EN Reference Clock Selection Register ..............69

10.3.2 PXAXB Pre-scale Divide Ratio for Reference Clock Register ............69

11. Internal Reference ............................70

12. Crystal, XO and Device Circuit Layout Recommendations .............71

12.1 64-Pin QFN Si5397 Layout Recommendations...................71

12.1.1 Si5397 XO Guidelines .........................71

12.1.2 Si5397 Crystal Guidelines ........................72

12.1.3 Si5397 Output Clocks ..........................78

12.2 64-Pin LGA Si5397 Layout Recommendations ...................79

12.3 44-Pin QFN Si5396 Layout Recommendations...................80

12.3.1 Si5396 XO Guidelines .........................80

12.3.2 Si5396 Crystal Guidelines ........................81

12.4 44-Pin LGA Si5396 Layout Recommendations ...................86

13. Power Management ...........................87

13.1 Power Management Features ........................87

13.2 Power Supply Recommendations .......................87

13.3 Power Supply Sequencing .........................87

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13.4 Grounding Vias .............................88

14. Register Map ..............................89

14.1 Base vs. Factory Preprogrammed Devices ....................89

14.2 “Base” Devices (a.k.a. “Blank” Devices) .....................89

14.3 “Factory Preprogrammed” (Custom OPN) Devices .................89

14.4 Register Map Overview and Default Settings Values .................90

15. Si5397A/B Register Map ..........................91

15.1 Page 0 Registers Si5397A/B .........................91

15.2 Page 1 Registers Si5397A/B ........................111

15.3 Page 2 Registers Si5397A/B ........................117

15.4 Page 3 Registers Si5397A/B ........................128

15.5 Page 4 Registers Si5397A/B ........................130

15.6 Page 5 Registers Si5397A/B ........................140

15.7 Page 6 Registers Si5397A/B ........................150

15.8 Page 7 Registers Si5397A/B ........................160

15.9 Page 9 Registers Si5397A/B ........................170

15.10 Page A Registers Si5397A/B .......................171

15.11 Page B Registers Si5397A/B .......................172

15.12 Page C Registers Si5397A/B .......................175

16. Si5397C/D Register Map ..........................177

16.1 Page 0 Registers Si5397C/D ........................177

16.2 Page 1 Registers Si5397C/D ........................197

16.3 Page 2 Registers Si5397C/D ........................201

16.4 Page 3 Registers Si5397C/D ........................212

16.5 Page 4 Registers Si5397C/D ........................214

16.6 Page 5 Registers Si5397C/D ........................224

16.7 Page 6 Registers Si5397C/D ........................234

16.8 Page 7 Registers Si5397C/D ........................244

16.9 Page 9 Registers Si5397C/D ........................254

16.10 Page A Registers Si5397C/D .......................255

16.11 Page B Registers Si5397C/D .......................256

16.12 Page C Registers Si5397C/D .......................259

17. Si5396 Register Map ...........................261

17.1 Page 0 Registers Si5396 .........................261

17.2 Page 1 Registers Si5396 .........................278

17.3 Page 2 Registers Si5396 .........................282

17.4 Page 3 Registers Si5396 .........................290

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17.5 Page 4 Registers Si5396 .........................292

17.6 Page 5 Registers Si5396 .........................301

17.7 Page 9 Registers Si5396 .........................311

17.8 Page A Registers Si5396 .........................312

17.9 Page B Registers Si5396 .........................313

17.10 Page C Registers Si5396 ........................315

18. Revision History.............................316

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1. Work Flow Using ClockBuilder Pro and the Register Map

This reference manual is to be used to describe all the functions and features of the parts in the product family with register map details

on how to implement them. It is important to understand that the intent is for customers to use the ClockBuilder Pro software to provide

the initial configuration for the device. Although the register map is documented, all the details of the algorithms to implement a valid

frequency plan are fairly complex and are beyond the scope of this document. Real-time changes to the frequency plan and other oper-

ating settings are supported by the devices. However, describing all the possible changes is not a primary purpose of this document.

Refer to the applications notes and Knowledge Base articles within the ClockBuilder Pro GUI for information on how to implement the

most common, real-time frequency plan changes.

The primary purpose of the software is to enable use of the device without an in-depth understanding of its complexities. The software

abstracts the details from the user to allow focus on the high level input and output configuration, making it intuitive to understand and

configure for the end application. The software walks the user through each step, with explanations about each configuration step in the

process to explain the different options available. The software will restrict the user from entering an invalid combination of selections.

The final configuration settings can be saved, written to an EVB and a custom part number can be created for customers who prefer to

order a factory preprogrammed device. The final register maps can be exported to text files, and comparisons can be done by viewing

the settings in the register map described in this document.

1.1 Field Programming

To simplify design and software development of systems using the Si5397/96, a field programmer is available in addition to the evalua-

tion board. The ClockBuilder Pro Field Programmer supports both “in-system” programming (for devices already mounted on a PCB),

as well as “in-socket” programming of Si5397/96 sample devices. Refer to www.silabs.com/CBProgrammer for information about this

kit.

Si5397/96 Reference Manual

Work Flow Using ClockBuilder Pro and the Register Map

silabs.com | Building a more connected world. Rev. 0.9 | 6

2. Family Product Comparison

The following table is a comparison of the different parts in the product family showing the differences in the inputs, MultiSynths, out-

puts and package type.

Table 2.1. Family Feature Comparison

Part Number

Internal/External

Reference

Number of Inputs Number of Multi-

Synths Number of Outputs Package Type

Si5397A/B External 4 4 8 64-QFN

Si5397J/K Internal 4 4 8 64-LGA

Si5397C/D External 4 4 4 64-QFN

Si5397L/M Internal 4 4 4 64-LGA

Si5396A/B External 4 2 4 44-QFN

Si5396J/K Internal 4 2 4 44-LGA

Si5397/96 Reference Manual

Family Product Comparison

silabs.com | Building a more connected world. Rev. 0.9 | 7

3. Functional Description

The Si5397 takes advantage of Silicon Labs fourth-generation DSPLL technology to offer the industry’s most integrated and flexible

jitter attenuating clock generator solution. Each of the DSPLLs operate independently from each other and are controlled through a

common serial interface. Each DSPLL has access to any of the four inputs (IN0 to IN3) after having been divided down by the P divid-

ers, which are either fractional or integer. Clock selection can be either manual or automatic. Any of the output clocks can be configured

to any of the DSPLLs using a flexible crosspoint connection. The Si5396 is a smaller form factor dual DSPLL version with four inputs

and four outputs.

The Si5397J/K is the internal refernce version of the Si5397A/B. Si5397L/M is the internal reference version of Si5397C/D. Si5396J/K is

the internal reference version of Si5396A/B. All the features and functions are the same. The only difference is that the reference is

integrated into the package. The registers and features of the external reference parts match that of the internal reference parts.

Throughout this document the register descriptions for labels of the external reference grades can be assumed to be the same for the

internal reference grades.

3.1 DSPLL and MultiSynth

The DSPLL is responsible for input frequency translation, jitter attenuation and wander filtering. Fractional input dividers (Pxn/Pxd) al-

low for integer or fractional division of the input frequency, but the input frequencies must be integer related to allow the DSPLL to per-

form hitless switching between input clocks (INx). Input switching is controlled manually or automatically using an internal state ma-

chine. The oscillator circuit (OSC) provides a frequency reference which determines output frequency stability and accuracy while the

device is in free-run or holdover mode. Note that a XTAL (or suitable XO reference on XA/XB) is always required and is the jitter refer-

ence for the device. The high-performance MultiSynth dividers (Nxn/Nxd) generate integer or fractionally related output frequencies for

the output stage. A crosspoint switch connects any of the generated frequencies to any of the outputs. A single MultiSynth output can

connect to one or more output drivers. Additional integer division (R) determines the final output frequency. The internal reference

grade devices have a XTAL integrated in the package, so no external XTAL is needed. The specs for the integrated reference can be

found in the data sheet.

Si5397

DSPLL

IN1

IN2

IN3

IN0

OUT7

OUT6

OUT5

OUT1

OUT4

OUT3

OUT2

OUT0

÷INT

÷FRAC

Si5347C/D

NVM

I2C/SPI

Control/

Status

XTAL/

REFCLK

XBXA

OSC

Si5347A/B

Si5396

DSPLL

IN1

IN2

IN3

IN0

OUT1

OUT3

OUT2

OUT0

÷INT

÷FRAC

NVM

I2C/SPI

Control/

Status

XTAL/

REFCLK

XBXA

OSC

Figure 3.1. DSPLL and Multisynth System Flow Diagram

The frequency configuration of the DSPLL is programmable through the SPI or I2C serial interface and can also be stored in non-vola-

tile memory. The combination of fractional input dividers (Pn/Pd), fractional frequency multiplication (Mn/Md), fractional output Multi-

Synth division (Nn/Nd), and integer output division (Rn) allows the generation of virtually any output frequency on any of the outputs. All

divider values for a specific frequency plan are easily determined using the ClockBuilder Pro software.

Si5397/96 Reference Manual

Functional Description

silabs.com | Building a more connected world. Rev. 0.9 | 8

3.1.1 Dividers

There are five main divider classes within the Si5397/96. Additionally, FSTEPW can be used to adjust the nominal output frequency in

DCO mode. See Section 7. Digitally-Controlled Oscillator (DCO) Mode for more information and block diagrams on DCO mode.

• 1. PXAXB: Reference input divider (0x0206)

• Divide reference clock by 1, 2, 4, or 8 to obtain an internal reference < 125 MHz

• 2. P0-P3: Input clock wide range dividers (0x0208-0x022F)

• Integer or Fractional divide values

•Min. value is 1, Max. value is 224 (Fractional-P divisors must be > 5)

• 48-bit numerator, 32-bit denominator

• Practical P divider range of (Fin / 2 MHz) < P < (Fin / 8 kHz)

• Each P divider has a separate update bit for the new divider value to take effect

• 3. MA-MD: DSPLL feedback dividers (0x0415-0x041F, 0x0515-0x051F, 0x0615-0x061F, 0x0716-0x0720)

• Integer or Fractional divide values

•Min. value is 1, Max. value is 224 (Fractional-M divisors must be > 10)

• 56-bit numerator, 32-bit denominator

• Practical M divider range of (Fdco / 2 MHz) < M < (Fdco / 8 kHz)

• Each M divider has a separate update bit for the new divider value to take effect

• Soft reset will also update M divider values

• 4. Output N dividers N0-N3(0x0302-0x032D)

• MultiSynth divider

• Integer or fractional divide values

• 44 bit numerator, 32 bit denominator

• Each divider has an update bit that must be written to cause a newly written divider value to take effect.

• 5. R0-R7: Output dividers (0x024A-0x026A)

• 24-bit field

•Min. value is 2, Max. value is 225-2

• Only even integer divide values: 2, 4, 6, etc.

• R Divisor = 2 x (Field + 1). For example, Field = 3 gives an R divisor of 8

• FSTEPW: DSPLL DCO step words (0x0423-0x0429, 0x0523-0x0529, 0x0623-0x0629, 0x0724-0x072A)

• Positive Integers, where FINC/FDEC select direction

•Min. value is 0, Max. value is 224

• 56-bit step size, relative to 32-bit M denominator

Si5397/96 Reference Manual

Functional Description

silabs.com | Building a more connected world. Rev. 0.9 | 9

3.1.2 DSPLL Loop Bandwidth

The DSPLL loop bandwidth determines the amount of input clock jitter attenuation and wander filtering. Register configurable DSPLL

loop bandwidth settings in the range of 0.1 Hz to 4 kHz are available for selection. The loop bandwidth is controlled digitally and re-

mains stable with less than 0.1 dB of peaking for the loop bandwidth selected. The DSPLL loop bandwidth is set in registers

0x0508-0x050D and are determined using ClockBuilder Pro.

The higher the PLL bandwidth is set relative to the phase detector frequency (fpfd), the more chance that fpfd will cause a spur in the

Phase Noise plot of the output clock and increase the output jitter. To guarantee the best phase noise/jitter it is recommended that the

normal PLL bandwidth be kept less than fpfd/160 although ratios of fpfd/100 will typically work fine.

Note: After changing the bandwidth parameters, the appropriate BW_UPDATE_PLLx bit (0x414, 0x514, 0x614, 0x714) must be set

high to latch the new values into operation. The update bits will latch both nominal and fastlock bandwidths.

Table 3.1. PLL Bandwidth Registers

Setting Name Hex Address [Bit Field] Function

Si5397 Si5396

BW_PLLA 0408[7:0] -

040D[7:0]

0408[7:0] -

040D[7:0]

This group of registers determine the loop bandwidth for

DSPLL A, B, C, D. They are all independently selectable

in the range from 0.1 Hz up to 4 kHz. Register values

determined by ClockBuilderPro.

BW_PLLB 0508[7:0] -

050D[7:0]

0508[7:0] -

050D[7:0]

BW_PLLC 0608[7:0] -

060D[7:0]

—

BW_PLLD 0709[7:0] -

070E[7:0]

—

Si5397/96 Reference Manual

Functional Description

silabs.com | Building a more connected world. Rev. 0.9 | 10

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