Shuttle HOT-565 Manuel utilisateur

HOT- 565 User's Manual 1

HOT-565

Pentium™processor

Based PCI MAIN BOARD

User's Manual

FCC Notice:

This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to Part 15 of

FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential

installation. This equipment generates, uses and can radiate radio frequency energy. If not installed and used properly, in

strict accordance with the manufacturer’s instructions, may cause harmful interference to radio communications.

However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause

interference to radio or television reception, which can be determined by turning the equipment off and on, the user is

encouraged to try to correct the interference by one or more of the following measures :

Reorient or relocate the receiving antenna.

Increase the separation between the equipment and receiver.

Connect the equipment into an outlet on a circuit different from that to which the receiver is connected.

Consult the dealer or an experienced radio/television technician for help and for additional suggestions.

The user may find the following booklet prepared by the Federal Communications Commission helpful “How to Identify

and Resolve Radio-TV Interference Problems.” This booklet is available from the U.S. Government Printing Office.

Washington, DC 20402, Stock 004-000-00345-4

FCC Warning

The user is cautioned that changes or modifications not expressly approved by the manufacturer could void the user’s

authority to operate this equipment.

Note : In order for an installation of this product to maintain compliance with the limits for a Class B device, shielded

cables and power cord must be used.

CE Notice:

Following standards were applied to this product, in order to achieve compliance with the electromagnetic compatibility :

- Immunity in accordance with EN 50082-1: 1992

- Emmitions in accordance with EN 55022: 1987 Class B.

NOTICE

Manual Ver 1.0

All information, documentation, and specifications contained in this manual are subject to change without prior

notification by the manufacturer.

The author assumes no responsibility for any errors or omissions which may appear in this document nor does it

make a commitment to update the information contained herein.

TRADEMARKS

Intel is a registered trademark of Intel Corporation

PentiumÔ Processor is a registered trademark of Intel Corporation

PC/AT is a registered trademark of International Business Machine Corporation.

PS/2 is a registered trademark of IBM Corporation.

All other brand and product names referred to in this manual are trademarks or registered trademarks of their

respective holders.

HOT- 565 User's Manual 3

TABLE OF CONTENTS

PREFACE ..................................................................................................4

CHAPTER 1 INTRODUCTION .......................................................................5

Specification................................................................................................5

CHAPTER 2 HARDWARE CONFIGURATION ..................................................7

HOT-565 Layout..........................................................................................7

Jumpers........................................................................................................8

CPU Clock Speed Selection - JP36, JP23, JP24 and JP42......................... 8

Onboard Regulators Output - J100, J101, J103 and JP43........................10

Flash EPROM Jumper - JP19....................................................................11

Clear CMOS - JP40....................................................................................11

Connectors & Sockets................................................................................12

CHAPTER 3 MEMORYCONFIGURATION ...................................................14

CHAPTER 4 AWARD BIOS SETUP ...........................................................16

The Main Menu..........................................................................................17

Standard CMOS Setup...............................................................................19

BIOS Features Setup..................................................................................21

Chipset Features Setup...............................................................................23

Power Management Setup..........................................................................26

PCI Configuration Setup............................................................................28

Integrated Peripherals................................................................................30

Password Setting........................................................................................32

HOT- 565 User's Manual 4

HOT-565 mainboard is a highly integrated IBM PC/AT compatible system

board. The design will accept Intel Pentium P54C, Pentium MMX, Cyrix/IBM

6x86/L and AMD K5/K6 processors and also features high-performance

pipelined burst secondary cache memory support with size of 512KB or

256KB. The memory subsystem is designed to support up to 256 MB of EDO

RAM, Standard Fast Page DRAM and SDRAM in standard 72-pin SIMM

socket and 168-pin 3.3 V DIMM socket.

HOT-565 provides a new level of I/O integration. Intel's 82430TX PCIset

chipset provides increased integration and improved performance over other

chipset designs. The 82430TX PCIset chipset provides an integrated Bus

Mastering IDE controller with two high performance Ultra 33 DMA IDE

interfaces for up to four IDE devices.

The onboard Giga I/O controller provides the standard PC I/O functions: floppy

interface, two FIFO serial ports, an IrDA device port and a SPP/EPP/ECP

capable parallel port.

Up to four PCI local bus slots provide a high bandwidth data path for data-

movement intensive functions such as graphics, and up to three ISA slots

complete the I/O function.

The HOT-565 provides the foundation for cost effective, high performance,

highly expandable platforms, which deliver the latest in Pentium processor and

I/O standard.

Preface

HOT- 565 User's Manual 5

Chapter1 Introduction

Specification

CPU Function

Pentium P54C/P55C-MMX™ processors : 75~233MHz

Cyrix/IBM 6x86/L processors : PR120~PR166

AMD K5/K6 processors : PR75~PR233

Chipset

Intel PCIset 82439TX and 82371AB

Memory

Supports two banks of EDO, Fast Page Mode DRAM or

3.3V Sync. DRAM ranging from 8MB to 256MB

Supports 4MB, 8MB, 16MB, 32MB and 64MB 72-pins

SIMMs or 8MB, 16MB, 32MB, 64MB and 128MB 168-pin

DIMMs

Cache Memory

Integrated L2 write-back cache controller

- 512KB or 256KB Direct Mapped Pipeline Burst Cache

Power Management Function

Provides four power management modes : Full on, Doze,

Standby, and Suspend

Supports Microsoft APM 1.2

Provides EPMI (External Power Management Interrupt) pin

HOT- 565 User's Manual 6

Expansions

32-bit PCI bus slot x 4

16-bit ISA bus slot x 3

2-channel PCI IDE port

- Support up to 4 IDE devices

- PIO Mode 4, DMA Mode 2 transfers up to 22 MB/sec

- Supports "Ultra 33" synchronous DMA mode transfer tup

to 33 Mbytes/sec

- Integrated 8 x 32-bit buffer for PCI IDE burst transfers

One floppy port

One parallel port

- SupportsSPP (PS/2 compatible bidirectional Parallel

Port), EPP (Enhanced Parallel Port), andECP (Extended

Capabilities Port) high performance parallel port.

Two serial ports

- Supports 16C550 compatible UARTS.

- Supports IrDA (Infrared) communication.

One PS/2 mouse port

Two USB (Universal Serial Bus) ports

System BIOS

Award PnP BIOS v4.51PG

Bundled with Symbios Login(NCR) SDCM V4.0 SCSI BIOS

Board Design

Dimension 220mm x 280mm

HOT- 565 User's Manual 7

Chapter2Hardware Configuration

HOT-565Layout

HOT- 565 User's Manual 8

Jumpers

CPU Clock Speed Selection - JP23, JP24 and JP42

HOT-565 mainboard features a clock generator to provide adjustable system

clock frequency. JP36 is a 6-pins jumper which determine the system clock

frequency from 50 MHz to 66 MHz.

HOT-565 mainboard also provides Jumpers JP23 and JP24 to figure the

CPU core clock multiplier. By inserting jumper caps on JP23 and JP24, the

user can change theHost Bus Clock/CPU Core Clock ratio from

1 : 1.5 to 1 : 3.5.

JP42 is reserved for AMD future processors.

Several hardware settings are made through the use of jumper caps to

connect jumper pins on the main board. The jumper's pin 1 on main board

will be on the top or on the left when holding the main board with the

keyboard connector away from yourself. Pinout numeric is written around

the jumpers with four or six pin jumpers. The jumpers will be show

graphically such as to connect pins 3&4 and 5&6, and

to connect pins 1&2 and 3&4 for six pin jumpers.

Jumpers will be show graphically such as to connect pins 2&4 and

to connect pins 3&4 for four pin jumpers.

Jumpers with two pins will be shown as for Short (On) and for

Open (Off).

To connect the pins, simply place a plastic jumper cap over the two pins as

diagramed.

HOT- 565 User's Manual 9

Processors JP36 System

Clock

/Multiplier

Frequency

Multiplier

JP23, JP24

PentiumMMX233 MHz

Pentium100 MHz

AMD-K6PR2-233

AMD-K5PR100/133

66 MHz

x 1.5 / x 3.5

Pentium/MMX200 MHz

AMD-K6PR2-200

AMD-K5PR200

66 MHz

x 3

Pentium/MMX166 MHz

AMD-K6PR2-166 MHz

AMD-K5PR166 MHz

66 MHz

x 2.5

Pentium/MMX150 MHz

AMD-K5PR150 60 MHz

x 2.5

Pentium133 MHz

Cyrix6x86/LP166+

IBM6x86/LP166+

66 MHz

x 2

Pentium120 MHz

Cyrix6x86 P150+

IBM6x86 P150+

60 MHz

x 2

Cyrix6x86 PR133+

IBM6x86 PR133+55 MHz

x 2

Cyrix6x86 P120+

IBM6x86 P120+50 MHz

x 2

Pentium90 MHz

AMD-K5PR90/120 60 MHz

x 1.5

Pentium75 MHz

AMD-K5PR75 50 MHz

x 1.5

CPU Clock Configuration

HOT- 565 User's Manual 10

OnboardRegulatorOutput- J100, J101,J103and JP43

These jumpers set the voltage supplied to the processor. Intel Pentium

processors has only a Single Power Plane and uses the standard 3.3V(STD),

AMD K5 and Cyrix/IBM 6x86 has also have a single power plane and use

3.52V. Currently Intel's new Pentium P55C MMX, AMD K6 and Cyrix/IBM

6x86L with dual power planes, Pentium P55C MMX and Cyrix/IBM 6x86L

requires 2.8V, AMD K6 PR166 and PR200 requires 2.9V; PR233 requires

3.2V.

JP43 is designed to fine tune VCORE

output from regulator. When the

jumper cap is removed from JP43, it

will increase VCORE voltage output

from regulator by 2.5%. Normally,

JP43 is set to close by insert a

jumper cap.

Processor Voltage

Output J103 J101 J100

AMD K5,

Cyrix/IBM 6x86 3.52 V

Pentium,

Cyrix/IBM 6x86 3.3 V

Processor Vcore

Output J103 J101 J100

Vio=3.3V

Pentium MMX,

Cyrix/IBM

6x86L 2.8 V

AMD K6

PR166/PR200 2.9 V

AMD K6

PR233 3.2 V

Single Power Plane (VIO=VCORE)

Dual Power Planes (VIO, VCORE separated)

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