Shiratech Solutions AT-501 Guide de configuration rapide

AT-501

Cortex-A5

System on Module

Integration guide

Revision 1.4

2 | AT-501 HW user manual 1.4

Contents

1 Scope..................................................................................................................................................... 4

1.1 SoM introduction ............................................................................................................................. 4

1.2 SoM models ..................................................................................................................................... 4

2 AT-501 Integration guide ...................................................................................................................... 6

2.1 Power connectivity .......................................................................................................................... 6

2.2 Reset ................................................................................................................................................ 8

2.3 Interfaces ......................................................................................................................................... 9

2.3.1 Ethernet ports ......................................................................................................................... 9

2.3.2 UART and USART ................................................................................................................... 10

2.3.3 USB ........................................................................................................................................ 12

2.3.4 High Speed Multi-Card Interface........................................................................................... 14

2.3.5 LCD and touch screen support .............................................................................................. 14

2.3.6 CAN........................................................................................................................................16

2.3.7 I2C.......................................................................................................................................... 16

2.3.8 SPI.......................................................................................................................................... 16

2.3.9 A to D Convertor ................................................................................................................... 16

2.3.10 JTAG .................................................................................................................................. 17

2.4 Mechanical considerations ............................................................................................................17

2.4.1 SO-DIMM connector .............................................................................................................19

2.5 Pin assignment............................................................................................................................... 19

2.5.1 SO-DIMM 200 Pins assignment............................................................................................. 19

2.5.2 Port A options........................................................................................................................ 26

2.5.3 Port B options........................................................................................................................ 27

2.5.4 Port C options........................................................................................................................ 28

2.5.5 Port D options .......................................................................................................................29

2.5.6 Port E options........................................................................................................................ 30

3 AT-501 System overview..................................................................................................................... 31

3.1 Cortex-A5 Processor ......................................................................................................................31

3.2 Memories.......................................................................................................................................31

3 | AT-501 HW user manual 1.4

Document Revision History

Revision

Date

Description

1.0

12.6.2013

Initial version

1.1

8.5.2014

Add D36, update USART capabilities.

1.2

1.6.2014

Add notes about OTG support; add details

about components height on the print side.

1.3

6.4.2015

Fix debug port pin out

1.4

26.8.2015

Add remarks about VBAT and Resistive touch

interfaces

4 | AT-501 HW user manual 1.4

1Scope

The purpose of this document is to provide a guide for integrating the AT-501 into the target hardware

in an easy and fast way so that the use of SoM will shorten and simplify the development process.

The guide is divided to two parts, the first one help you through the integration process, giving design

samples based on the design of the CB-20(schematics can be provided by Shiratech via

support@shiratech.com ) while the second part provide more details on the AT-501 system.

In order to simplify the integration process we recommend the following process:

1. Read through the integration guide on the required interfaces.

2. Use Shiratech’s Pin configuration tool to define the solution

3. Use the CB-20 as a reference design to shorten the development process.

For more details if needed review the SAMA5D3 user manual and access Shiratech at

support@shiratech.com

1.1 SoM introduction

The AT-501 is an industrial embedded System-On-Module (SoM) based on Atmel’s new SAMA5D3

Cortex-A5 system on chip. It offers the optimal balance of the most power efficient Cortex A processor

available to date with a high performance CPU running at 536 MHz and a floating point unit.

The AT-501 includes the processor and its entire environment, as well a 1Gbe physical layer chip. All the

interfaces of the processor are available for the user through a well-known 200 pins SO-DIMM form

factor.

1.2 SoM models

The SOM support the various variations of the SAMA5D3 –different assembly options. In case the SOM

uses the SAMA5D31 the 1Gbe physical interface is not assembled.

See the table below for the supported interface in each variation:

5 | AT-501 HW user manual 1.4

Figure 1 –Interface support on the various SAMA5D3 processors

6 | AT-501 HW user manual 1.4

2AT-501 Integration guide

The HW integration guide covers all the hardware issues related to the connecting the SoM to the target

device starting from power connectivity, connector details, pin-out options, description of the various

interfaces and provides reference design for most of the interfaces. By using the same design as the

reference board you can shorten the BSP development phase and reduce the option for mistakes. The

reference design is based on the CB-20. Schematics of the CB-20 can be provided by request. For more

details contact support@shiratech.com

2.1 Power connectivity

The AT-501 uses a single power input of 3.3V from which all the other required voltages are taken. The

3.3V input is only directly used for power the processor I/Os. The Inlet power should be

Rise time: <= 3ms

Input voltage range: 3.3V +/- 5%

Typical power consumption: 0.5W

Figure 2 –AT-501 internal power scheme

The AT-501 support low power modes, it can enter sleep mode by shutting down the main power source

leaving only a very small part active for possible wake up interrupt either internal or external.

For supporting these modes several additional lines are available:

VBAT –battery input for maintaining the RTC unit and Shutdown Controller within the processor. If not

used should be connected to 3.3V.

3.3 -> 1.8

3.3 -> 1.2

I/O

DDR

Core

PLL

3.3 V (2-3A)

1.8 -> 1.2

LDO

Battery

Optional

VBAT

Ferrit

3.3 -> 2.5

LDO

FUSE

7 | AT-501 HW user manual 1.4

Important:

VBAT must be high during power up for the processor to start working, so in case VBAT is connected to a

dedicated rechargeable battery or super cap, there must be a mechanism to provide the required

voltage during power up otherwise the processor will not start.

The AT-501 has an optional backup power source for the Real-Time-Clock. It can support an

approximately 1 hour of the RTC operation when the main power fails. The following figure describes

the AT-501 backup power. The backup power device, CBC3105, monitors the main power level and

when it drops below a configurable threshold it switch to its internal power source. During normal

operation the backup chip is recharge to its nominal power. In the basic ordering option the backup chip

is bypassed by a 0 ohm resistor. In this way an external power source can be connected to VBAT e.g.

high energy battery, to support longer backup time. For more details on that option contact

[email protected]m .

WKUP (Input –pin 10 in the SO-DIMM connector) –The Wake Up line is used to wake up the system

using an external trigger, if unused should be left open. An internal pull up is assembled on the SOM.

Level 0 on the WKUP pin triggers the processor to wake up.

SHDN (Output - pin 12 in the SO-DIMM connector) –This pin enable the SW to shut down the power

after entering the SW and processor to sleep mode. A typical application connects the pin SHDN to the

shutdown input of the DC/DC Converter providing the main power supplies of the system.

Level 1 (3.3V) = Enable, Level 0 (0V) = Shutdown.

Note: If this pin is used along with a battery connected to the VBAT signal then the signal should be

pulled up to VBAT and not to regular 3.3V. In that way the signal remain valid even when the main

power is down.

PWR_ENB (Input –pin 30 in the SO-DIMM connector) this pin can be used to shut down the DC2DC chip

on the SOM. Asserting this line during shut down will reduce the system power dissipation

Level 1 (3.3V)= Enable, Level 0 (0V) = disable)

ADVREF - this pin is used for the reference voltage of the A/D pins if not used should be connected to

3.3V.

8 | AT-501 HW user manual 1.4

Figure 3 –AT-501 Backup Power scheme

2.2 Reset

The NRESET signal is an open-drain interface. It generates a reset on POR or on a reset event generated

by the SW. It also can be used as an input to an external reset source like a push-button.

The generated reset signal can be used to reset the system chips. The following figure describes the AT-

501 Reset signal.

Figure 4 - Reset Generation

Atmel

SAMA5D

3.3 -> 1.8

3.3 -> 1.2

I/O

DDR

Core

CBC

3105 VBAT

SO-DIMM 200

3.3V

Shutdown WakeUp

VBAT

Inlet

PLLFilter

SAMA5D

MNRESET

3.3 V

Push-Button

NRESET

9 | AT-501 HW user manual 1.4

2.3 Interfaces

The AT-501 offers a large variety of interfaces over the 200 pins SO-DIMM connector. The following

paragraphs describe the available interfaces along with guidance on how to connect and to use them.

For more information, review the SAMA5D3 data sheet.

2.3.1 Ethernet ports

The AT-501 support 1 Giga Ethernet port and one fast Ethernet port depending on the type of processor

assembled.

Figure 5 - Giga Ethernet & Fast Ethernet Interfaces

2.3.1.1 Giga Ethernet port

The AT-501 includes a build in 1GE interface (including physical layer chip) in all it models except the one

which includes the SAMA5D31 which does not support GE.

The Physical layer chip is connected via MDC/MDIO interface using the default PHY address is 0001 for

both interfaces.

The Giga Ethernet uses an RGMII interface to interconnect to the processor. The figure 5 describes the

Giga Ethernet interface. On the carrier board only the magnetics and connector should be placed. The

Giga Ethernet signals pairs should be routed from the PHY to the magnetic as differential pairs using 100

ohm impedance.

For the GE port the following signals are used as well:

Interrupt - PB-25 of the SAMA5 uses as an interrupt input for the Giga Ethernet PHY.

LEDs - Two led signals from the GE PHY are also connected to the SOM edge connector.

LED1 –Blinking Activity.

LED2- Link, on when there is link.

SAM-A5

Micrel

ksz9031

Ethernet 0

RGMII

4 x TX

4 x RX

Controls

125 Mhz

25M

Int.

SO-DIMM 200

NReset

LEDS RJ45

MAG

LEDS

GE Analog

PHY

RMII 2 x TX

2 x RX

50 MHz

25M

MODULE A

RMII Analog

Control

Ethernet 1

10 | AT-501 HW user manual 1.4

The led are connected to the GE PHY through a 470 ohm serial resistor.

Note: In case of the SAMA5D31, the pins used for GE should be left unconnected.

Figure 6 - Giga Ethernet schematics

2.3.1.2 Ethernet port

The Fast Ethernet interface is available for the D36, D35 and SAMA5D31 only. For the fast Ethernet port

there is no internal physical layer chip so it should be placed on the carrier board. The processor can be

connected to the physical layer using the RMII interface of the processor. The RMII runs on 50 MHz clock

that need to be provided to the processor by an external source.

The RMII signals should be connected directly to the CPU i.e. no serial resistors. Routing these signals to

the FE PHY should be done according to the RMII standard for proper operation.

2.3.1.3 MDC/MDIO

The Giga Ethernet MDC/MDIO signals are NOT available on the edge connector since the physical layer

chip is built in. The Fast Ethernet MDC/MDIO signals are available, MDIO (PC9) on pin 174, MDC (PC8) on

pin 175.

The MDC frequency is derived from the system clock and should not exceed 2.5MHz.

2.3.2 UART and USART

There are up to four USART and two UART interfaces dependent on PIO utilization and processor type.

The following paragraph describes the various options.

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