Renesas HD151TS207SS Manuel utilisateur

Rev.1.00, Apr.25.2003, page 1 of 38

HD151TS207SS

Mother Board Clock Generator

for Intel P4+ Chipset (Springdale)

REJ03D0006-0100Z

Preliminary

Rev.1.00

Apr.25.2003

Description

The HD151TS207SS is Intel CK409T type high-performance, low-skew, low-jitter, PC motherboard clock

generator. It is specifically designed for Intel Pentium®4+ chipset.

Features

•3 differential pairs of current mode control CPU clocks

•1 differential pair of Serial Reference Clock (SRC), selectable 100 MHz/200 MHz

•6 copies PCI clocks and 3 copies PCIF clocks @3.3V, 33.3 MHz

•1 copy PCI clock @3.3 V, selectable 33.3 MHz/25 MHz

•1 copy USB clock @3.3 V, selectable 48 MHz/24 MHz

•1 copy DOT clock @3.3 V, 48 MHz

•4 copies of 3V66 clocks @3.3 V, 66.6 MHz

•1 copy of 3V66/VCH clock @3.3 V, selectable 66.6 MHz/48 MHz

•2 copies of REF clocks @3.3 V, 14.318 MHz

•Power save and clock stop function

•I2CTM serial port programming

•Programmable Clock Control (Spread Spectrum Percentage, Clock Output Skew, Slew Rate)

•Watchdog timer and reset output

•56pin SSOP (300 mils)

Note: I2C is a trademark of Philips Corporation.

Pentium is registered trademark of Intel Corporation

HD151TS207SS

Rev.1.00, Apr.25.2003, page 2 of 38

Key Specifications

•Supply Voltages: VDD = 3.3 V±5%

•CPU clock cycle to cycle jitter = |125ps| (SSC Disabled)

•CPU clock group Skew = 100ps

•3V66 clock group Skew = 250psmax

•PCI clock group Skew = 500psmax

HD151TS207SS

Rev.1.00, Apr.25.2003, page 3 of 38

Pin Arrangement

REF0

REF1

VDD_REF

XTAL_IN

XTAL_OUT

VSS_REF

FS2/PCIF_0

FS4/PCIF_1

VDD_PCI

VSS_PCI

PCI_1

MODE/PCI_0

PCI_2

PCI_3

VDD_PCI

VSS_PCI

SEL100_200/PCI_4

SEL33_25/PCI_5

PCI_6

PWRDWN#/SAFE_F#

3V66_0/RESET#

3V66_1

VDD_3V66

PCIF_2

24 33

VSS_48

VDD_48

VTT_PWRGD#

SRC#

SRC

CPU_1

CPU_0#

CPU_0

VSS_CPU

CPU_2

VDD_CPU

PCI_STOP#

VSS_SRC

TEST_CLK#

FS_A

IREF

VSS_A

FS_B

VDD_A

VDD_SRC

VSS_3V66

3V66_2

3V66_3

SCLK

28 29

SEL66_48/3V66_4/VCH

SDATA

SEL48_24/USB_48

FS3/DOT_48

VDD_CPU

CPU_1#

CPU_2#

VSS_IREF

(Top view)

PCI_STOP#, PWRDWN# = 150 kΩInternal Pull-up

HD151TS207SS

Rev.1.00, Apr.25.2003, page 4 of 38

Pin Descriptions

Pin name No. Type Description

VSS_A 54 Ground for PLL

VSS_CPU 45 Ground for outputs

VSS_IREF 53 Ground for current reference

VSS_SRC 39

VSS_3V66 25

VSS_PCI 11, 17

VSS_REF 6

VSS_48 33

Ground

Ground for outputs

VDD_A 55 3.3 V Power Supply for PLL

VDD_CPU 42, 48

VDD_SRC 36

VDD_3V66 24

VDD_PCI 10, 16

VDD_REF 3

VDD_48 34

Power

3.3 V Power Supply for outputs

REF0 1

REF1 2

OUTPUT 3.3 V 14.318 MHz reference clock.

XTAL_IN 4 INPUT 14.318 MHz XTAL input.

XTAL_OUT 5 OUTPUT 14.318 MHz XTAL output.

Don’t connect when an external clock is applied at XTAL_IN.

FS2/PCIF_[0:1] 7,8 INPUT/

OUTPUT Frequency select latch input pin.

/Free running PCI clock 3.3 V output.

PCIF_2 9 OUTPUT Free running PCI clock 3.3 V output.

**MODE/PCI_0 12 INPUT/

OUTPUT Function select latch input pin for pin 22,

1 = Reset#, 0 = clock output.

/PCI clock 3.3 V output.

PCI_[1:3] 13,14,

15 OUTPUT PCI clock 3.3 V outputs.

**SEL100_200/

PCI_4 18 INPUT/

OUTPUT Latched select input for SRC output.

1 = 200 MHz, 0 = 100 MHz

/PCI clock 3.3 V output.

**SEL33_25/PCI_5 19 INPUT/

OUTPUT Latched select input for PCI5 output.

1 = 25 MHz, 0 = 33 MHz

/PCI clock 3.3 V output.

PCI_6 20 OUTPUT PCI clock 3.3 V outputs.

Note: (*): Those pins are 150 kΩinternal pulled-UP.

(**): Those pins are 150 kΩinternal pulled-DOWN.

HD151TS207SS

Rev.1.00, Apr.25.2003, page 5 of 38

Pin Descriptions (cont.)

Pin name No. Type Description

PWRDWN#/

SAFE_F# 21 INPUT

PULL–UP* PWRDWN# / SAFE_F# selectable input.

Default is PWRDWN# input.

Byte15[5] = “1” : SAFE_F# input.

PWRDWN# is all clocks stop pin.

Asynchronous active “Low” input.

When asserted low, all output clocks are disabled.

SAFE_F# is active “Low” input.

When SAFE_F# is “Low” ,frequency mode is changed to the

predefined frequency mode.

3V66_0/RESET# 22 OUTPUT 3V66 / Watchdog RESET# selectable output.

Default is 3V66 output.

This signal is active low and selected by Mode latch input.

3V66_[1:3] 23,26,

27 OUTPUT 3V66 clock 3.3V outputs.

SCLK 28 INPUT

PULL-UP* Clock input for I2C logic.

**SEL66_48/

3V66_4/VCH 29 INPUT/

OUTPUT Latched select input for 3V66/VCH output 1 = 48 MHz,

0 = 66.66 MHz. /3V66 or VCH clock output.

SDATA 30 IN/OUTPUT

PULL-UP* Data input for I2C logic.

**SEL48_24/

USB_48 31 INPUT/

OUTPUT Latched select input for 48_24 MHz output

1 = 24 MHz, 0 = 48 MHz / 24_48 MHz clock 3.3 V output.

FS3/DOT_48 32 INPUT/

OUTPUT Frequency select latch input pin.

/DOT_48 clock 3.3 V output.

VTT_PWRGD# 35 INPUT

PULL-UP* Qualifying input that latches FS_A and FS_B.

When asserted low, FS_A and FS_B are latched.

SRC# 37 OUTPUT “Complementary” clock of Differential Serial Reference Clock.

SRC 38 OUTPUT “True” clock of Differential Serial Reference Clock.

CPU_[0:2]# 40,43,

46 OUTPUT “Complementary” clock of differential CPU clock.

CPU_[0:2] 41,44,

47 OUTPUT “True” clock of differential CPU clock.

PCI_STOP# 49 INPUT

PULL–UP* PCI clocks stop pin. Active “Low” input.

When asserted low, PCI[6:0] and SRC clocks are

synchronously disabled in low state.

Usually this pin does not give to effect PCIF[2:0] clock outputs.

TEST_CLK# 50 INPUT

PULL-UP* Test clock mode pin. Active “Low” input.

FS_[A:B] 51,52 INPUT CPU clocks frequency select latch input.

IREF 52 INPUT A precision resistor is attached to this pin which is connected

to internal current reference.

A resistor is connected between this pin and GNDIREF.

Note: (*): Those pins are 150 kΩinternal pulled-UP.

(**): Those pins are 150 kΩinternal pulled-DOWN

HD151TS207SS

Rev.1.00, Apr.25.2003, page 6 of 38

Block Diagram

3V66[3:1]

1/M2

SSC2

1/N2

1/M1

SSC1

1/N1

1/M0

1/N0

OSC

CK2

CK1

CK0

XTAL

14.318 MHz

REF[1:0]

(14.318MHz)

CPU[2:0]

CPU[2:0]#

* : Latched Input pin.

3.3 V VDD_48 3.3 V VDD_AVSS_48 VSS_A 6×3.3V VDD 6×VSS VSS_IREF IREF

PCI[6:0]

SRC#

SRC

*SEL48_24

*FS_4/3/2A/B

*SEL33_25

*MODE

TEST_CLK#

*SEL66_48

*SEL100_200

VTT_PWRGD#

PWRDWN#/SAFE_F#

PCI_STOP#

SCLK

SDATA

Input

Clock

Select

PLL2

For

CPU

USB

PLL

PLL1

For

SRC

3V66

PCI

PCIF[2:0]

3V66_0/RESET#

3V66_4/VCH

USB_48

DOT_48

Control Logic

VCO0

VCO1

VCO2

Clock

Divider

Clock

Select

Delay

Control

Stop

Control

HD151TS207SS

Rev.1.00, Apr.25.2003, page 7 of 38

I2C Controlled Register Bit Map

Byte0 Control Register

Bit Description Contents Type Default Note

7 Reserved R 0

6 Reserved R 0

5 Reserved R 0

4 Reserved R 0

3 PCI_Stop Reflects the current value

of the external PCI_STOP# pin 0 = PCI_STOP# pin is Low

1 = PCI_STOP# pin is High RX

2 Reserved R X

1 FS_B Reflects the value of the

FS_B pin sampled on power up 0 = FS_B Low at power up

1 = FS_B High at power up RX

0 FS_A Reflects the value of the

FS_A pin sampled on power up 0 = FS_A Low at power up

1 = FS_A High at power up RX

See

Table

Table1 Clock Frequency Function Table

Byte6

Bit5 FS_A FS_B CPU

[MHz] SRC

[MHz] 3V66

[MHz] PCIF

PCI

[MHz]

REF0

REF1

[MHz]

USB

DOT

[MHz]

Note

0 0 0 100 100/200 66 33 14.318 48

0 0 1 200 100/200 66 33 14.318 48

0 1 0 133 100/200 66 33 14.318 48

0 1 1 166 100/200 66 33 14.318 48

1 0 0 200 100/200 66 33 14.318 48

1 0 1 400 100/200 66 33 14.318 48

1 1 0 266 100/200 66 33 14.318 48

1 1 1 333 100/200 66 33 14.318 48

Table2 Test Clock select table

TEST_CLK# CPU

[MHz] SRC

[MHz] 3V66

[MHz] PCIF

PCI

[MHz]

REF0

REF1

[MHz]

USB

DOT

[MHz]

Note

1 REF/2 REF/2 REF/4 REF/8 REF REF/2

0 Hi–Z Hi–Z Hi–Z Hi–Z Hi–Z Hi–Z

See Note1,

Table3

Note: 1. REF is a clock over driven on the XIN during test mode.

HD151TS207SS

Rev.1.00, Apr.25.2003, page 8 of 38

I2C Controlled Register Bit Map (cont.)

Table3 FS_A and FS_B pin Input level

Logic Level Min Voltage Max Voltage

0 (Low) 0.35V

1 (High) 0.70V 

Byte1 Control Register

Bit Description Contents Type Default Note

7 Allow control of SCR with assertion

of PCI_STOP# 0 = Free running

1 = Stopped with

PCI_STOP#

RW 0 See

Table5

6 SRC Output enable 0 = Disabled (tristate)

1 = Enabled RW 1

5 Reserved RW 1

4 Reserved RW 1

3 Reserved RW 1

2 CPU2 Output enable 0 = Disabled (tristate)

1 = Enabled RW 1

1 CPU1 Output enable 0 = Disabled (tristate)

1 = Enabled RW 1

0 CPU0 Output enable 0 = Disabled (tristate)

1 = Enabled RW 1

Byte2 Control Register

Bit Description Contents Type Default Note

7 SRC_Pwrdwn drive mode 0 = Driven in power down,

1 = Tristate RW 0

6 SRC_Stop drive mode 0 = Driven when stopped,

1 = Tristate RW 0

See

Table5

5 CPU2_Pwrdwn drive mode 0 = Driven in power down,

1 = Tristate RW 0

4 CPU1_Pwrdwn drive mode 0 = Driven in power down,

1 = Tristate RW 0

3 CPU0_Pwrdwn drive mode 0 = Driven in power down,

1 = Tristate RW 0

2 Reserved RW 0

1 Reserved RW 0

0 Reserved RW 0

See

Table4

HD151TS207SS

Rev.1.00, Apr.25.2003, page 9 of 38

I2C Controlled Register Bit Map (cont.)

Table4 CPU Clock Power Management Truth Table

Signal Pin

PWRDWN# PWRDWN#

Tristate Bit

Byte2[5:3]

Non-Stop

Outputs

Byte1[5:3] = 1

Note

CPU[2:0] 1 X Running

CPU[2:0] 0 0 Driven @ Iref x2 See Note1

CPU[2:0] 0 1 Tristate

Note: 1. Iref = VDD/(3Rr) = 3.3/(3x475) = 2.32 mA,

Iref x2 = 4.6 mA (Voh @Z: 0.23 V @50 Ω)

Table5 SRC Clock Power Management Truth Table

Signal Pin

PWRDWN# Pin

PCI_STOP# PCI_STOP#

Tristate Bit

Byte2[6]

PWRDWN#

Tristate Bit

Byte2[7]

Non-Stop

Outputs

Byte1[7] = 1

Stoppable

Outputs

Byte1[7] = 0

Note

SRC 1 1 X X Running Running

SRC100XRunningDriven@

Iref x6 See Note1

SRC101XRunningTristate

SRC 0 X X 0 Driven @

Iref x2 Driven @

Iref x2 See Note1

SRC 0 X X 1 Tristate Tristate

Note: 1. Iref = VDD/(3Rr) = 3.3/(3x475) = 2.32 mA

Iref x6 = 13.9 mA (Voh @Z: 0.7 V @50 Ω)

Iref x2 = 4.6 mA (Voh @Z: 0.23 V @50 Ω)

Byte3 Control Register

Bit Description Contents Type Default Note

7 PCI_Stop control 0 = Enabled, all stoppable PCI

and SRC clocks are stopped.

1 = Disabled

RW 1

6 PCI_6 Output enable 0 = Disabled, 1 = Enabled RW 1

5 PCI_5 Output enable 0 = Disabled, 1 = Enabled RW 1

4 PCI_4 Output enable 0 = Disabled, 1 = Enabled RW 1

3 PCI_3 Output enable 0 = Disabled, 1 = Enabled RW 1

2 PCI_2 Output enable 0 = Disabled, 1 = Enabled RW 1

1 PCI_1 Output enable 0 = Disabled, 1 = Enabled RW 1

0 PCI_0 Output enable 0 = Disabled, 1 = Enabled RW 1

HD151TS207SS

Rev.1.00, Apr.25.2003, page 10 of 38

I2C Controlled Register Bit Map (cont.)

Byte4 Control Register

Bit Description Contents Type Default Note

7 USB_48 2x output drive 0 = 2x Drive strength,

1 = Normal RW 0

6 USB_48MHz Output Enable 0 = Disabled,

1 = Enabled RW 1

5 Allow control of PCIF_2 with

assertion of PCI_STOP# 0 = Free Running

1 = Stopped with PCI_STOP# RW 0

4 Allow control of PCIF_1 with

assertion of PCI_STOP# 0 = Free Running

1 = Stopped with PCI_STOP# RW 0

3 Allow control of PCIF_0 with

assertion of PCI_STOP# 0 = Free Running

1 = Stopped with PCI_STOP# RW 0

2 PCIF_2 Output enable 0 = Disabled, 1 = Enabled RW 1

1 PCIF_1 Output enable 0 = Disabled, 1 = Enabled RW 1

0 PCIF_0 Output enable 0 = Disabled, 1 = Enabled RW 1

Byte5 Control Register

Bit Description Contents Type Default Note

7 DOT_48MHz Output Enable 0 = Disabled, 1 = Enabled RW 1

6 Reserved RW 1

5 VCH Select 66MHz / 48MHz 0 = 3V66 mode

1 = VCH (48 MHz) mode RW 0

4 3V66_4/VCH Output Enable 0 = Disabled (tristate),

1 = Enabled RW 1

3 3V66_3 Output Enable 0 = Disabled, 1 = Enabled RW 1

2 3V66_2 Output Enable 0 = Disabled, 1 = Enabled RW 1

1 3V66_1 Output Enable 0 = Disabled, 1 = Enabled RW 1

0 3V66_0 Output Enable 0 = Disabled, 1 = Enabled RW 1

Byte6 Control Register

Bit Description Contents Type Default Note

7 Test Clock Mode 0 = Disabled, 1 = Enabled RW 0

6 Reserved RW 0

5 FS_A & FS_B Operation 0 = Normal, 1 = Test mode RW 0

4 SRC Frequency Select 0 = 100MHz, 1 = 200 MHz RW 0

3 Reserved RW 0

2 Spread Spectrum Mode 0 = Spread OFF

1 = Spread ON RW 0 See

B9[7:6]

1 REF1 Output Enable 0 = Disabled, 1 = Enabled RW 1

0 REF0 Output Enable 0 = Disabled, 1 = Enabled RW 1

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