Microchip Technology VSC8211 Manuel utilisateur

 2022 Microchip Technology Inc. and its subsidiaries DS00004531A-page 1

1.0 INTRODUCTION

This document provides a hardware design checklist for the Microchip VSC8211 product family. It is meant to help cus-

tomers achieve first-pass design success. These checklist items should be followed when utilizing the VSC8211 in a

new design. A summary of these items is provided in Section 11.0, "Hardware Checklist Summary". Detailed information

on these subjects can be found in the corresponding sections:

•Section 2.0, "General Considerations"

•Section 3.0, "Power"

•Section 4.0, "Twisted Pair Media Interface (CAT5)"

•Section 5.0, "SGMII/SerDes MAC Interface"

•Section 6.0, "Parallel MAC Interface"

•Section 7.0, "Device Clocks"

•Section 8.0, "Hardware Configuration Using CMODE Pins"

•Section 9.0, "Digital Interface"

•Section 10.0, "Miscellaneous"

2.0 GENERAL CONSIDERATIONS

2.1 Required References

The VSC8211 implementor should have the following documents on hand:

•VSC8211 Single-Port 10/100/1000BASE-T, 1000BASE-X, and 100BASE-FX PHY Data Sheet

• Device documents on the VSC8211 product page at www.microchip.com

• VSC8211EV EVB schematics and PCB information in the VSC8211 Evaluation Board User Guide as well as

VSC8211 PCB design and layout guidelines at www.microchip.com.

2.2 Pin Check

• Check the pinout of the part against the data sheet. Ensure that all pins match the data sheet and are configured

as inputs, outputs, or bidirectional for error checking.

2.3 Ground

• A single ground reference as a system ground is used for all ground pins. Use one continuous ground plane to

ensure a low-impedance ground path and a continuous ground reference for all signals.

• A chassis ground is necessary between the magnetics and RJ45 connector at line side for better EMI and ESD.

VSC8211

Hardware Design Checklist

VSC8211

DS00004531A-page 2  2022 Microchip Technology Inc.and its subsidiaries

3.0 POWER

Table 3-1 shows the power supply pins for the VSC8211.

TABLE 3-1: POWER SUPPLY PINS

Pin Name 117 LBGA

Ball

Voltage

(V) Descriptions Associated Functional Pins

Digital I/O Power Pins

VDDIOMAC C6, C3, D3 3.3V or

2.5V

Power for the parallel

MAC interface

RXLOS/SIGDET, RXD7:0], RXDV, RXER,

RXCLK, COL, CRS, TXCLK, TXER, GTX-

CLK, TXEN, TXD [7:0], MODDEF0/CLK-

OUTMAC

VDDIOMICRO G7 3.3V or

2.5V

3.3V or 2.5V,

Power for SMI,

EEPROM interface and

CLKOUTMICRO clock

EECLK/PLLMODE, EEDAT, TXDIS/,

SRESET, MDINT, MODDEF1/MDC, MODD-

EF2/MDIO, CLKOUTMICRO/OSCDIS

VDDIOCTRL D10 3.3V or

2.5V

Power for JTAG I/O RESET, TDO, TDI, TMS, TCK, TRST,

Digital Core Power Pins

VDD12 C10, C11, F3,

F4, G3

1.2V Power for internal digi-

tal logic, and SerDes/

SGMII I/O power

RDP, RDN, TDP, TDN, SCLKP, SCLKN,

SDIN, SDIP, SDOP, SDON

Analog Power Pins

VDD33A F10, G10, G9,

3.3V Power for MDI,

CMODE, PLL, and LED

blocks. For analog core

power, use ferrite bead.

LED [4:0], CMODE7:0], TXVND, TXVPD,

TXVNC, TXVPC, TXVNB, TXVPB, TXVNA,

TXVPAXTAL2, XTAL1/REFCLK, REF-

FILT, REFREXT

VDD12A H7 1.2V Power of PLL and ADC

blocks. For analog core

power, use ferrite bead.

—

Ground Pins

VSS C5, D4, D5,

D6, D7, D8,

D9, E4, E5,

E6, E7, E8,

E9, E10, F5,

F6, F7, F8,

F9, J7, H9,

J9, H11, J11

0V Ground for all blocks —

 2022 Microchip Technology Inc. and its subsidiaries DS00004531A-page 3

VSC8211

3.1 Current and Power Requirements

• Ensure that the voltage regulators and power distribution are designed to adequately support these current

requirements for each power rail. Refer to Table 3-2 for different system configurations. Note that the power dissi-

pation values in the table need 25% to 30% based on the maximum current for the power supply designs of 3.3V,

1.2V, and 2.5V. Designs with 100Base-FX need an additional margin of 35% to 50% based on the typical current

for the power supply designs of 3.3V and 1.2V. See Table 3-3 for details.

TABLE 3-2: MAXIMUM RAIL CURRENT

Power Rail Voltage (V) Maximum Current (mA) Power Dissipation (mW)

VDDIO at 3.3V, RGMII-CAT5, 1000BASE-T, FD, 1518 Byte Random Data Packet, 100% Utilization, SFP Mode Off

VDD33A 3.3 110 363

VDDIOMAC, VDDIOMI-

CRO,

VDDIOCTRL

3.3 53 175

VDD12 1.2 324 389

VDD12A 1.2 38 46

VDDIO at 2.5V, RGMII-CAT5, 1000BASE-T, FD, 1518 Byte Random Data Packet, 100% Utilization, SFP Mode Off

VDD33A 3.3 110 363

VDDIOMAC,

VDDIOMICRO,

VDDIOCTRL

2.5 41 103

VDD12 1.2 324 389

VDD12A 1.2 38 46

VDDIO at 3.3 V, RGMII-CAT5, 100BASE-TX, FD, 1518 Byte Random Data Packet, 100% Utilization, SFP Mode Off

VDD33A 3.3 91.5 303

VDDIOMAC, VDDIOMI-

CRO,

VDDIOCTRL

3.3 19 63

VDD12 1.2 103 124

VDD12A 1.2 26.5 32

VDDIO at 2.5 V, RGMII-CAT5, 100BASE-TX, FD, 1518 Byte Random Data Packet, 100% Utilization, SFP Mode Off

VDD33A 3.3 91.5 303

VDDIOMAC,

VDDIOMICRO,

VDDIOCTRL

2.5 15 38

VDD12 1.2 103 124

VDD12A 1.2 26.5 32

VDDIO at 3.3 V, RGMII-CAT5, 10BASE-T, FD, 1518 Byte Random Data Packet, 100% Utilization, SFP Mode Off

VDD33A 3.3 152 502

VDDIOMAC,

VDDIOMICRO,

VDDIOCTRL

3.3 14 46

VDD12 1.2 31 37

VDD12A 1.2 27 32

VDDIO at 2.5 V, RGMII-CAT5, 10BASE-T, FD, 1518 Byte Random Data Packet, 100% Utilization, SFP Mode Off

VDD33A 3.3 152 502

VDDIOMAC,

VDDIOMICRO,

VDDIOCTRL

2.5 11 28

VSC8211

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VDD12 1.2 31 37

VDD12A 1.2 27 32

VDDIO at 3.3 V, RGMII-Fiber, 1000BASE-X, FD, 1518 Byte Random Data Packet, 100% Utilization, SFP Mode Off

VDD33A 3.3 20 66

VDDIOMAC,

VDDIOMICRO,

VDDIOCTRL

3.3 53 175

VDD12 1.2 56.5 68

VDD12A 1.2 23 28

VDDIO at 2.5 V, RGMII-Fiber, 1000BASE-X, FD, 1518 Byte Random Data Packet, 100% Utilization, SFP Mode Off

VDD33A 3.3 20 66

VDDIOMAC,

VDDIOMICRO,

VDDIOCTRL

2.5 42 105

VDD12 1.2 56.5 68

VDD12A 1.2 23 28

VDDIO at 3.3 V, SerDes-CAT5, 1000BASE-T, FD, 1518 Byte Random Data Packet, 100% Utilization, SFP Mode Off

VDD33A 3.3 112 370

VDDIOMAC,

VDDIOMICRO,

VDDIOCTRL

3.3 14 46

VDD12 1.2 343 412

VDD12A 1.2 37 44

VDDIO at 2.5 V, SerDes-CAT5, 1000BASE-T, FD, 1518 Byte Random Data Packet, 100% Utilization, SFP Mode Off

VDD33A 3.3 112 370

VDDIOMAC,

VDDIOMICRO,

VDDIOCTRL

2.5 10 33

VDD12 1.2 343 412

VDD12A 1.2 37 44

VDDIO at 3.3 V, SerDes-CAT5, 1000BASE-T, FD, 1518 Byte Random Data Packet, 100% Utilization, SFP Mode On

VDD33A 3.3 112 370

VDDIOMAC,

VDDIOMICRO,

VDDIOCTRL

3.3 14 46

VDD12 1.2 283 340

VDD12A 1.2 37 44

TABLE 3-2: MAXIMUM RAIL CURRENT

Power Rail Voltage (V) Maximum Current (mA) Power Dissipation (mW)

 2022 Microchip Technology Inc. and its subsidiaries DS00004531A-page 5

VSC8211

3.2 Power Supply Planes

• The VSC8211 requires two power rails of 3.3V and 1.2V or three power rails of VDDIO 2.5V, 3.3V, and 1.2V. The fil-

tered analog 1.2V and 3.3V supplies should not be shorted to any other digital supply at the package or PCB level.

See Section 3.3, "Power Circuit Connection and Analog Power Plane Filtering".

• The most important PCB design and layout considerations are as follows:

- Ensure that the return plane is adjacent to the power plane (without a signal layer in between).

- Ensure that a single plane is used for voltage reference with splits for individual voltage rails within that plane.

Try to maximize the area of each power split on the power plane based on corresponding via coordinates for

each rail to maximize coupling between each voltage rail and the return plane.

- Minimize resistive drop while efficiently conducting away heat from the device using 1 oz copper cladding.

• Four-layer PCBs with only one designated power plane must adhere to proper design techniques to prevent ran-

dom system events, such as CRC errors. Each power supply requires the lowest resistive drop possible to power

the pins of the device with correctly positioned local decoupling. For more information, see Section 3.4, "Bulk

Decoupling Capacitors".

• Ferrite beads should be used over a series inductor filter whenever possible, particularly for high-density or high-

power devices.

3.3 Power Circuit Connection and Analog Power Plane Filtering

• The analog power supplies are:

- VDD33A

- VDD12A

• A ferrite bead should be used to isolate each analog supply from the rest of the board. The bead should be placed

in series between the bulk decoupling capacitors and local decoupling capacitors.

• Because all PCB designs yield unique noise coupling behavior, not all ferrite beads or decoupling capacitors may

be needed for every design. It is recommended that system designers provide an option to replace the ferrite

beads with 0Ω resistors once a thorough evaluation of system performance is completed.

• Ferrite beads are not recommended for digital supplies VDDIOMAC, VDDIOMICRO, VDDIOCTRL, and VDD12.

The power and ground connections are shown in Figure 3-1.

TABLE 3-3: TYPICAL RAIL CURRENTS FOR DESIGN WITH 100BASE-FX

Power Rail Voltage (V) Typical Current (mA) Power Dissipation (mW)

VDDIO at 3.3V, RGMII-100BASE-FX, FDX, 1518 Byte Random Data Packet, 100% Utilization, SFP Mode Off

VDD33A 3.3 96 317

VDDIOMAC,

VDDIOMICRO,

VDDIOCTRL

3.3 19 63

VDD12 + VDD12A 1.2 145 174

VSC8211

DS00004531A-page 6  2022 Microchip Technology Inc.and its subsidiaries

3.4 Bulk Decoupling Capacitors

• Bulk decoupling capacitors can be placed at any convenient position on the board. Local decoupling capacitors

should be X5R or X7R ceramic and placed as close as possible to the VSC8211's power pins.

• Make sure that enough bulk capacitors (1 µF to 22 µF) are incorporated in each power rail of the power supply.

• If the VSC8211 device is on the top layer of the printed circuit board (PCB), the best location for local decoupling

capacitors is on the bottom or underside of the PCB, directly under the device.

FIGURE 3-1: POWER SUPPLY CONNECTIONS AND LOCAL FILTERING

VSC8211

VDD33A

VSS

VDD12A

Ferrite

Bead

1.2V

0.1µF

1µF

10µF

Ferrite

Bead

3.3V

VDDMAC

4 pins

1µF 1µF

F10,G10,G9, G8 H7

C5, D4, D5, D6, D7,

D8, D9, E4, E5, E6,

E7, E8, E9, E10, F5,

F6, F7, F8, F9, J7,

H9, J9, H11, J11

VDD12

5 X 0.1µF

1.2V

5 pins

C10, C11,

F3, F4, G3

24 pins

4 X 0.1µF

3.3V or 2.5V

3 X 0.1µF

VDDIOMICRO

VDDIOCTRL

0.1µF

C6, C3, D3

D10

1µF

3 pins

 2022 Microchip Technology Inc. and its subsidiaries DS00004531A-page 7

VSC8211

4.0 TWISTED PAIR MEDIA INTERFACE (CAT5)

4.1 10/100/1000 Mbps Interface Connection

The VSC8211 has one GPHY that supports 10/100/1000Base-T Ethernet Gigabit port. Details on the pin numbers for

this GPHY are described as follows:

•TXVNA (J12): This pin is the transmit/receive negative connection from Pair A of the internal GPHY. This pin con-