Linear Technology DC1682B Guide de configuration rapide

dc1840bfc

DEMO MANUAL DC1840B

Description

DC1682B and DC1680A

LTC4270/LTC4271

12-Port PSE with Digital Isolation

Demonstration kit DC1840B is a 12-port Type 2 power

sourcing equipment (PSE) composed of a DC1682B

daughter card and DC1680A mother board. The kit is

used for evaluation of the LTC4270B and LTC4271 PSE

chipset. Up to 12 powered devices (PDs) can be con-

nectedandpoweredfromthissystemusingasinglepower

supply. A DC590B is connected to the DC1840B for I2C

interfacing with QuikEval™. This demonstration manual

provides a Quick Start Procedure, a DC1682 overview,

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and

QuikEval is a trademark of Linear Technology Corporation. All other trademarks are the property

of their respective owners.

BoarD photo

a DC1680 overview, schematics, and layout printouts.

Other available supporting documents for the DC1840

are the LTC4270/LTC4271 Layout Guide and the LTC4271

PSE Demo Software Users Manual.

Design files for this circuit board are available at

http://www.linear.com/demo

dc1840bfc

DEMO MANUAL DC1840B

Quick start proceDure

Demonstration kit DC1840B includes the DC1682

daughter card and DC1680 mother board. The kit is set

up for evaluating the LTC4270/LTC4271. Follow the pro-

cedure below and refer to Figures 1 through 4 for proper

equipment setup.

1. On the DC1682 set AUTO jumper JP1 to HI (Figure 1)

to enable AUTO pin mode.

2. On the DC1682 set MID jumper JP2 to LO (Figure 1)

to disable midspan mode.

3. Align pin 1 of the 34-pin male connector on the DC1682

with pin 1 of the 34-pin female connector on the

DC1680 (Figure 2). Pin 12 is polarized to assist with the

alignment. Carefully push the DC1682 straight down

untilthetwo34-pinconnectorsareflushwitheachother.

4. On the DC1680, connect a supply with the positive

rail to POS and negative rail to NEG (Figure 3). Use a

power supply capable of sourcing the maximum load

expected(12ports×850mA≥10.2A). Rampthesupply

up to 55V.

5. Connect up to 12 PDs to the DC1680, J4 (Figure 3).

6. The DC590 is optionally connected to the DC1680 con-

nector J5 with a 14-pin ribbon cable (Figure 3). A GUI

for the LTC4270/LTC4271 is brought up by QuikEval for

I2C interfacing from a PC (Figure 4).

dc1840bfc

DEMO MANUAL DC1840B

Quick start proceDure

Figure 1. DC1682 Backside. Setting AUTO and MID Jumpers

Figure 2. Inserting the DC1682 into J1 of the DC1680

dc1840bfc

DEMO MANUAL DC1840B

Quick start proceDure

Figure 3. DC1840 Basic Setup

Figure 4. System Setup with the DC590, DC1680, DC1682 and 55V Power Supply

dc1840bfc

DEMO MANUAL DC1840B

Demonstration circuit 1682B operation

Figure 5. DC1682A 12-Port PSE Daughter Card with Digital Isolation Features the LTC4270 and LTC4271

12-Port PSE Daughter Card with Digital Isolation

Demonstration circuit 1682B (Figure 5) features the

LTC4270/LTC4271 chipset on a compact daughter card

with digital isolation. The LTC4270/LTC4271 chipset is

a 12-port power sourcing equipment (PSE) controller

designed for use in IEEE 802.3at Type 1 and Type 2 (high

power) compliant Power over Ethernet (PoE) systems. A

transformer isolated communication protocol replaces

expensiveopto-couplersandcomplexisolated3.3Vsupply

resulting in significant BOM cost savings. The LTC4270/

LTC4271 chipset delivers lowest-in-industry heat dissipa-

tionbyutilizinglowRON externalMOSFETsand0.25Ωsense

resistors, eliminating the need for expensive heat sinks.

Advanced power management features in the LTC4270/

LTC4271 chipset include: per port 12-bit current monitor-

ing ADCs, DAC programmable current limit, and versatile

quick shutdown of preselected ports. PD discovery uses a

proprietarydualmode4-pointdetectionmechanismensur-

ing excellent immunity from false PD detection. Midspan

PSEs are supported with 2-event classification and a two

second backoff timer. The LTC4270/LTC4271 includes an

I2C serial interface operable up to 1MHz.

The DC1682B demonstrates proper LTC4270/LTC4271

board layout that is approximately the height and width

of a 2 × 6 RJ45 connector. The compact layout is made

possiblebythesmallpackagesizeofkeycomponents.The

LTC4270 is in a 7mm × 8mm QFN, while the LTC4271 is in

a 4mm × 4mm QFN. Each port has a FDMC3612 MOSFET

in a 3mm × 3mm power33 package.

The daughter card inserts in the DC1680B mother board

through J1, a polarized 34-pin connector. Isolated 3.3V

and logic control signals are brought in on this connec-

tor. Also connected at J1 is the PoE VEE supply from the

mother board and 12 PSE controlled outputs.

dc1840bfc

DEMO MANUAL DC1840B

Demonstration circuit 1682B operation

Board Layout

ProperboardlayoutiscrucialforproperLTC4270/LTC4271

chipset operation, robustness, and accuracy. When lay-

ing out, pay attention to parts placement, Kelvin sensing,

power paths, and copper fill. It is imperative to follow the

LTC4270/LTC4271 Layout Guide document when laying

out the board.

Figure 6. DC1682B Digital and Analog Isolation

Isolation and Power Supplies

The LTC4270/LTC4271 chipset provides communication

across an isolation barrier through a data transformer

(Figure 6). This eliminates the need for expensive opto-

couplers. All digital pins reside on the digital ground refer-

ence and are isolated from the analog PoE supply. A 3.3V

supply for VDD and an isolated VEE supply are connected

to the DC1682B through the 34-pin connector.

VDD33

DND

CPD

CND

DPD

AGND

VEE

DNA

VEE

ISOLATION

WÜRTH 7490100143

CPA

34-PIN

CONNECTOR

DC1682B SIDE DC1680A SIDE

VDD33 SUPPLY

VEE

SUPPLY

CNA

DPA

TX+

RX–

CT(4)

CT(2)

RX+

TX–

TD+

RD–

CT(3)

RD+

TD–

LTC4271 U2

LTC4270

C23

1µF

C21

0.1µF

R13

100Ω

DC1840B F06

DGND

C19

1µF

100V

R35

10Ω

SMAJ58A

R14

100Ω

C22

1µF

R15

100Ω

R16

100Ω

R21

100Ω

R22

100Ω

R23

100Ω

R24

100Ω

C24, 2nF

2kV

CBULK

TVSBULK

–

dc1840bfc

DEMO MANUAL DC1840B

Demonstration circuit 1682B operation

Figure 7. DC1682B LTC4271 I2C and Address Connections

I2C Communication and Addressing

TheLTC4271internalregisters areaccessedvia I2Ctoread

and/or write configuration, status, and interrupt registers.

The I2C lines SDAOUT, SDAIN and SCL connect to the

34-pin connector (Figure 7). Subsequently, the I2C bus

is accessed on the DC1680.

The LTC4270/LTC4271 chipset has an address of

(A610A3A2A1A0b), where A6, A3, A2, A1, and A0are the

logic state of the AD6, AD3, AD2, AD1, and AD0 pins

respectively. On the DC1682B, AD0 and AD1 are tied low

with pull-down resistors. AD2, AD3 and AD6 are brought

out to the 34-pin connector (Figure 7) and set with three

switches on the DC1680.

I/O LED Indicators

The DC1682B features four LEDs to indicate the states of

theLTC4270/LTC4271chipsetgeneralpurposeinputoutput

pins. These pins are configured as inputs or outputs via

I2C. GP1 and GP0 are referenced to DGND and driven by

the LTC4271 when set as outputs (Figure 8). XIO0 and

XIO1 are referenced to VEE and are driven by the LTC4270

when set as outputs (Figure 9). J2 provides test points

for access to these I/Os.

Figure 8. DC1682B, LTC4270 General Purpose I/O LED Indicators

Figure 9. DC1682B, LTC4271 General Purpose I/O LED Indicators

Figure 10. DC1682B AUTO and MID Jumpers

DGND

SDAOUT

SDAIN

SCL

INT

SDAOUT

SDAIN

SCL

INT

AD6

AD3

AD2

AD1

AD0

AD6

AD3

AD2

TO 34-PIN

CONNECTOR

LTC4271

0Ω

DC1840B F07

0Ω R9

0Ω

VDD33

GP1

GP0

DGND

J2, PIN 5

J2, PIN 6

LTC4271

DC1840B F09

R28

560Ω R29

560Ω

GRN

GP0

GRN

GP1

VDD33

AUTO

MID

DGND

J2, PIN 3

J2, PIN 4

LTC4271

DC1840B F10

JP1 JP2

AUTO

MID

AGND

XIO1

XIO0

VEE

J2, PIN 9

J2, PIN 10

VEE

LTC4270

DC1840B F08

R30

27k R31

27k

GRN

XIO0

GRN

XIO1

Q13B

BC846AS

Q13A

BC846AS R33

220k

R32

220k

dc1840bfc

DEMO MANUAL DC1840B

Demonstration circuit 1682B operation

AUTO and MID Jumpers

The AUTO and MID pins of the LTC4271 are set by

jumpers JP1 and JP2 respectively on the DC1682B

(Figure 10). Setting JP1 to HI enables the AUTO pin mode

in the LTC4270/LTC4271 chipset. J2 provides test points

for access to AUTO and MID.

In AUTO pin mode (JP1 high), the LTC4270/LTC4271

chipset internal I2C registers default to the AUTO pin high

state after a software or hardware reset, or system power

on. The LTC4270/71 chipset autonomously detects, pow-

ers on and disconnects power to PDs without the need

for I2C host control.

Setting JP1 to LO disables AUTO pin mode and sets the

LTC4270/LTC4271 chipset to a low current shutdown

mode. An I2C host controller can then be used to con-

figure the LTC4270/LTC4271 chipset to semi-auto mode

for controlled PSE operation or to manual mode for test

purposes.

Setting JP2 to HI enables the midspan mode detection

backoff timer in the LTC4270/LTC4271 chipset. For end-

point PSEs, set JP2 to LO to disable midspan mode.

For quick PSE evaluation in AUTO pin mode with

MIDSPANdisabled,setJP1HIandJP2LOontheDC1682B.

Surge Protection

Ethernet ports can be subject to significant cable surge

events.TokeepPoE voltagesbelow asafelevel andprotect

the application against damage, protection components,

as shown in Figure 11, are required at the main supply,

at the LTC4270 supply pins and at each port.

Bulk transient voltage suppression (TVSBULK) and bulk

capacitance (CBULK) are required across the main PoE

supply and should be sized to accommodate system level

surge requirements.

EachLTC4270 requires a 10Ω, 0805resistor (R1) in series

from supply AGND to the LTC4270 AGND pin. Across the

LTC4270 AGND pin and VEE pin are an SMAJ58A, 58V

TVS (D1) and a 1μF, 100V bypass capacitor (C19). These

components must be placed close to the LTC4270 pins.

Finally, each port requires a pair of S1B clamp diodes:

one from OUTn to supply AGND and one from OUTn to

supply VEE. The diodes at the ports steer harmful surges

into the supply rails where they are absorbed by the surge

suppressors and the VEE bypass capacitance. The layout

of these paths must be low impedance. These S1B diodes

are placed on the DC1680 mother board of the DC1840 kit.

Figure 11. DC1682B, 1 of 12 Ports Surge Protection

34-PIN

CONNECTOR

DC1682B SIDE DC1680 SIDE

DC1840B F11

VEE

VEE VEE

S1B

PROTECTION

S1B

VSSK

C19

1µF

100V

R35

10Ω

D26

B1100

4 × 1.00

FDMC3612

OUTn OUTn

PORT

SENSEn

RSENSEn

GATEn OUTn

LTC4270

AGND

SMAJ58A

C26

0.1µF

0.22µF

X7R

100V

VEE

+CBULK

TVSBULK

dc1840bfc

DEMO MANUAL DC1840B

Demonstration circuit 1680a operation

Demonstration circuit 1680A is a 12-Port, IEEE802.3at

Type 1 and Type 2 PoE PSE mother board. This board

accepts various PSE daughter cards featuring Linear

Technology PSE controllers. The DC1680A is capable of

powering up to 12 PDs.

Daughter Card Insertion Precautions

When inserting or removing the daughter card into the

DC1680A, verify all supplies and LEDs are off. Push the

card straight down for insertion or pull straight up for

removal to avoid bending the connector pins. Follow the

instructions in the Quick Start Procedure for alignment.

VEE Supply

ConnectapowersupplyforVEE withthepositiverailtoPOS

and negative rail to NEG as shown in Figure 3 of the Quick

Start Procedure. Set the voltage within the range in Table 1

dependingon whetherthe application isa Type1or Type2.

Choose a power supply rating and set the current limit

highenoughto providepower forthe maximumnumberof

PDs connected and to meet each PD power requirements.

Table 1. DC1680A VEE Power Range for Type 1 and Type 2 PSEs

PSE TYPE

VEE SUPPLY

RANGE

MAX DELIVERED

PORT POWER

POWER

SUPPLY*

Type 1 45V to 57V 13W 300W

Type 2 51V to 57V 25.5W 600W

*Recommended DC1840A power supply minimum to avoid dropping in

a worst-case scenario with ILIM current at all 12 ports.

PD Connection

PDs are connected using an Ethernet cable to any of the

12 ports at the 2×6, RJ45 connector J4 on the DC1680A

(Figure 3). J4 has an integrated Ethernet transformer and

common mode termination for each port. Test points for

port outputs OUT1 through OUT12 are provided.

DC1680A USER FEATURES

Refer to Figure 12 and Figure 13 for the following user

features.

Onboard 3.3V Supply

The DC1680A has an onboard VDD33 digital supply gener-

atedfromtheVEE supply.VDD33 istiedtoAGND,and DGND

is a negative voltage referenced to AGND. If an external

3.3V supply is to be used, contact Linear Technology Ap-

plications for proper connection.

VEE and VDD33 LED Indicators

LEDs for VEE and VDD33 indicate if voltage is present at

these supplies. Verify these LEDs are off before inserting

or removing the daughter card.

Digital Connections

The DC1680A has connections for I2C control from a

host controller. The DC590 is optionally connected to

the DC1680A at J5 through a 14-pin ribbon cable. The

QuikEval software will automatically detect the DC1680A

and open the LTC4271 GUI. Refer to the LTC4271 PSE

Demo Software User Manual document for instructions

on using the GUI. A second 14-pin ribbon cable can be

connected to J6 for I2C expansion to another DC1680A

board with slight board modifications. Contact Linear

Technology Applications for instructions.

Digital test points include SCL, SDA, DGND, INT, MSD,

and RESET. I2C address pin AD6, AD3, and AD2 are set

with a 3-bit switch SW3.

Midspan PSE

The DC1840A can be configured as a midspan PSE.

Upstream switch data comes in to J3. Data and PoE go

out to a PD at J4. Set both MID and AUTO pins logic high.

dc1840bfc

DEMO MANUAL DC1840B

Demonstration circuit 1680a operation

Figure 12. DC1680A Connections and Supply LEDs

MSD and RESET Pushbuttons

Pushbutton switch SW1, when pressed, pulls the RESET

pin of the daughter card logic low. The PSE controller is

thenheldinactive withall portsoff andallinternal registers

reset to their power-up states. When SW1 is released,

RESET ispulledhigh,andthePSEbeginsnormaloperation.

Pushbutton switch SW2 when pressed pulls the maskable

shutdown input (MSD) pin of the daughter card logic low.

Whenpressed,allportsthathavetheircorrespondingmask

bit set in the mconfig register of the PSE controller will be

shutdown. These ports must then be manually re-enabled

via I2C or by resetting the PSE.

Ce manuel convient aux modèles suivants

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