Linear Technology LTC2268-14 Manuel utilisateur

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LTC2263CUJ-12#PBF

ANALOG DEVICES

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QUICK START GUIDE FOR DEMONSTRATION CIRCUIT 1532

12/14 BIT, 25 TO 125 MSPS DUAL ADC

LTC2268-14, LTC2268-12, LTC2267-14, LTC2267-12, LTC2266-14, LTC2266-12, LTC2265-14,

LTC2265-12, LTC2264-14, LTC2264-12, LTC2263-14, LTC2263-12

DESCRIPTION

Demonstration circuit 1532 supports a family of 14/12

BIT 125 MSPS ADCs. Each assembly features one of

the following devices: LTC2268-14, LTC2268-12,

LTC2267-14, LTC2267-12, LTC2266-14, LTC2266-12,

LTC2265-14, LTC2265-12, LTC2264-14, LTC2264-12,

LTC2263-14, LTC2263-12 high speed, dual ADCs.

The versions of the 1532A demo board are listed in

Table 1. Depending on the required resolution and

sample rate, the DC1532 is supplied with the appropri-

ate ADC. The circuitry on the analog inputs is opti-

mized for analog input frequencies from 5 MHz to

140MHz. Refer to the datasheet for proper input net-

works for different input frequencies.

Design files for this circuit board are available. Call

the LTC factory.

LTC is a trademark of Linear Technology Corporation

Table 1.

DC1532 Variants

DC1532

VARIANTS

ADC PART

NUMBER

RESOLUTION* MAXIMUM SAMPLE

RATE

INPUT FREQUENCY

1532A-A

LTC2268-14 14-BIT 125 Msps 5MHz-140MHz

1532A-B

LTC2267-14 14-BIT 105 Msps 5MHz-140MHz

1532A-C

LTC2266-14 14-BIT 80 Msps 5MHz-140MHz

1532A-D

LTC2265-14 14-BIT 65 Msps 5MHz-140MHz

1532A-E

LTC2264-14 14-BIT 40 Msps 5MHz-140MHz

1532A-F

LTC2263-14 14-BIT 25 Msps 5MHz-140MHz

1532A-G

LTC2268-12 12-BIT 125 Msps 5MHz-140MHz

1532A-H

LTC2267-12 12-BIT 105 Msps 5MHz-140MHz

1532A-I

LTC2266-12 12-BIT 80 Msps 5MHz-140MHz

1532A-J

LTC2265-12 12-BIT 65 Msps 5MHz-140MHz

1532A-K

LTC2264-12 12-BIT 40 Msps 5MHz-140MHz

1532A-L

LTC2263-12 12-BIT 25 Msps 5MHz-140MHz

QUICK START GUIDE FOR DEMONSTRATION CIRCUIT 1532

12/14 BIT, 25 TO 125 MSPS DUAL ADC

Table 2.

Performance Summary (TA= 25°C)

PARAMETER CONDITION VALUE

Supply Voltage – DC1532A Depending on sampling rate and the A/D converter

provided, this supply must provide up to 500mA.

Optimized for 3V

[3V 6.0V min/max]

Analog input range Depending on SENSE Pin Voltage 1 V

to 2V

Minimum Logic High 1.3V

Logic Input Voltages

Maximum Logic Low 0.6V

Nominal Logic levels (100Ωload, 3.5mA Mode) 350mV/1.25V com

mon mode

Logic Output Voltages (differential)

Minimum Logic levels (100Ω load, 3.5mA Mode) 247mV/1.25V common mode

Sampling Frequency (Convert Clock Fre-

quency)

See Table 1

Encode Clock Level Single ended Encode Mode (ENC- tied to GND) 0-3.6V

Encode Clock Level Differential Encode Mode (ENC- not tied to GND) 0.2V-3.6V

Resolution See Table 1

Input frequency range See Table 1

SFDR See Applicable Data Sheet

SNR See Applicable Data Sheet

QUICK START PROCEDURE

Demonstration circuit 1532 is easy to set up to

evaluate the performance of the LTC2268 A/D

converters. Refer to Figure 1 for proper meas-

urement equipment setup and follow the proce-

dure below:

SETUP

If a DC1371 “PStache” Data Acquisition and Col-

lection System was supplied with the DC1532

demonstration circuit, follow the DC1371 Quick

Start Guide to install the required software and

for connecting the DC1371 to the DC1532 and to

a PC running Windows 2000 or XP.

Figure 1. DC1532 Setup (zoom for detail)

3.5-6V

Analog Inputs

Single Ended Encode Clock

(Use provided DC1075, di-

vide by 4 clock board)

Channel 1

Channel 2

To provided power supply

To provided USB cable

Parallel/Serial

DC1532 DEMONSTRATION CIRCUIT

BOARD JUMPERS

The DC1532 demonstration circuit board

should have the following jumper settings as

default positions: (as per Figure 1)

J13: PAR/SER : Selects Parallel or Serial pro-

gramming mode. (Default - Serial)

Optional Jumpers:

J8: Term: Enables/ Disable optional output

termination. (Default - Removed)

J5: ILVDS: Selects either 1.75mA or 3.5mA

of output current for the LVDS drivers. (De-

fault – Removed)

J14: LANE: Selects either 1 lane or 2 lane

output modes (Default – Removed) NOTE:

The DC1371 does not support 1 lane opera-

tion.

J15: SHDN: Enables and disables the

LTC2268. (Default - Removed)

J2: WP: Enable/Disables write protect for the

EEPROM. (Default – Removed)

Note: optional jumper should be left open to

ensure proper serial configuration.

APPLYING POWER AND SIGNALS TO THE

DC1532 DEMONSTRATION CIRCUIT

The DC1371 is used to acquire data from the

DC1532, the DC1371 must FIRST be con-

nected to a powered USB port and have 5V

applied power BEFORE applying +3.6V to

+6.0V across the pins marked “V+” and

“GND” on the DC1532. DC1532 requires 3.6V

for proper operation.

Regulators on the board produce the volt-

ages required for the ADC. The DC1532

demonstration circuit requires up to 500mA

depending on the sampling rate and the A/D

converter supplied.

The DC1532 should not be removed, or con-

nected to the DC1371 while power is applied.

ANALOG INPUT NETWORK

For optimal distortion and noise performance

the RC network on the analog inputs may

need to be optimized for different analog input

frequencies. For input frequencies above 140

MHz, refer to the LTC2268 datasheet for a

proper input network. Other input networks

may be more appropriate for input frequen-

cies less that 5MHz.

In almost all cases, filters will be required on

both analog input and encode clock to provide

data sheet SNR.

The filters should be located close to the in-

puts to avoid reflections from impedance dis-

continuities at the driven end of a long trans-

mission line. Most filters do not present 50Ω

outside the passband. In some cases, 3dB to

10dB pads may be required to obtain low dis-

tortion.

If your generator cannot deliver full scale sig-

nals without distortion, you may benefit from a

medium power amplifier based on a Gallium

Arsenide Gain block prior to the final filter.

This is particularly true at higher frequencies

where IC based operational amplifiers may be

unable to deliver the combination of low noise

figure and High IP3 point required. A high or-

der filter can be used prior to this final ampli-

fier, and a relatively lower Q filter used be-

tween the amplifier and the demo circuit.

Apply the analog input signal of interest to the

SMA connectors on the DC1532 demonstra-

tion circuit board marked “J3 AIN1”, “J4 AIN2”,

“J6 AIN3”, “J7 AIN4”. These inputs corre-

spond with channels 1-4 of the ADC respec-

tively. These inputs are capacitive coupled to

Balun transformers ETC1-1-13.

ENCODE CLOCK

NOTE: Apply an encode clock to the SMA

connector on the DC1532 demonstration cir-

cuit board marked “J11 CLK+”. As a default

the DC1532 is populated to have a single

ended input.

For the best noise performance, the ENCODE

INPUT must be driven with a very low jitter,

square wave source. The amplitude should be

large, up to 3V

P-P

or 13dBm. When using a

sinusoidal signal generator a squaring circuit

can be used. Linear Technology also pro-

vides demo board DC1075A that divides a

high frequency sine wave by four, producing a

low jitter square wave for best results with the

LTC2268.

Using band pass filters on the clock and the

analog input will improve the noise perform-

ance by reducing the wideband noise power

of the signals. In the case of the DC1532 a

band pass filter used for the clock should be

used prior to the DC1075A. Datasheet FFT

plots are taken with 10 pole LC filters made by

TTE (Los Angeles, CA) to suppress signal

generator harmonics, non-harmonically re-

lated spurs and broadband noise. Low phase

noise Agilent 8644B generators are used for

both the Clock input and the Analog input.

DIGITAL OUTPUTS

Data outputs. data clock, and frame clock sig-

nals are available on J1 of the DC1532. This

connector follows the VITA-57/FMC standard,

but all signals should be verified when using an

FMC carrier card other than the DC1371.

SOFTWARE

The DC1371A is controlled by the PScope

System Software provided or downloaded

from the Linear Technology website at

http://www.linear.com/software/.

To start the data collection software if

“PScope.exe”, is installed (by default) in

\Program Files\LTC\PScope\, double click the

PScope Icon or bring up the run window un-

der the start menu and browse to the PScope

directory and select PScope.

If the DC1532 demonstration circuit is prop-

erly connected to the DC1371, PSCOPE

should automatically detect the DC1532, and

configure itself accordingly.

If everything is hooked up properly, powered

and a suitable convert clock is present, click-

ing the “Collect” button should result in time

and frequency plots displayed in the PScope

window. Additional information and help for

PScope is available in the DC1371A Quick

Start Guide and in the online help available

within the PScope program itself.

SERIAL PROGRAMMING

PScope has the ability to program the DC1532

board serially through the DC1371. There are

several options available in the LTC2268 family

that are only available through serially pro-

gramming. PScope allows all of these features

to be tested.

These options are available by first clicking on

the “Set Demo Bd Options” icon on the PScope

toolbar (Figure 3).

Figure 3: PScope Toolbar

This will bring up the menu shown in figure 4.

Figure 4: Demobd Configuration Options.

This menu allows any of the options available for

the LTC2268 family to be programmed serially.

The LTC2268 family has the following options:

Randomizer

– Enables Data Output Random-

izer

- Off (Default) – Disables data output randomizer

- On – Enables data output randomizer

Two’s complement

– Enables two’s comple-

ment mode

- Off (Default) – Selects offset binary mode

- On – Selects two’s complement mode

Sleep Mode

– Selects between normal opera-

tion, sleep mode:

- Off (Default) – Entire ADC is powered, and ac-

tive

- On – The entire ADC is powered down.

Channel 1 Nap-

Selects between normal opera-

tion and putting channel 1 in nap mode.

-Off (Default) – Channel one is active

- On – Channel one is in nap mode

Channel 2 Nap-

Selects between normal opera-

tion and putting channel 2 in nap mode.

-Off (Default) – Channel two is active

- On – Channel two is in nap mode

Output Current

– Selects the LVDS output drive

current

- 1.75mA (Default) - LVDS output driver current

- 2.1mA - LVDS output driver current

- 2.5mA - LVDS output driver current

- 3.0mA - LVDS output driver current

- 3.5mA - LVDS output driver current

- 4.0mA - LVDS output driver current

- 4.5mA - LVDS output driver current

Internal Termination

– Enables LVDS internal

termination

- Off (Default) – Disables internal termination

- On – Enables internal termination

Outputs

– Enables Digital Outputs

- Enabled (Default) – Enables digital outputs

- Disabled – Disables digital outputs

Test Pattern

– Selects Digital output test pat-

terns. The desired test pattern can be entered

into the text boxes provided.

-Off(default) – ADC input data is displayed

-On – Test pattern is displayed.

Once the desired settings are selected hit OK

and PScope will automatically update the regis-

ter of the device on the DC1532 demo board.

Ce manuel convient aux modèles suivants

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