Intel PD6730 Instructions d'installation et d'utilisation

PD672X/30/32/33 — ZV Port

Implementation

Application Note

May 2001

As of May 2001, this document replaces the Basis Communications Corp. document AN-PD10.

Application Note

Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any intellectual

property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability

whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to

fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not

intended for use in medical, life saving, or life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice.

Designers must not rely on the absence or characteristics of any features or instructions marked “reserved”or “undefined.”Intel reserves these for

future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

The PD672X/30/32/33 —ZV Port Implementation may contain design defects or errors known as errata which may cause the product to deviate from

published specifications. Current characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

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*Third-party brands and names are the property of their respective owners.

Application Note 3

PD672X/30/32/33 —ZV Port Implementation

Contents

1.0 Introduction..................................................................................................................5

2.0 Overview........................................................................................................................6

3.0 Zoomed Video (ZV)....................................................................................................6

4.0 A Typical ZV Port Implementation ......................................................................6

5.0 Dedicated Socket Approach to ZV Port Implementation...........................9

6.0 Buffer Implementation for Audio DAC.............................................................10

7.0 ZV Port Implementation for Socket A and B.................................................11

8.0 Layout Guidelines....................................................................................................15

Figures

1 Typical ZV Port Implementation............................................................................7

2 Dedicated Socket Approach to ZV Port Implementation.......................................9

3 Buffer Implementation for Audio DAC.................................................................10

4 ZV Port Implementation for Socket A and B........................................................11

Tables

1 PC Card, ZV Port, and PD6722 Pin Assignment ................................................11

2 PC Card, ZV Port, and PD6729 Pin Assignment ................................................12

3 PC Card, ZV Port, and PD6730/’6832 Pin Assignment.......................................13

4Application Note

PD672X/30/32/33 — ZV Port Implementation

PD672X/30/32/33 —ZV Port Implementation

Application Note 5

1.0 Introduction

The PD6710, PD6722, and PD6729 are single-chip PCMCIA interface controllers capable of

controlling one or two PCMCIA or compact Flash sockets, respectively. They are designed for use

in embedded applications and notebook systems where reduced form factor and low power

consumption are critical design objectives.

Current typical application examples include:

With the PD6710, a complete single-socket PCMCIA solution with power-control circuitry can

occupy less than 1.5 square inches (10 square centimeters) of board space. Similarly, with the

PD6722 and PD6729, a complete dual-socket PCMCIA solution with power-control circuitry can

occupy less than 2 square inches (13 square centimeters) of board space.

The PD67XX controllers are completely compatible with the standards of PCMCIA (Personal

Card Memory International Association) Release 2.0 Standard as well as JEIDA (Japan Electronic

Industry Development Association) Version 4.1 Standard (PD6729 is compliant with the PCI 2.1

Specification. The PD67XX controllers also offer special power-saving features such as Automatic

Low-power Dynamic Mode and Suspend Mode. Both controllers are true mixed-voltage devices

that can operate at +5 volts, +3.3 volts, or a combination of these at various interfaces. The

controllers have full internal buffering and require no additional circuitry to interface to the ISA (or

ISA-like) Bus for the PD6710 and PD6722, and the PCI Bus for PD6729, or to PCMCIA sockets.

Note: In this document, PD67XX represents the PD6710, PD6722, and PD6729.

■Routers ■Integrated access devices

■Access network servers ■DSLAMs

■PBXs ■Terminal servers

■Vending machines ■Point of Sale terminals

■Portable handheld systems ■Navigation systems

■Data acquisition systems ■Measurement equipment

■Settop boxes

PD672X/30/32/33 —ZV Port Implementation

6Application Note

2.0 Overview

This application note discusses system design considerations associated with the implementation

of the ZV (Zoomed Video) Port when using the PD6722/’29/’30, or PD6832 controller devices.

Intended to assist the system designer, this document highlights how various aspects of the PC

Card relate to the ZV Port implementation. Since the ZV Port implementation overlaps PC Card,

graphics, and audio technologies, consulting with appropriate applications/product groups is

recommended.

3.0 Zoomed Video (ZV)

ZV is a cost-effective method of accessing live video through a PC Card. The ZV Port provides a

direct connection between a PC Card and a VGA controller and an audio DAC. It allows the PC

Card to directly write video data to an input port of a graphics controller and audio data to a digital-

to-analog converter. Intel offers a family of PC Card (PCMCIA) Controllers that support the ZV

Port standard.

4.0 A Typical ZV Port Implementation

Figure 1 on page 7 illustrates a typical ZV Port implementation with PD6722/’29/’30 and PD6832

controller devices. These devices support the ZV Port in the ‘bypass’ mode during which the

signals are directly rerouted from the PC Card bus to the Video ZV Port (the video port of the

GD7XXX device is also referred to as the V-Port). This rerouting is accomplished by tristating

specific PC Card Bus signals from the PC Card (PCMCIA) Controller. Once these signals are

tristated by the host controller during the ZV Port operation, the ZV Port-compliant PC Card drives

video and audio data on the same signals. Video signals from the PC Card are routed to the ZV

Port-capable video controller; audio signals from the PC Card are routed to the ZV Port-compliant

audio DAC in the host system. This mechanism provides an inexpensive means of adding video/

audio capability to a notebook or desktop system without any additional burden on the host bus.

As specified in the PC Card standard, a ZV Port-compliant PC Card, when inserted into a PC Card

slot, is initialized the same way as a PC Card 16. It is then recognized as a ZV Port card and

programmed accordingly by Card Services. As shown in Figure 1, the PD6722/’29/’30/’6832

enters the ZV Port mode by tristating address pins A[25:4] of the PC Card bus when the

Multimedia Enable bit (bit 0 of the Misc. Control register 1 at index 16h in the PD6722/’29/’30 and

PD6832; in the PD6832 it can also be at memory offset 816h) is set. These address pins are outputs

from the PD6722/’29/’30/’6832 during normal PC Card operation. The tristating of the address

pins by the adapter allows the A[25:4] signals to simultaneously carry video data and video capture

timing control signals directly to a video controller, and the audio signals to the audio DAC. The

PD6832 has a Multimedia Arm bit (bit 7 of the Misc. Control register 3; this register is at I/O index

2Fh, extended index 25h, or memory offset 925h) that works as the overriding control bit. Until the

Multimedia Arm bit is set, the Multimedia Enable bit does not tristate the address bit as previously

described. When the Multimedia Expand bit (bit 6 of Misc. Control register 3) is set to ‘1’, CE2

and D[15:8] are tristated on the 16-bit PC Card bus, in addition to the tristating of the address

signals A[25:4]. The Multimedia Expand bus allows 24-bit video from the ZV Port-compliant PC

Card.

PD672X/30/32/33 —ZV Port Implementation

Application Note 7

Note that ZV Port implementation is likely to vary depending on the platform; the Socket Services

software must be customized to address these variances. Controlling the OE (output enable) inputs

of the external buffers depends upon specific hardware design and software needs to be aware of

specifics, such as the I/O Port addresses.

When the PC Card Multimedia mode is used, Intel recommends that the ZV Port pins be connected

as shown in Tables 1–3 for the various controller devices. The pin assignments provided in the

tables ensure signal integrity and compliance with the ZV Port standard. By disabling or powering

down the ZV Port, this connection between the GD7XXX and the PC Card bus does not interfere

with the normal (non-multimedia) PC Card bus operation.

When the ZV Port is disabled, VPM (Video Port Manager) software or other client drivers must

program the VGA controller so as not to adversely affect the video port of the VGA controller. A

bus switch, turned off during normal PC Card bus operation, may be needed to reduce the load on

the PC Card bus.

Figure 1. Typical ZV Port Implementation

DRAM

GD7XXX

ANALOG

PD6722

PD6729

PD6730

PD6832

VIDEO

PCM

PC CARD

INTERFACE

PC CARD

MOTHERBOARD

AUDIO

VIDEO

NTSC/PAL

AUDIO

VIDEO & CONTROL

PC CARD SLOT

TV LCD CRT

AMP

AUDIO

CODEC

SPEAKERS

4PCM

AUDIO

INPUT

ZV PORT

(Video)

HOST BUS

PD6833

ENCODER

RF SIGNAL

CONVERTER

DECODER

PD672X/30/32/33 —ZV Port Implementation

8Application Note

A buffer circuit placed between the PC Card bus and the VGA video port reduces the trace length

to lower the loading effect. The ZV Port standard requires that the length of the trace between the

PC Card connector and the buffer (if used) must be less than two inches. Buffers are also needed to

support ZV Port PC Cards in either socket.

In a full implementation of the ZV Port, multiple PC Card slots can be used to implement the ZV

Port. This implies that the user inserts the multimedia PC Card into either slot and the system is

able to recognize and respond to this event appropriately. To allow the multimedia PC Card to be

inserted into either slot, the individual PC Card bus must be isolated from the other bus by using

buffers in the system. The following block diagrams illustrate possible ZV Port implementations.

Note that the control signal inputs to the buffers can be controlled by different methods. For the

GD7XXX, the buffer control comes from the I/O pins of the GD7XXX that are labeled VPCNTL

and TVON. For further information, refer to the application note titled, “V-Port Implementation for

the GD7548 Super VGA Controller”.

PD672X/30/32/33 —ZV Port Implementation

Application Note 9

5.0 Dedicated Socket Approach to ZV Port

Implementation

Figure 2 shows a solution using the PD6722/’29/’30/’6832 Controller and the GD7XXX Super

VGA controller to support a single dedicated ZV Port slot. This simple implementation does not

require any external buffer or glue logic; the only limitation is that one socket must be dedicated to

the ZV Port. Also, depending upon the audio controller used, a buffer may be required between the

PC Card bus and the audio controller. The designer must ensure that while in R2 PC Card mode

(non-ZV operation), the traffic over the bus does not cause the audio input to be driven or the video

port of the VGA controller to be adversely affected. If the audio controller or VGA controller do

not support a shutdown mode, buffers are required in each path. Also refer to “Layout Guidelines”

on page 15 to determine if buffers are required for the video path.

Figure 2. Dedicated Socket Approach to ZV Port Implementation

GD7XXX

PD6722

PD6729

PD6730

PD6832

V-PORT

ZV PORT PC CARD

AUDIO CODEC

PC CARD BUS

PD6833

PD672X/30/32/33 —ZV Port Implementation

10 Application Note

6.0 Buffer Implementation for Audio DAC

A buffer solution to isolate the audio controller when the socket is not configured in ZV Port mode

is shown in Figure 3. This illustrates how to control the buffer enable; if the GD7XXX is used, then

one of the GPO pins can control the buffer enable.

Figure 3. Buffer Implementation for Audio DAC

GD7XXX

V-PORT

ZV PORT PC CARD

PC CARD BUS

BUFFER

AUDIO

PD6722

PD6729

PD6730

PD6832

PD6833

Ce manuel convient aux modèles suivants

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