Holtek HT827A0 Manuel utilisateur

HT827A0

8-Bit Microcontroller with Voice ROM

1 March 15, 2000

Features

8-bit microcontroller

·Operating voltage: 2.4V~5.2V

·8K´16 program ROM

·208´8 data RAM

·36 bidirectional I/O lines

·Interrupt input

·16-bit programmable timer/event

counter with overflow interrupts

·Watchdog timer

·On-chip crystal or RC types of oscillator

·Halt function and wake-up feature reduces

power consumption

·63 powerful instructions

·Up to a 1ms instruction cycle with a 4MHz

system clock at VDD=5V

·All instructions in 1 or 2 machine cycles

·16-bit table read instruction

·8-level subroutine nesting

·Bit manipulation instruction

General Description

The HT827A0 is 8-bit high performance

microcontroller with a voice synthesizer and

tone generator. They are designed for applica-

tions on multiple I/Os with sound effects. The

LSIs provide 26 kinds of voice sampling rates, 4

octaves of tone level as well as a high quality of

current type D/A output. With such a flexible

structure, the HT827A0 is excellent for versa-

tile voice and sound effect product applications.

It also includes a halt function to reduce power

consumption.

Voice and melody synthesizer

·128K´8 voice ROM

·3/4 bit ADPCM coding algorithm

·26 kinds of voice sampling rates

·Tone level of 4 octaves

·14 kinds of melody beats

·Current type of D/A switch output

·Tone generator counter

·Controllable volume

·48-pin DIP package

Applications

·Intelligent educational toys

·High end toy controllers

·Talking alarm clocks

·Alert and warning systems

·Public address systems

·Sound effect generators

Block Diagram

Pin Assignment

HT827A0

2 March 15, 2000

IN T

OSC1

OSC2

RES

8-bit H igh Perform ance

M icrocontroller

Voice ROM

C ontroller

Voice

Synthesizer

Tone generator

C urrent Type

D/A Output

36-bit Bidirectional

I/O P o rts

TM R

AUD

PA0

PA7

PB0 PB7 PC0 PC7 PD0 PD7 PE0 PE3

VDD

VSS

PA3

PA2

PA1

PA0

PB3

PB2

PB1

PB0

VSS

PE0

PE1

PE2

PE3

IN T

TM R

PD0

PD1

PD2

PD3

PD4

PD5

PD6

PD7

PB4

PB5

PB6

PB7

PA4

PA5

PA6

PA7

OSC2

OSC1

VDD

RES

AUD

PC7

PC6

PC5

PC4

PC3

PC2

PC1

PC0

0 6& %) 

"&, 12

Pad Assignment

Chip size: 3555 ´5015 (mm)2

* The IC substrate should be connected to VSS in the PCB layout artwork.

* The TMR pad must be bound to VDD or VSS if it is not used.

HT827A0

3 March 15, 2000

13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

36 37 38

39 40

42 43

PB3

PB2

PB1

PB0

VSS

PE0

PE1

PE2

PE3

IN T

TM R

PC7

PC6

PC5

PC4

PC3

PC2

PC1

PC0

PD7

PD6

PD5

PD4

PD3

PD2

PD1

PD0

OSC2

OSC1

VDD

RES

AUD

PA7

PA6

PA5

PA4

PB7

PB6

PB5

PB4

PA3

PA2

PA1

PA0

(0 ,0 )

Pad Coordinates Unit: mm

Pad No. X Y Pad No. X Y

1-1543.05 2242.95 23 69.05 -2211.75

2-1486.75 1675.25 24 237.85 -2211.75

3-1486.75 1491.25 25 598.35 -2291.45

4-1486.75 1308.95 26 890.95 -2291.45

5-1486.75 1126.15 27 1184.35 -2291.45

6-1486.75 925.35 28 1476.95 -2291.45

7-1486.75 727.25 29 1507.85 -2091.35

8-1486.75 538.35 30 1499.05 -1925.15

9-1486.75 347.85 31 1539.95 -1757.35

10 -1486.75 157.35 32 1585.75 -1465.55

11 -1486.75 -28.35 33 1574.15 -667.75

12 -1486.75 -219.25 34 1502.55 2242.95

13 -1547.75 -2211.75 35 1227.35 2242.95

14 -1389.55 -2211.75 36 951.35 2242.95

15 -1239.35 -2211.75 37 676.15 2242.95

16 -1072.15 -2211.75 38 396.95 2242.95

17 -913.45 -2211.75 39 119.35 2242.95

18 -744.65 -2211.75 40 -159.85 2242.95

19 -585.95 -2211.75 41 -437.45 2242.95

20 -417.15 -2211.75 42 -716.65 2242.95

21 -258.45 -2211.75 43 -991.85 2242.95

22 -89.65 -2211.75 44 -1267.85 2242.95

Pad Description

Pad No. Pad Name I/O Mask

Option Description

1, 44~42,

37~34 PA0~PA7 I/O

Wake-up

Pull-high

or None

Bidirectional 8-bit input/output ports

Each bit can be configured as a wake-up input by mask

option. Software instructions determine the CMOS out-

put or schmitt trigger input with or without a pull-high re-

sistor (mask option).

5~2,

41~38 PB0~PB7 I/O Pull-high

or None

Bidirectional 8-bit input/output ports

Software instructions determine the CMOS output or

schmitt trigger input with or without a pull-high resistor

(mask option).

21~28 PC0~PC7 I/O Pull-high

or None

Bidirectional 8-bit input/output ports

Software instructions determine the CMOS output or

schmitt trigger input with or without a pull-high resistor

(mask option).

HT827A0

4 March 15, 2000

Pad No. Pad Name I/O Mask

Option Description

13~20 PD0~PD7 I/O Pull-high

or None

Bidirectional 8-bit input/output ports

Software instructions determine the CMOS output or

schmitt trigger input with or without a pull-high resistor

(mask option).

6 VSS ¾¾

Negative power supply, ground

7~10 PE0~PE3 I/O Pull-high

or None

Bidirectional 8-bit input/output ports

Software instructions determine the CMOS output or

schmitt trigger input with or without a pull-high resistor

(mask option).

11 INT I¾

External interrupt schmitt trigger input with a

pull-high resistor

Edge triggered is activated on a high to low transition.

12 TMR I ¾Schmitt trigger input for a timer/event counter

29 AUD O ¾Audio output for driving an external transistor

PMOS open drain output

30 RES I¾Schmitt trigger reset input, active low

31 VDD ¾¾

Positive power supply

OSC1

OSC2

Crystal or

OSC1 and OSC2 connect to an RC network or crystal os-

cillator (determined by mask option) for an internal sys-

tem clock. In the case of RC operation, an oscillation

resistor connects to OSC1. OSC2 is the output terminal

of a 1/4 system clock.

Absolute Maximum Ratings

Supply Voltage..............................-0.3V to 5.5V Storage Temperature.................-50°Cto125°C

Input Voltage .................VSS-0.3V to VDD+0.3V Operating Temperature ..............-25°Cto70°C

Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maxi-

mum Ratings²may cause substantial damage to the device. Functional operation of this de-

vice at other conditions beyond those listed in the specification is not implied and prolonged

exposure to extreme conditions may affect device reliability.

HT827A0

5 March 15, 2000

D.C. Characteristics Ta=25°C

Symbol Parameter Test Conditions Min. Typ. Max. Unit

VDD Conditions

VDD Operating Voltage ¾¾2.4 ¾5.2 V

IDD1 Operating Current (Crystal OSC) 3V No load,

fSYS=4MHz

¾1.5 3 mA

5V ¾35mA

IDD2 Operating Current (RC OSC) 3V No load,

fSYS=4MHz

¾1.5 3 mA

5V ¾2.5 5 mA

ISTB1 Standby Current (WDT Enabled) 3V No load,

system Halt

¾¾10 mA

5V ¾¾20 mA

ISTB2 Standby Current (WDT Disabled) 3V No load,

system Halt

¾¾ 3mA

5V ¾¾ 5mA

VIL Input Low Voltage for I/O Ports 3V ¾0¾0.6 V

5V ¾0¾1.0 V

VIH Input High Voltage for I/O Ports 3V ¾2.4 ¾3V

5V ¾4.0 ¾5V

VIL1 Input Low Voltage

(RES, TMR, INT)

3V ¾0¾0.6 V

5V ¾0¾1.0 V

VIH1 Input High Voltage

(RES, TMR, INT)

3V ¾2.4 ¾3V

5V ¾4.0 ¾5V

IOL1 I/O Port Sink Current

(PA, PC, PD, PE)

3V VOL=0.3V 24

¾mA

5V VOL=0.5V 610

¾mA

IOH1 I/O Port Source Current

(PA, PC, PD, PE)

3V VOH=2.7V -1-1.5 ¾mA

5V VOH=4.5V -2-4¾mA

IOL2 PB Sink Current 3V VOL=0.3V 610

¾mA

5V VOL=0.5V 20 25 ¾mA

IOH2 PB Source Current 3V VOH=2.7V -0.5 -1¾mA

5V VOH=4.5V -1-2¾mA

RPH Pull-high Resistance of I/O Ports

& INT

3V ¾25 50 100 kW

5V ¾10 30 60 kW

IOMax. AUD Output Current 3V VOH=0.6V -1.5 -2¾mA

5V VOH=0.6V -3.5 -4¾mA

HT827A0

6 March 15, 2000

A.C. Characteristics Ta=25°C

Symbol Parameter Test Conditions Min. Typ. Max. Unit

VDD Conditions

fSYS1 System Clock (Crystal OSC) 3V ¾400 ¾4000 kHz

5V ¾400 ¾4000 kHz

fSYS2 System Clock (RC OSC) 3V ¾400 ¾4000 kHz

5V ¾400 ¾4000 kHz

fTIMER Timer I/P Frequency (TMR) 3V ¾0¾4000 kHz

5V ¾0¾4000 kHz

tWDTOSC Watchdog Oscillator 5V ¾31 78 140 ms

tWDT1 Watchdog Timeout Period (RC) 5V Without WDT

prescaler 82036ms

tWDT2 Watchdog Timeout Period

(System Clock) 5V Without WDT

prescaler ¾1024 ¾tSYS

tRES External Reset Low Pulse Width 5V ¾1¾¾ms

tINT Interrupt Pulse Width 5V ¾1¾¾ms

Note: tSYS=1/(fSYS)

HT827A0

7 March 15, 2000

HT827A0

8 March 15, 2000

Functional Description

Executive flow

The HT827A0 provides a system clock which is

derived from a crystal or an RC type of oscillator.

The clock is internally divided into four

non-overlapping clocks denoted by P1, P2, P3 and

P4. An instruction cycle consists of T1~T4.

Instruction fetching and execution are

pipelined in such a way that a fetch takes an in-

struction cycle while decoding and execution

take the next instruction cycle. The pipelining

scheme causes each instruction to execute ef-

fectively in a cycle. If an instruction changes

the program counter, two cycles are required to

complete that instruction.

Program counter -PC

The program counter (PC) controls the se-

quence in which the instructions stored in the

program ROM are executed.

The contents of the program counter are incre-

mented by one after a program memory word is

accessed to fetch an instruction code. The pro-

gram counter then points to a memory word

containing the next instruction code.

The PC manipulates a program transfer by

loading the address corresponding to each in-

struction when executing a jump instruction,

conditional skip execution, loading PCL regis-

ter, subroutine call, initial reset, internal inter-

rupt, external interrupt or return from

subroutine.

The conditional skip is activated by instructions.

Once the condition is satisfied, the next instruc-

tion, fetched during the current instruction exe-

cution, is discarded and a dummy cycle replaces

it to get a proper instruction. Otherwise, the sys-

tem will proceed with the next instructions.

The lower byte of the program counter (PCL) is

a readable and writable register (06H). Moving

data into PCL performs a short jump. The desti-

nation is within 256 locations.

Once a control transfer takes place, the execu-

tion suffers from an additional dummy cycle.

T1 T2 T3 T4 T1 T2 T3 T4 T1 T2 T3 T4

F e tc h IN S T (P C )

Execute IN S T (P C -1) F e tc h IN S T (P C + 1 )

Execute IN S T (P C ) F e tc h IN S T (P C + 2 )

Execute IN S T (P C +1)

PC PC+1 PC+2

S ystem C lock

OSC2 (RC only)

Internal

Phase

C locks

Execution flow

HT827A0

9 March 15, 2000

Program memory -ROM

The program memory stores the to-be-executed

program instructions. It also includes data, ta-

ble and interrupt entries, addressed by the pro-

gram counter along with the table pointer.

The program memory size for HT827A0 is

8K´16.

Certain locations in the program memory are

reserved for special usage:

·Location 000H

This area is reserved for program initializa-

tion. The program always begins execution at

location 000H each time the system is reset.

·Location 004H

This area is reserved for an external interrupt

service program. The program begins execu-

tion at location 004H if the INT input pin is

activated, the interrupt is enabled and the

stack is not full.

·Location 008H

This area is reserved for a voice sampling rate

counter interrupt service program. The pro-

gram begins execution at location 008H if a

timer interrupt results from a sampling rate

counter overflow, the interrupt is enabled and

the stack is not full.

·Location 00CH

This area is reserved for a timer/event coun-

ter interrupt service program. The program

begins execution at location 00CH if an inter-

rupt results from a timer/event counter over-

flow, the interrupt is enabled and the stack is

not full.

Mode Program Counter

*12 *11 *10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0

Initial reset 00000000000 0 0

External interrupt 00000000001 0 0

Sampling rate counter

overflow 00000000010 0 0

Timer/event counter

overflow 00000000011 0 0

Skip PC+2

Loading PCL *12 *11 *10 *9 *8 @7 @6 @5 @4 @3 @2 @1 @0

Jump, call branch #12 #11 #10 #9 #8 #7 #6 #5 #4 #3 #2 #1 #0

Return from subroutine S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0

Program counter

Note: *12~*0: Bits of program counter S12~S0: Bits of stack register

#12~#0: Bits of instruction code @7~@0: Bits of PCL

D evice initialization program

External interrupt subroutine

Sam pling rate counter interrupt subroutine

Tim er/event counter interrupt subroutine

Look-up table (256 w ords)

000H

004H

008H

00C H

1FFFH

Program

ROM

Program memory

HT827A0

10 March 15, 2000

·Table location

Any location in the program ROM can be used

as a look-up table. The instructions

²TABRDC [m]²(the current page, 1 page=256

words) and ²TABRDL [m]²(the last page)

transfer the contents of the lower-order byte

to the specified data memory, and the

higher-order byte to TBLH (08H). Only the

destination of the lower-order byte in the ta-

ble is well-defined. The other bits of the table

word are transferred to the lower portion of

TBLH. The higher-order byte register

(TBLH) of the table is read only. The table

pointer (TBLP), on the other hand, is a

read/write register (07H) indicating the table

location. This location must be placed in

TBLP before accessing the table. All the table

related instructions require 2 cycles to com-

plete an operation. These areas may function

as a normal program memory depending

upon the user¢s requirements.

Stack register -Stack

The stack register is a special part of the mem-

ory used to save the contents of the program

counter (PC). This stack is organized into 8 lev-

els. It is neither part of the data nor program

space, and cannot be read or written to. Its acti-

vated level is indexed by a stack pointer (SP)

and cannot be read or written to. At a subrou-

tine call or interrupt acknowledgment, the con-

tents of the program counter are pushed onto

the stack. The program counter is restored to

its previous value from the stack at the end of a

subroutine or interrupt routine, which is sig-

naled by a return instruction (RET or RETI).

After a chip resets, SP will point to the top of

the stack.

The interrupt request flag will be recorded but

the acknowledgment will be inhibited when the

stack is full and a non-masked interrupt takes

place. After the stack pointer is decremented

(by RET or RETI), the interrupt will be ser-

viced. This feature prevents stack overflow and

allows programmers to use the structure more

easily. In a similar case, if the stack is full and a

²CALL²is subsequently executed, stack over-

flow occurs and the first entry is lost.

Data memory -RAM

The data memory is further divided into two

functional groups, namely, special function reg-

isters and general purpose data memories. Al-

though most of them can be read or be written

to, some are read only.

The data memory size for HT827A0 is shown as

follows.

Pard No. Special

RAM

General

RAM Address

HT827A0 00H~2FH 30H~FFH

The special function registers include an indi-

rect addressing register (00H), timer/event

counter high byte register (TMRH; 0FH),

timer/event counter low byte register (TMRL;

10H); timer/event counter control register

(TMRC; 11H), program counter lower-order

byte register (PCL; 06H), memory pointer reg-

ister (MP; 01H), accumulator (ACC; 05H), table

pointer (TBLP; 07H), table higher-order byte

(STATUS; 0AH), interrupt control register

(INTC; 0BH), watchdog timer option setting

PB; 14H, PC; 16H, PD; 18H, PE; 1AH) and I/O

Instruction(s) Table Location

*12 *11 *10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0

TABRDC [m] P12 P11 P10 P9 P8 @7 @6 @5 @4 @3 @2 @1 @0

TABRDL [m] 1 1 1 1 1 @7 @6 @5 @4 @3 @2 @1 @0

Table location

Note: *12~*0: Bits of table location P12~P8: Bits of current program counter

@7~@0: Bits of table pointer

Table des matières

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