Hitachi H8S/2215 Series Manuel utilisateur

Hitachi Single-Chip Microcomputer

H8S/2215 Series

Hardware Manual

ADE-602-217B

Rev. 3.0

10/04/02

Hitachi Ltd.

Rev. 3.0, 10/02, page ii of lviii

Cautions

1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s

patent, copyright, trademark, or other intellectual property rights for information contained in

this document. Hitachi bears no responsibility for problems that may arise with third party’s

rights, including intellectual property rights, in connection with use of the information

contained in this document.

2. Products and product specifications may be subject to change without notice. Confirm that you

have received the latest product standards or specifications before final design, purchase or

use.

3. Hitachi makes every attempt to ensure that its products are of high quality and reliability.

However, contact Hitachi’s sales office before using the product in an application that

demands especially high quality and reliability or where its failure or malfunction may directly

threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear

power, combustion control, transportation, traffic, safety equipment or medical equipment for

life support.

4. Design your application so that the product is used within the ranges guaranteed by Hitachi

particularly for maximum rating, operating supply voltage range, heat radiation characteristics,

installation conditions and other characteristics. Hitachi bears no responsibility for failure or

damage when used beyond the guaranteed ranges. Even within the guaranteed ranges,

consider normally foreseeable failure rates or failure modes in semiconductor devices and

employ systemic measures such as fail-safes, so that the equipment incorporating Hitachi

product does not cause bodily injury, fire or other consequential damage due to operation of

the Hitachi product.

5. This product is not designed to be radiation resistant.

6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document

without written approval from Hitachi.

7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi

semiconductor products.

Rev. 3.0, 10/02, page iii of lviii

General Precautions on the Handling of Products

1. Treatment of NC Pins

Note: Do not connect anything to the NC pins.

The NC (not connected) pins are either not connected to any of the internal circuitry or are

used as test pins or to reduce noise. If something is connected to the NC pins, the operation

of the LSI is not guaranteed.

2. Treatment of Unused Input Pins

Note: Fix all unused input pins to high or low level.

Generally, the input pins of CMOS products are high-impedance input pins. If unused pins

are in their open states, intermediate levels are induced by noise in the vicinity, a pass-

through current flows internally, and a malfunction may occur.

3. Processing before Initialization

Note: When power is first supplied, the product’s state is undefined. The states of internal

circuits are undefined until full power is supplied throughout the chip and a low level is

input on the reset pin. During the period where the states are undefined, the register

settings and the output state of each pin are also undefined. Design your system so that it

does not malfunction because of processing while it is in this undefined state. For those

products which have a reset function, reset the LSI immediately after the power supply has

been turned on.

4. Prohibition of Access to Undefined or Reserved Address

Note: Access to undefined or reserved addresses is prohibited.

The undefined or reserved addresses may be used to expand functions, or test registers

may have been be allocated to these address. Do not access these registers: the system’s

operation is not guaranteed if they are accessed.

Rev. 3.0, 10/02, page iv of lviii

Rev. 3.0, 10/02, page v of lviii

Configuration of this Manual

This manual comprises the following items:

1. Precautions in Relation to this Product

2. Configuration of this Manual

3. Overview

4. Table of Contents

5. Summary

6. Description of Functional Modules

• CPU and System-Control Modules

• On-chip Peripheral Modules

The configuration of the functional description of each module differs according to the module.

However, the generic style includes the following items:

i) Features

ii) I/O pins

iii) Description of Registers

iv) Description of Operation

v) Usage: Points for Caution

When designing an application system that includes this LSI, take the points for caution into

account. Each section includes points for caution in relation to the descriptions given, and points

for caution in usage are given, as required, as the final part of each section.

7. List of Registers

8. Electrical Characteristics

9. Appendix

• Product-type codes and external dimensions

• Major revisions or addenda in this version of the manual (only for revised versions)

The history of revisions is a summary of sections that have been revised and sections that have

been added to earlier versions. This does not include all of the revised contents. For details,

confirm by referring to the main description of this manual.

10.Appendix/Appendices

Rev. 3.0, 10/02, page vi of lviii

Rev. 3.0, 10/02, page vii of lviii

Preface

This LSI is a high-performance microcomputer (MCU) made up of the H8S/2000 CPU with

Hitachi's original architecture as its core, and the peripheral functions required to configure a

system.

The H8S/2000 CPU has an internal 32-bit configuration, sixteen 16-bit general registers, and a

simple and optimized instruction set for high-speed operation. The H8S/2000 CPU can handle a

16-Mbyte linear address space. The instruction set of the H8S/2000 CPU maintains upward

compatibility at the object level with the H8/300 and H8/300H CPUs. This allows the H8/300,

H8/300L, or H8/300H user to easily utilize the H8S/2000 CPU.

This LSI is equipped with ROM, RAM, a direct memory access controller (DMAC), a bus master

for a data transfer controller (DTC), a 16-bit timer pulse unit (TPU), an 8-bit timer (TMR), a

watchdog timer (WDT), a universal serial bus (USB), two types of serial communication interfaces

(SCIs), an A/D converter, a D/A converter, and I/O ports as on-chip peripheral modules for system

configuration.

A single-power flash memory (F-ZTATTM) version and masked ROM version are available for this

SI's ROM. The F-ZTAT version provides flexibility as it can be reprogrammed in no time to

cope with all situations from the early stages of mass production to full-scale mass production.

This is particularly applicable to application devices with specifications that will most probably

change.

This manual describes this SI's hardware.

Note: * F-ZTATTM is a trademark of Hitachi, Ltd.

Target Users: This manual was written for users who will be using the H8S/2215 Series in the

design of application systems. Target users are expected to understand the

fundamentals of electrical circuits, logical circuits, and microcomputers.

Objective: This manual was written to explain the hardware functions and electrical

characteristics of the H8S/2215 Series to the target users.

Refer to the H8S/2600 Series, H8S/2000 Series Programming Manual for a

detailed description of the instruction set.

Notes on reading this manual:

• In order to understand the overall functions of the chip

Read the manual according to the contents. This manual can be roughly categorized into parts

on the CPU, system control functions, peripheral functions and electrical characteristics.

• In order to understand the details of the CPU's functions

Read the H8S/2600 Series, H8S/2000 Series Programming Manual.

Rev. 3.0, 10/02, page viii of lviii

• In order to understand the details of a register when its name is known

Read the index that is the final part of the manual to find the page number of the entry on the

On-Chip I/O Register.

Examples: Register name: The following notation is used for cases when the same or a

similar function, e.g. 16-bit timer pulse unit or serial

communication, is implemented on more than one channel:

XXX_N (XXX is the register name and N is the channel

number)

Bit order: The MSB is on the left and the LSB is on the right.

Related Manuals: The latest versions of all related manuals are available from our web site.

Please ensure you have the latest versions of all documents you require.

http://www.hitachisemiconductor.com/

H8S/2215 Series manuals:

Manual Title ADE No.

H8S/2215 Series Hardware Manual This manual

H8S/2600 Series, H8S/2000 Series Programming Manual ADE-602-083

User's manuals for development tools:

Manual Title ADE No.

H8S, H8/300 Series C/C++ Compiler, Assembler, Optimizing Linkage Editor

User’s Manual ADE-702-247

H8S, H8/300 Series Simulator Debugger (for Windows) Users Manual ADE-702-085

H8S, H8/300 Series Hitachi Embedded Workshop, Hitachi Debugging

Interface Tutorial ADE-702-231

Hitachi Embedded Workshop User's Manual ADE-702-201

Rev. 3.0, 10/02, page ix of lviii

List of Items Revised or Added for This Version

Section Page Description

1.1 Overview

• On-chip memory

• ComPact Package

ROM Product Code ROM RAM Remarks

HD64F2215 256 kbytes 16 kbytes SCI boot version

F-ZTAT Version HD64F2215U 256 kbytes 16 kbytes USB boot version

HD6432215A 256 kbytes 16 kbytes In planning

HD6432215B 128 kbytes 16 kbytes 

Masked ROM

Version

HD6432215C 64 kbytes 8 kbytes 

Remarks column amended

(Incorrect) Under development

(Correct) 

1.2 Internal Block

Diagram

Figure 1.1 Internal Block

Diagram

2 Figure amended

Interrupts controller

USB

NMI

FWE*

USPND

USD+

USD-

VBUS

Note added to figure

Note: * The FWE pin is only provided in the flash memory

version.

1.3 Pin Arrangement

Figure 1.2 Pin

Arrangement (TFP-120)

3Figure amended

XTAL

VSS

NMI

FWE*

MD1

MD0

Note added to figure

Note: * The FWE pin is only provided in the flash memory

version.

Rev. 3.0, 10/02, page x of lviii

Section Page Description

1.3 Pin Arrangement

Figure 1.3 Pin

Arrangement (BP-112)

4Figure replaced

23456789 1110

BP-112

(Top view)

PA1/

A17/TxD2

PA2/

A18/RxD2

P10/

TIOCA0/

A20/VM

P11/

TIOCB0/

A21/VP

PA3/

A19/

SCK2/

SUSPND

P12/

TIOCC0/

TCLKA/

A22/RCV

P13/

TIOCD0/

TCLKB/

A23/VPO

P14/

TIOCA1/

P15/

TIOCB1/

TCLKC/

FSE0

P16/TIO

CA2/

P17/

TIOCB2/

TCLKD/

P97/

AN15/DA1

P96/

AN14/

DA0

P70/

TMRI01/

TMCI01/

P72/

TMO0/

P73/

TMO1/

P35/

SCK1/

PF3///

P74/

P32/

SCK0/

PF0/ /

(Reserve)

PD1/D9

PD4/D12

PD7/D15

VSS

PC3/A3

PC6/A6

PB1/A9

PB4/A12

PB7/A15

(Reserve)

PE6/D6

PD0/D8

PD3/D11

PD6/D14

PC1/A1

PC4/A4

PC7/A7

PB3/A11

PB6/A14

PE3/D3

PE5/D5

PE7/D7

PD5/D13

PC0/A0

PC2/A2

PB0/A8

PB5/A13

PA0/A16

PE0/D0

PE2/D2

PE4/D4

PD2/D10

VCC

PC5/A5

PB2/A10

TMS

TDI

PE1/D1

AVSS

PG4/

TDO

PG3/

TCK

P42/AN2

P43/AN3

PG1/

PG2/

PG0

USPND

Vref

P40/AN0

P41/AN1

P71/

MD2

NMI

PLLVCC

DrVCC

VBUS

AVCC

P36

PF5/

XTAL

MD0

DrVSS

USD+

P34/RxD1

P33/TxD1

P30/TxD0

PF2/

PF6/

EXTAL

VSS

MD1

XTAL48

PLLVSS

USD-

(Reserve)

P31/RxD0

PF1/

PF4/

PF7/

VCC

FWE*

EXTAL48

PLLCAP

(Reserve)

Note added

Note: *The FWE pin is only provided in the flash memory

version.

1.5 Pin Functions 11 Table amended

Pin No.

Type Symbol TFP-120 BP-112 I/O Function

System

Control FWE 69 H11 Input Pin for use by flash memory. This pin

is only used in the flash memory

version. In the mask ROM version it

should be fixed at 0.

3.4 Memory Map in Each

Operating Mode

Figure 3.1 Memory Map

in Each Operating Mode

for HD64F2215,

HD64F2215U,

and HD6432215A

61 Description amended

Figures 3.1 to 3.3 show the memory map in each operating

mode for HD64F2215, HD64F2215U, HD6432215A,

HD6432215B, and HD6432215C.

5.4.1 External Interrupts

Figure 5.2 Block Diagram

of Interrupts IRQ7 to IRQ0

83 Figure amended

(Incorrect) IRQn input

(Correct) IRQn input

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