GigaDevice Semiconductor GD32H737 Manuel utilisateur

GigaDevice Semiconductor Inc.

GD32H737/757/759

Arm® Cortex®-M7 32-bit MCU

User Manual

Revision 1.0

(May. 2023)

                                             GD32H737/757/759 User Manual 

 
Table of Contents 
Table of Contents ...........................................................................................................2
List of Figures ..............................................................................................................38 
List of Tables ................................................................................................................52 
System and memory architecture ........................................................................59 
1. Arm®Cortex®-M7 processor ..................................................................................... 59 
2. System architecture .................................................................................................. 60 
2.1. Bus matrix Region 0 ............................................................................................................. 63 
2.2. Bus matrix Region 1 ............................................................................................................. 63 
2.3. Bus matrix Region 2 ............................................................................................................. 64 
3. Memory map .............................................................................................................. 65 
3.1. On-chip SRAM memory........................................................................................................ 73 
3.2. On-chip flash memory overview ........................................................................................... 75 
4. Boot configuration..................................................................................................... 75 
5. System configuration controller (SYSCFG)............................................................. 76 
6. Timer break input lock .............................................................................................. 77 
7. AXI interconnect matrix (AXIIM) ............................................................................... 77 
7.1. Characteristics ...................................................................................................................... 77 
7.2. Function overview ................................................................................................................. 77 
8. System configuration registers................................................................................ 79 
8.1. Peripheral mode configuration register (SYSCFG_PMCFG) ............................................... 79 
8.2. EXTI sources selection register 0 (SYSCFG_EXTISS0)...................................................... 81 
8.3. EXTI sources selection register 1 (SYSCFG_EXTISS1)...................................................... 82 
8.4. EXTI sources selection register 2 (SYSCFG_EXTISS2)...................................................... 83 
8.5. EXTI sources selection register 3 (SYSCFG_EXTISS3)...................................................... 84 
8.6. Lockup control register (SYSCFG_LKCTL).......................................................................... 86 
8.7. I/O compensation control register (SYSCFG_CPSCTL) ...................................................... 87 
8.8. I/O compensation cell code configuration register (SYSCFG_CPSCCCFG) ....................... 88 
8.9. Timer input selection register 0 (SYSCFG_TIMERCISEL0)................................................. 89 
8.10. Timer input selection register 1 (SYSCFG_TIMERCISEL1)................................................. 90 
8.11. Timer input selection register 2 (SYSCFG_TIMERCISEL2)................................................. 91 
8.12. Timer input selection register 3 (SYSCFG_TIMERCISEL3)................................................. 92 
8.13. Timer input selection register 4 (SYSCFG_TIMERCISEL4)................................................. 94 
8.14. Timer input selection register 5 (SYSCFG_TIMERCISEL5)................................................. 95 
8.15. Timer input selection register 6 (SYSCFG_TIMERCISEL6)................................................. 97 
8.16. CPU ICACHE error status register(SYSCFG_CPUICAC).................................................... 98 
8.17. CPU DCACHE error status register (SYSCFG_CPUDCAC) ............................................... 99 

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8.18. FPU interrupt enable register (SYSCFG_FPUINTEN) ......................................................... 99 
8.19. SRAM configuration register 0 (SYSCFG_SRAMCFG0) ................................................... 100 
8.20. SRAM configuration register 1 (SYSCFG_SRAMCFG1) ................................................... 101
8.21. TIMERx configuration register 0 (SYSCFG_TIMERxCFG0, x=0, 7) .................................. 101 
8.22. TIMERx configuration register 1 (SYSCFG_TIMERxCFG1, x=0, 7) .................................. 104 
8.23. TIMERx configuration register 2 (SYSCFG_TIMERxCFG2, x=0, 7) .................................. 106 
8.24. TIMERx configuration register 0 (SYSCFG_TIMERxCFG0, x=1, 2, 3, 4, 22, 23, 30, 31) .. 107 
8.25. TIMERx configuration register 1 (SYSCFG_TIMERxCFG1, x=1, 2, 3, 4, 22, 23, 30, 31) .. 109 
8.26. TIMERx configuration register 2 (SYSCFG_TIMERxCFG2, x=1, 2, 3, 4, 22, 23, 30, 31) ...112 
8.27. TIMERx configuration register 0 (SYSCFG_TIMERxCFG0, x=14, 40, 41, 42, 43, 44) .......113 
8.28. TIMERx configuration register 1 (SYSCFG_TIMERxCFG1, x=14, 40, 41, 42, 43, 44).......115 
8.29. TIMERx configuration register 2 (SYSCFG_TIMERxCFG2, x=14, 40, 41, 42, 43, 44) .......116 
8.30. User configuration register (SYSCFG_USERCFG).............................................................117 
9. AXI interconnect registers.......................................................................................118 
9.1. AXI peripheral ID4 register (AXI_PERIPH_ID4) ..................................................................118 
9.2. AXI peripheral ID0 register (AXI_PERIPH_ID0) ..................................................................118 
9.3. AXI peripheral ID1 register (AXI_PERIPH_ID1) ..................................................................119 
9.4. AXI peripheral ID2 register (AXI_PERIPH_ID2) ..................................................................119 
9.5. AXI peripheral ID3 register (AXI_PERIPH_ID3) ................................................................. 120 
9.6. AXI componet ID0 register (AXI_COMP_ID0).................................................................... 120 
9.7. AXI componet ID1 register (AXI_COMP_ID1).................................................................... 120 
9.8. AXI componet ID2 register (AXI_COMP_ID2).................................................................... 121 
9.9. AXI componet ID3 register (AXI_COMP_ID3).................................................................... 121 
9.10. AXI Master Port x bus matrix issuing functionality control register (AXI_MPxBM_ISS_CTL)

9.11. AXI Master Port x bus matrix functionality control register (AXI_MPxBM_CTL) ................ 122 
9.12. AXI Master Port x long burst functionality control register (AXI_MPx_LB_CTL) ................ 123 
9.13. AXI Master Port x issuing functionality control register (AXI_MPx_ISS_CTL) ................... 123 
9.14. AXI Slave Port x functionality control register (AXI_SPx_CTL) .......................................... 124 
9.15. AXI Slave Port x AHB issuing functionality control register (AXI_SPx_AHBISS_CTL) ...... 124 
9.16. AXI Slave Port x read QOS control register (AXI_SPx_RDQOS_CTL) ............................. 125 
9.17. AXI Slave Port x write QOS control register (AXI_SPx_WRQOS_CTL) ............................ 125 
9.18. AXI Slave Port x issuing functionality control register (AXI_SPx_ISS_CTL)...................... 126 
10. Device electronic signature................................................................................. 126 
10.1. Memory density information................................................................................................ 127 
10.2. Unique device ID (96 bits) .................................................................................................. 127 
RAM ECC monitor unit (RAMECCMU)................................................................129 
1. Characteristics......................................................................................................... 129 
2. Function overview................................................................................................... 129 
3. Register definition................................................................................................... 131 
3.1. RAMECCMU global interruput register (RAMECCMU_INT) .............................................. 131 

                                             GD32H737/757/759 User Manual 

 
3.2. RAMECCMU monitor x control register (RAMECCMU_MxCTL) ....................................... 131 
3.3. RAMECCMU monitor x status register (RAMECCMU_MxSTAT)....................................... 132 
3.4. RAMECCMU monitor x failing address register (RAMECCMU_MxFADDR) ..................... 133 
3.5. RAMECCMU monitor x failing data low register (RAMECCMU_MxFDL) .......................... 134 
3.6. RAMECCMU monitor x failing data high register (RAMECCMU_MxFDH) ........................ 134 
3.7. RAMECCMU monitor x failing ECC error code register (RAMECCMU_MxFECODE) ...... 134 
Flash memory controller (FMC)..........................................................................136 
1. Overview .................................................................................................................. 136 
2. Characteristics......................................................................................................... 136 
3. Function overview................................................................................................... 136 
3.1. Flash memory architecture ................................................................................................. 136 
3.2. Read operations ................................................................................................................. 137 
3.3. Unlock the FMC_CTL and FMC_OBCTL register .............................................................. 138 
3.4. Sector erase........................................................................................................................ 139 
3.5. Mass erase ......................................................................................................................... 140 
3.6. Main flash Programming..................................................................................................... 144 
3.7. Option bytes........................................................................................................................ 145 
3.8. Sector erase/program protection ........................................................................................ 148 
3.9. Security protection .............................................................................................................. 149 
3.10. Dedicated code read protection area ................................................................................. 151 
3.11. Secure user area ................................................................................................................ 153 
3.12. Secure mode....................................................................................................................... 154 
3.13. Basic security service ......................................................................................................... 156 
3.14. Error description.................................................................................................................. 157 
3.15. FMC interrupts .................................................................................................................... 159 
4. Register definition................................................................................................... 160 
4.1.Unlock key register (FMC_KEY)......................................................................................... 160 
4.2. Option byte unlock key register (FMC_OBKEY)................................................................. 160 
4.3. Control register (FMC_CTL) ............................................................................................... 160 
4.4. Status register (FMC_STAT)............................................................................................... 162 
4.5. Address register (FMC_ADDR) .......................................................................................... 163 
4.6. Option byte control register (FMC_OBCTL) ....................................................................... 164 
4.7. Option byte status register 0 (FMC_OBSTAT0_EFT)......................................................... 165 
4.8. Option byte status register 0 (FMC_OBSTAT0_MDF)........................................................ 166 
4.9. DCRP address register (FMC_DCRPADDR_EFT) ............................................................ 168 
4.10. DCRP address register (FMC_DCRPADDR_MDF) ........................................................... 169 
4.11. Secure address register (FMC_SCRADDR_EFT).............................................................. 170 
4.12. Secure address register (FMC_SCRADDR_MDF)............................................................. 170 
4.13. Erase/program protection register (FMC_WP_EFT) .......................................................... 171 
4.14. Erase/program protection register (FMC_WP_MDF) ......................................................... 172 
4.15. Boot address register (FMC_BTADDR_EFT) ..................................................................... 173 
4.16. Boot address register (FMC_BTADDR_MDF) .................................................................... 173 

                                             GD32H737/757/759 User Manual 

 
4.17. Option byte status register 1 (FMC_OBSTAT1_EFT)......................................................... 174 
4.18. Option byte status register 1 (FMC_OBSTAT1_MDF)........................................................ 175 
4.19. NO-RTDEC area register (FMC_NODEC) ......................................................................... 176 
4.20. AES IV register (FMC_AESIVx_EFT) (x = 0…2)................................................................ 176 
4.21. AES IV register (FMC_AESIVx_MDF) (x = 0…2)............................................................... 177 
4.22. Product ID register x (FMC_PIDx) (x = 0,1)........................................................................ 177 
Electronic fuse (EFUSE)......................................................................................179 
1. Overview .................................................................................................................. 179 
2. Characteristics......................................................................................................... 179 
3. Function overview................................................................................................... 179 
3.1. Block diagram ..................................................................................................................... 179 
3.2. Efuse macro description ..................................................................................................... 180 
3.3. Read operation ................................................................................................................... 183 
3.4. Program operation .............................................................................................................. 184 
3.5. AES key CRC function........................................................................................................ 184 
3.6. EFUSE interrupts ................................................................................................................ 185 
4. Register definition................................................................................................... 187 
4.1. Control register (EFUSE_CTL) ........................................................................................... 187 
4.2. Address register (EFUSE_ADDR) ...................................................................................... 188 
4.3. Status register (EFUSE_STAT) .......................................................................................... 189 
4.4. Status flag clear register (EFUSE_STATC) ........................................................................ 189 
4.5. User control register (EFUSE_USER_CTL) ....................................................................... 190 
4.6. MCU reserved register (EFUSE_MCU_RSV) .................................................................... 192 
4.7. Debug password register x (EFUSE_DPx) (x = 0,1) .......................................................... 194 
4.8. Firmware AES key register x (EFUSE_AES_KEYx) (x = 0…3) ......................................... 195 
4.9. User data register x (EFUSE_USER_DATAx) (x = 0…3) ................................................... 195 
Power management unit (PMU) ..........................................................................196 
1. Overview .................................................................................................................. 196 
2. Characteristics......................................................................................................... 196 
3. Function overview................................................................................................... 197 
3.1. Backup domain ................................................................................................................... 197 
3.2. VDD / VDDA power domain .................................................................................................... 199 
3.3. 0.9V power domain............................................................................................................. 203 
3.4. Power saving modes .......................................................................................................... 208 
4. Register definition................................................................................................... 210 
4.1. Control register 0 (PMU_CTL0) .......................................................................................... 210 
4.2. Control and status register (PMU_CS) ................................................................................211 
4.3. Control register 1 (PMU_CTL1) .......................................................................................... 213 
4.4. Control register 2 (PMU_CTL2) .......................................................................................... 215 
4.5. Control register 3 (PMU_CTL3) .......................................................................................... 216 

                                             GD32H737/757/759 User Manual 

 
4.6. Parameter register (PMU_PAR) ......................................................................................... 217 
Reset and clock unit (RCU).................................................................................219 
1. Reset control unit (RCTL) ....................................................................................... 219 
1.1. Overview ............................................................................................................................. 219 
1.2. Function overview ............................................................................................................... 219 
2. Clock control unit (CCTL) ....................................................................................... 220 
2.1. Overview ............................................................................................................................. 220 
2.2. Characteristics .................................................................................................................... 224 
2.3. Function overview ............................................................................................................... 224 
3. Register definition................................................................................................... 230 
3.1. Control register (RCU_CTL) ............................................................................................... 230 
3.2. PLL0 register (RCU_PLL0)................................................................................................. 232 
3.3. Clock configuration register 0 (RCU_CFG0) ...................................................................... 234 
3.4. Clock interrupt register (RCU_INT) .................................................................................... 236 
3.5. AHB1 reset register (RCU_AHB1RST) .............................................................................. 239 
3.6. AHB2 reset register (RCU_AHB2RST) .............................................................................. 241 
3.7. AHB3 reset register (RCU_AHB3RST) .............................................................................. 242 
3.8. AHB4 reset register (RCU_AHB4RST) .............................................................................. 243 
3.9. APB1 reset register (RCU_APB1RST) ............................................................................... 245 
3.10. APB2 reset register (RCU_APB2RST) ............................................................................... 248 
3.11. APB3 reset register (RCU_APB3RST) ............................................................................... 251 
3.12. APB4 reset register (RCU_APB4RST) ............................................................................... 252 
3.13. AHB1 enable register (RCU_AHB1EN) .............................................................................. 253 
3.14. AHB2 enable register (RCU_AHB2EN) .............................................................................. 255 
3.15. AHB3 enable register (RCU_AHB3EN) .............................................................................. 256 
3.16. AHB4 enable register (RCU_AHB4EN) .............................................................................. 258 
3.17. APB1 enable register (RCU_APB1EN) .............................................................................. 259 
3.18. APB2 enable register (RCU_APB2EN) .............................................................................. 263 
3.19. APB3 enable register (RCU_APB3EN) .............................................................................. 266 
3.20. APB4 enable register (RCU_APB4EN) .............................................................................. 266 
3.21. AHB1 sleep mode enable register (RCU_AHB1SPEN) ..................................................... 267 
3.22. AHB2 sleep mode enable register (RCU_AHB2SPEN) ..................................................... 270 
3.23. AHB3 sleep mode enable register (RCU_AHB3SPEN) ..................................................... 271 
3.24. AHB4 sleep mode enable register (RCU_AHB4SPEN) ..................................................... 273 
3.25. APB1 sleep mode enable register (RCU_APB1SPEN)...................................................... 274 
3.26. APB2 sleep mode enable register (RCU_APB2SPEN)...................................................... 278 
3.27. APB3 sleep mode enable register (RCU_APB3SPEN)...................................................... 281 
3.28. APB4 sleep mode enable register (RCU_APB4SPEN)...................................................... 281 
3.29. Backup domain control register (RCU_BDCTL) ................................................................. 282 
3.30. Reset source/clock register (RCU_RSTSCK) .................................................................... 284 
3.31. PLL clock additional control register (RCU_PLLADDCTL) ................................................. 286 
3.32. PLL1 register (RCU_PLL1)................................................................................................. 288 

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3.33. PLL2 register (RCU_PLL2)................................................................................................. 290 
3.34. Clock configuration register 1 (RCU_CFG1) ...................................................................... 292 
3.35. Clock configuration register 2 (RCU_CFG2) ...................................................................... 294 
3.36. Clock configuration register 3 (RCU_CFG3) ...................................................................... 296 
3.37. PLL all configuration register (RCU_PLLALL) .................................................................... 298 
3.38. PLL0 fraction configuration register (RCU_PLL0FRA) ....................................................... 300 
3.39. PLL1 fraction configuration register (RCU_PLL1FRA) ....................................................... 300 
3.40. PLL2 fraction configuration register (RCU_PLL2FRA) ....................................................... 301 
3.41. Additional clock control register 0 (RCU_ADDCTL0) ......................................................... 302 
3.42. Additional clock control register 1(RCU_ADDCTL1) .......................................................... 303 
3.43. Additional clock interrupt register (RCU_ADDINT)............................................................. 304 
3.44. Clock configuration register 4 (RCU_CFG4) ...................................................................... 306 
3.45. USB clock control register (RCU_USBCLKCTL)................................................................ 307 
3.46. PLLUSB configuration register (RCU_PLLUSBCFG)......................................................... 309 
3.47. APB2 additional reset register (RCU_ADDAPB2RST)....................................................... 310 
3.48. APB2 additional enable register (RCU_ADDAPB2EN) .......................................................311 
3.49. APB2 additional sleep enable register (RCU_ADDAPB2SPEN)........................................ 312 
3.50. Clock configuration register 5 (RCU_CFG5) ...................................................................... 312 
Clock trim controller (CTC) .................................................................................315 
1. Overview .................................................................................................................. 315 
2. Characteristics......................................................................................................... 315 
3. Function overview ................................................................................................... 315 
3.1. REF sync pulse generator .................................................................................................. 316 
3.2. CTC trim counter................................................................................................................. 316 
3.3. Frequency evaluation and automatically trim process........................................................ 317 
3.4. Software program guide ..................................................................................................... 318 
4. Register definition ................................................................................................... 320 
4.1. Control register 0 (CTC_CTL0)........................................................................................... 320 
4.2. Control register 1 (CTC_CTL1)........................................................................................... 321 
4.3. Status register (CTC_STAT) ............................................................................................... 322 
4.4. Interrupt clear register (CTC_INTC) ................................................................................... 324 
Interrupt / event controller (EXTI).......................................................................326 
1. Overview .................................................................................................................. 326 
2. Characteristics......................................................................................................... 326 
3. Interrupts function overview................................................................................... 326 
4. External interrupt and event (EXTI) block diagram ............................................... 333 
5. External interrupt and event function overview .................................................... 333 
6. Register definition................................................................................................... 336 
6.1. Interrupt enable register 0 (EXTI_INTEN0) ........................................................................ 336 

                                             GD32H737/757/759 User Manual 

 
6.2. Event enable register 0 (EXTI_EVEN0) ............................................................................. 336 
6.3. Rising edge trigger enable register 0 (EXTI_RTEN0) ........................................................ 336 
6.4. Falling edge trigger enable register 0 (EXTI_FTEN0) ........................................................ 337 
6.5. Software interrupt event register 0 (EXTI_SWIEV0) .......................................................... 337 
6.6. Pending register 0 (EXTI_PD0) .......................................................................................... 338 
6.7. Interrupt enable register 1 (EXTI_INTEN1) ........................................................................ 338 
6.8. Event enable register 1 (EXTI_EVEN1) ............................................................................. 339 
6.9. Rising edge trigger enable register 1 (EXTI_RTEN1) ........................................................ 339 
6.10. Falling edge trigger enable register 1 (EXTI_FTEN1) ........................................................ 339 
6.11. Software interrupt event register 1 (EXTI_SWIEV1) .......................................................... 340 
6.12. Pending register 1 (EXTI_PD1) .......................................................................................... 340 
Trigger selection controller (TRIGSEL)..............................................................342 
1. Overview .................................................................................................................. 342 
2. Characteristics......................................................................................................... 342 
3. Function overview ................................................................................................... 342 
4. Internal connect....................................................................................................... 343 
5. Register definition ................................................................................................... 354 
5.1. Trigger selection for EXTOUT0 register (TRIGSEL_EXTOUT0) ........................................ 354 
5.2. Trigger selection for EXTOUT1 register (TRIGSEL_EXTOUT1)........................................ 354 
5.3. Trigger selection for EXTOUT2 register (TRIGSEL_EXTOUT2) ........................................ 355 
5.4. Trigger selection for EXTOUT3 register (TRIGSEL_EXTOUT3)........................................ 356 
5.5. Trigger selection for ADC0 register (TRIGSEL_ADC0) ...................................................... 356 
5.6. Trigger selection for ADC1 register (TRIGSEL_ADC1) ...................................................... 357 
5.7. Trigger selection for ADC2 register (TRIGSEL_ADC2) ...................................................... 358 
5.8. Trigger selection for DAC_OUT0 register (TRIGSEL_DACOUT0)..................................... 358 
5.9. Trigger selection for DAC_OUT1 register (TRIGSEL_DACOUT1)..................................... 359 
5.10. Trigger selection for TIMER0_BRKIN register (TRIGSEL_TIMER0BRKIN) ...................... 360 
5.11. Trigger selection for TIMER7_BRKIN register (TRIGSEL_TIMER7BRKIN) ...................... 360 
5.12. Trigger selection for TIMER14_BRKIN register (TRIGSEL_TIMER14BRKIN) .................. 361 
5.13. Trigger selection for TIMER15_BRKIN register (TRIGSEL_TIMER15BRKIN) .................. 362 
5.14. Trigger selection for TIMER16_BRKIN register (TRIGSEL_TIMER16BRKIN) .................. 363 
5.15. Trigger selection for TIMER40_BRKIN register (TRIGSEL_TIMER40BRKIN) .................. 363 
5.16. Trigger selection for TIMER41_BRKIN register (TRIGSEL_TIMER41BRKIN) .................. 364 
5.17. Trigger selection for TIMER42_BRKIN register (TRIGSEL_TIMER42BRKIN) .................. 365 
5.18. Trigger selection for TIMER43_BRKIN register (TRIGSEL_TIMER43BRKIN) .................. 365 
5.19. Trigger selection for TIMER44_BRKIN register (TRIGSEL_TIMER44BRKIN) .................. 366 
5.20. Trigger selection for CAN0 register (TRIGSEL_CAN0) ...................................................... 366 
5.21. Trigger selection for CAN1 register (TRIGSEL_CAN1) ...................................................... 367 
5.22. Trigger selection for CAN2 register (TRIGSEL_CAN2) ...................................................... 368 
5.23. Trigger selection for LPDTS register (TRIGSEL_LPDTS).................................................. 368 
5.24. Trigger selection for TIMER0_ETI register (TRIGSEL_TIMER0ETI) ................................. 369 

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5.25. Trigger selection for TIMER1_ETI register (TRIGSEL_TIMER1ETI) ................................. 369 
5.26. Trigger selection for TIMER2_ETI register (TRIGSEL_TIMER2ETI) ................................. 370 
5.27. Trigger selection for TIMER3_ETI register (TRIGSEL_TIMER3ETI) ................................. 371 
5.28. Trigger selection for TIMER4_ETI register (TRIGSEL_TIMER4ETI) ................................. 371 
5.29. Trigger selection for TIMER7_ETI register (TRIGSEL_TIMER7ETI) ................................. 372 
5.30. Trigger selection for TIMER22_ETI register (TRIGSEL_TIMER22ETI) ............................. 372 
5.31. Trigger selection for TIMER23_ETI register (TRIGSEL_TIMER23ETI) ............................. 373 
5.32. Trigger selection for TIMER30_ETI register (TRIGSEL_TIMER30ETI) ............................. 374 
5.33. Trigger selection for TIMER31_ETI register (TRIGSEL_TIMER31ETI) ............................. 374 
5.34. Trigger selection for EDOUT register (TRIGSEL_EDOUT)................................................ 375 
5.35. Trigger selection for HPDF_ITRG register (TRIGSEL_HPDF) ........................................... 375 
5.36. Trigger selection for TIMER0_ITI14 register (TRIGSEL_TIMER0ITI14) ............................ 376 
5.37. Trigger selection for TIMER1_ITI14 register (TRIGSEL_TIMER1ITI14) ............................ 377 
5.38. Trigger selection for TIMER2_ITI14 register (TRIGSEL_TIMER2ITI14) ............................ 377 
5.39. Trigger selection for TIMER3_ITI14 register (TRIGSEL_TIMER3ITI14) ............................ 378
5.40. Trigger selection for TIMER4_ITI14 register (TRIGSEL_TIMER4ITI14) ............................ 378 
5.41. Trigger selection for TIMER7_ITI14 register (TRIGSEL_TIMER7ITI14) ............................ 379 
5.42. Trigger selection for TIMER14_ITI14 register (TRIGSEL_TIMER14ITI14) ........................ 380 
5.43. Trigger selection for TIMER22_ITI14 register (TRIGSEL_TIMER22ITI14) ........................ 380 
5.44. Trigger selection for TIMER23_ITI14 register (TRIGSEL_TIMER23ITI14) ........................ 381 
5.45. Trigger selection for TIMER30_ITI14 register (TRIGSEL_TIMER30ITI14) ........................ 381 
5.46. Trigger selection for TIMER31_ITI14 register (TRIGSEL_TIMER31ITI14) ........................ 382 
5.47. Trigger selection for TIMER40_ITI14 register (TRIGSEL_TIMER40ITI14) ........................ 383 
5.48. Trigger selection for TIMER41_ITI14 register (TRIGSEL_TIMER41ITI14) ........................ 383 
5.49. Trigger selection for TIMER42_ITI14 register (TRIGSEL_TIMER42ITI14) ........................ 384 
5.50. Trigger selection for TIMER43_ITI14 register (TRIGSEL_TIMER43ITI14) ........................ 384 
5.51. Trigger selection for TIMER44_ITI14 register (TRIGSEL_TIMER44ITI14) ........................ 385 
General-purpose and alternate-function I/Os (GPIO and AFIO)....................387 
1. Overview............................................................................................................... 387 
2. Characteristics..................................................................................................... 387 
3. Function overview................................................................................................ 387 
3.1. GPIO pin configuration ....................................................................................................... 389 
3.2. External interrupt/event lines .............................................................................................. 390 
3.3. Alternate functions (AF) ...................................................................................................... 390 
3.4. Additional functions............................................................................................................. 390 
3.5. Input configuration .............................................................................................................. 390 
3.6. Output configuration ........................................................................................................... 390 
3.7. Analog configuration ........................................................................................................... 391 
3.8. Alternate function (AF) configuration .................................................................................. 392 
3.9. GPIO locking function ......................................................................................................... 392 
3.10. GPIO single cycle toggle function....................................................................................... 393 
3.11. I/O compensation unit ......................................................................................................... 393 

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3.12. Analog configuration for ADC ............................................................................................. 393 
3.13. Input filtering ....................................................................................................................... 394 
4. Register definition................................................................................................ 397 
4.1. Port control register (GPIOx_CTL, x=A...H, J, K) ............................................................... 397 
4.2. Port output mode register (GPIOx_OMODE, x=A…H, J, K) .............................................. 399 
4.3. Port output speed register (GPIOx_OSPD, x=A...H, J, K).................................................. 400 
4.4. Port pull-up/down register (GPIOx_PUD, x=A…H, J, K) .................................................... 402 
4.5. Port input status register (GPIOx_ISTAT, x=A…H, J, K) .................................................... 404 
4.6. Port output control register (GPIOx_OCTL, x=A…H, J, K)................................................. 404 
4.7. Port bit operate register (GPIOx_BOP, x=A...H, J, K) ........................................................ 405 
4.8. Port configuration lock register (GPIOx_LOCK, x=A...H, J, K)........................................... 405 
4.9. Alternate function selected register 0 (GPIOx_AFSEL0, x=A...H, J, K) ............................. 406 
4.10. Alternate function selected register 1 (GPIOx_AFSEL1, x=A…H, J, K)............................. 407 
4.11. Bit clear register (GPIOx_BC, x=A…H, J, K)...................................................................... 408 
4.12. Port bit toggle register (GPIOx_TG, x=A…H, J, K) ............................................................ 409 
4.13. Input filtering register (GPIOx_IFL, x=A...H, J, K) .............................................................. 409 
4.14. Input filtering type register (GPIOx_IFTP, x=A...H, J, K) .................................................... 410 
Cyclic redundancy checks management unit (CRC) .....................................412 
1. Overview ............................................................................................................... 412 
2. Characteristics ..................................................................................................... 412 
3. Function overview................................................................................................ 413 
4. Register definition................................................................................................ 414 
4.1. Data register (CRC_DATA) ................................................................................................. 414 
4.2. Free data register (CRC_FDATA)....................................................................................... 414 
4.3. Control register (CRC_CTL) ............................................................................................... 415 
4.4. Initialization data register (CRC_IDATA)............................................................................. 415 
4.5. Polynomial register (CRC_POLY)....................................................................................... 416 
True random number generator (TRNG).........................................................417 
1. Overview ............................................................................................................... 417 
2. Characteristics ..................................................................................................... 417 
3. Function overview................................................................................................ 418 
3.1. LFSR................................................................................................................................... 418 
3.2. Post processing .................................................................................................................. 419 
3.3. Conditioning ........................................................................................................................ 419 
3.4. Output FIFO ........................................................................................................................ 419 
3.5. Health tests ......................................................................................................................... 420 
3.6. NIST mode state ................................................................................................................. 421 
3.7. Operation flow..................................................................................................................... 421 
3.8. Error flags ........................................................................................................................... 422 
3.9. Low power usage................................................................................................................ 422 

Ce manuel convient aux modèles suivants

Table des matières

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