GigaDevice Semiconductor GD32E23 Series Manuel utilisateur

GigaDevice Semiconductor Inc.

GD32E23x

Arm®Cortex®-M23 32-bit MCU

User Manual

Revision 1.5

(Jul. 2022)

 GD32E23x User Manual

 
Table of Contents 
Table of Contents...........................................................................................................2 
List of Figures ..............................................................................................................13 
List of Table..................................................................................................................19 
System and memory architecture ........................................................................21 
1. Arm®Cortex®-M23 processor ................................................................................... 21 
2. System architecture .................................................................................................. 22 
3. Memory map .............................................................................................................. 23 
3.1. On-chip SRAM memory........................................................................................................ 26 
3.2. On-chip Flash memory ......................................................................................................... 26 
4. Boot configuration..................................................................................................... 27 
5. System configuration registers (SYSCFG) .............................................................. 28 
5.1. System configuration register 0 (SYSCFG_CFG0) .............................................................. 28 
5.2. EXTI sources selection register 0 (SYSCFG_EXTISS0)...................................................... 31 
5.3. EXTI sources selection register 1 (SYSCFG_EXTISS1)...................................................... 32 
5.4. EXTI sources selection register 2 (SYSCFG_EXTISS2)...................................................... 33 
5.5. EXTI sources selection register 3 (SYSCFG_EXTISS3)...................................................... 35 
5.6. System configuration register 2 (SYSCFG_CFG2) .............................................................. 38 
5.7. IRQ Latency register (SYSCFG_CPU_IRQ_LAT)................................................................ 39 
6. Device electronic signature...................................................................................... 39 
6.1. Memory density information.................................................................................................. 40 
6.2. Unique device ID (96 bits) .................................................................................................... 40 
Flash memory controller (FMC)............................................................................42 
1. Overview .................................................................................................................... 42 
2. Characteristics........................................................................................................... 42 
3. Function overview..................................................................................................... 42 
3.1. Flash memory architecture ................................................................................................... 42 
3.2. Read operations ................................................................................................................... 43 
3.3. Unlock the FMC_CTL register .............................................................................................. 44 
3.4. Page erase............................................................................................................................ 44 
3.5. Mass erase ........................................................................................................................... 46 
3.6. Main flash programming ....................................................................................................... 47 
3.7. OTP programming ................................................................................................................ 49 
3.8. Option byte erase ................................................................................................................. 50 
3.9. Option byte programming ..................................................................................................... 50 
3.10. Option byte description......................................................................................................... 51 

 GD32E23x User Manual

 
3.11. Page erase/Program protection............................................................................................ 52 
3.12. Security protection................................................................................................................ 52 
4. Register definition..................................................................................................... 54 
4.1. Wait state register (FMC_WS).............................................................................................. 54 
4.2. Unlock key register (FMC_KEY)........................................................................................... 54 
4.3. Option byte unlock key register (FMC_OBKEY)................................................................... 55 
4.4. Status register (FMC_STAT)................................................................................................. 55 
4.5. Control register (FMC_CTL)................................................................................................. 56 
4.6. Address register (FMC_ADDR) ............................................................................................ 58 
4.7. Option byte status register (FMC_OBSTAT)......................................................................... 58 
4.8. Write protection register (FMC_WP)..................................................................................... 59 
4.9. Product ID register (FMC_PID)............................................................................................. 59 
Power management unit (PMU)............................................................................60 
1. Overview .................................................................................................................... 60 
2. Characteristics........................................................................................................... 60 
3. Function overview..................................................................................................... 60 
3.1. Backup domain..................................................................................................................... 61 
3.2. VDD / VDDA power domain...................................................................................................... 62 
3.3. 1.2V power domain............................................................................................................... 64 
3.4. Power saving modes ............................................................................................................ 64 
4. PMU registers ............................................................................................................ 67 
4.1. Control register (PMU_CTL)................................................................................................. 67 
4.2. Control and status register (PMU_CS)................................................................................. 68 
Reset and clock unit (RCU)...................................................................................72 
1. Reset control unit (RCTL) ......................................................................................... 72 
1.1. Overview............................................................................................................................... 72 
1.2. Function overview................................................................................................................. 72 
2. Clock control unit (CCTL) ......................................................................................... 73 
2.1. Overview............................................................................................................................... 73 
2.2. Characteristics...................................................................................................................... 75 
2.3. Function overview................................................................................................................. 75 
3. Register definition..................................................................................................... 79 
3.1. Control register 0 (RCU_CTL0)............................................................................................ 79 
3.2. Configuration register 0 (RCU_CFG0) ................................................................................. 80 
3.3. Interrupt register (RCU_INT) ................................................................................................ 84 
3.4. APB2 reset register (RCU_APB2RST)................................................................................. 87 
3.5. APB1 reset register (RCU_APB1RST)................................................................................. 88 
3.6. AHB enable register (RCU_AHBEN).................................................................................... 90 
3.7. APB2 enable register (RCU_APB2EN) ................................................................................ 91 
3.8. APB1 enable register (RCU_APB1EN) ................................................................................ 93 

 GD32E23x User Manual

 
3.9. Backup domain control register (RCU_BDCTL)................................................................... 94 
3.10. Reset source /clock register (RCU_RSTSCK) ..................................................................... 96 
3.11. AHB reset register (RCU_AHBRST)..................................................................................... 97 
3.12. Configuration register 1 (RCU_CFG1) ................................................................................. 98 
3.13. Configuration register 2 (RCU_CFG2) ................................................................................. 99 
3.14. Control register 1 (RCU_CTL1).......................................................................................... 100 
3.15. Voltage key register (RCU_VKEY) ..................................................................................... 101 
3.16. Deep-sleep mode voltage register (RCU_DSV)................................................................. 101 
Interrupt/event controller (EXTI).........................................................................103 
1. Overview .................................................................................................................. 103 
2. Characteristics......................................................................................................... 103 
3. Interrupts function overview................................................................................... 103 
4. External interrupt and event (EXTI) block diagram ............................................... 106 
5. External interrupt and Event function overview.................................................... 106 
6. Register definition................................................................................................... 109 
6.1. Interrupt enable register (EXTI_INTEN) ............................................................................. 109 
6.2. Event enable register (EXTI_EVEN) .................................................................................. 109 
6.3. Rising edge trigger enable register (EXTI_RTEN) ..............................................................110 
6.4. Falling edge trigger enable register (EXTI_FTEN)..............................................................110 
6.5. Software interrupt event register (EXTI_SWIEV) ................................................................111 
6.6. Pending register (EXTI_PD) ................................................................................................112 
General-purpose and alternate-function I/Os (GPIO and AFIO)....................... 113 
1. Overview ...................................................................................................................113 
2. Characteristics..........................................................................................................113 
3. Function overview....................................................................................................113 
3.1. GPIO pin configuration ........................................................................................................114 
3.2. Alternate functions (AF).......................................................................................................115 
3.3. Additional functions..............................................................................................................115 
3.4. Input configuration ...............................................................................................................115 
3.5. Output configuration ............................................................................................................116 
3.6. Analog configuration............................................................................................................116 
3.7. Alternate function (AF) configuration...................................................................................117 
3.8. GPIO locking function..........................................................................................................118 
3.9. GPIO single cycle toggle function........................................................................................118 
4. Register definition....................................................................................................119 
4.1. Port control register (GPIOx_CTL, x=A..C,F)......................................................................119 
4.2. Port output mode register (GPIOx_OMODE, x=A..C,F)..................................................... 120 
4.3. Port output speed register (GPIOx_OSPD, x=A..C,F)........................................................ 122 
4.4. Port pull-up/down register (GPIOx_PUD, x=A..C,F)........................................................... 124 

 GD32E23x User Manual

 
4.5. Port input status register (GPIOx_ISTAT, x=A..C,F)........................................................... 125 
4.6. Port output control register (GPIOx_OCTL, x=A..C,F) ....................................................... 126 
4.7. Port bit operate register (GPIOx_BOP, x=A..C,F)............................................................... 126 
4.8. Port configuration lock register (GPIOx_LOCK, x=A,B) ..................................................... 127 
4.9. Alternate function selected register 0 (GPIOx_AFSEL0, x=A,B,C).................................... 128 
4.10. Alternate function selected register 1 (GPIOx_AFSEL1, x=A,B,C).................................... 129 
4.11. Bit clear register (GPIOx_BC, x=A..C,F) ............................................................................ 130 
4.12. Port bit toggle register (GPIOx_TG, x=A..C,F)................................................................... 130 
Cyclic redundancy checks management unit (CRC) ........................................132 
1. Overview .................................................................................................................. 132 
2. Characteristics......................................................................................................... 132 
3. Function overview................................................................................................... 133 
4. Register definition................................................................................................... 135 
4.1. Data register (CRC_DATA)................................................................................................. 135 
4.2. Free data register (CRC_FDATA)....................................................................................... 135 
4.3. Control register (CRC_CTL)............................................................................................... 136 
4.4. Initialization data register (CRC_IDATA)............................................................................. 137 
4.5. Polynomial register (CRC_POLY)....................................................................................... 137 
Direct memory access controller (DMA)............................................................138 
1. Overview .................................................................................................................. 138 
2. Characteristics......................................................................................................... 138 
3. Block diagram.......................................................................................................... 139 
4. Function overview................................................................................................... 139 
4.1. DMA operation.................................................................................................................... 139 
4.2. Peripheral handshake......................................................................................................... 141 
4.3. Arbitration............................................................................................................................ 142 
4.4. Address generation............................................................................................................. 142 
4.5. Circular mode...................................................................................................................... 142 
4.6. Memory to memory mode................................................................................................... 142 
4.7. Channel configuration......................................................................................................... 143 
4.8. Interrupt............................................................................................................................... 143 
4.9. DMA request mapping ........................................................................................................ 144 
5. Register definition................................................................................................... 147 
5.1. Interrupt flag register (DMA_INTF)..................................................................................... 147 
5.2. Interrupt flag clear register (DMA_INTC)............................................................................ 147 
5.3. Channel x control register (DMA_CHxCTL) ....................................................................... 148 
5.4. Channel x counter register (DMA_CHxCNT)...................................................................... 150 
5.5. Channel x peripheral base address register (DMA_CHxPADDR)...................................... 151 
5.6. Channel x memory base address register (DMA_CHxMADDR)........................................ 151 

 GD32E23x User Manual

 
Debug (DBG) ........................................................................................................153 
1. Overview .................................................................................................................. 153 
2. SW function overview ............................................................................................. 153 
2.1. Pin assignment ................................................................................................................... 153 
3. Debug hold function overview................................................................................ 153 
3.1. Debug support for power saving mode............................................................................... 153 
3.2. Debug support for TIMER, I2C, RTC, WWDGT and FWDGT............................................ 154 
4. Register definition................................................................................................... 155 
4.1. ID code register (DBG_ID).................................................................................................. 155 
4.2. Control register 0 (DBG_CTL0).......................................................................................... 155 
4.3. Control register 1 (DBG_CTL1).......................................................................................... 157 
Analog to digital converter (ADC)...................................................................159 
1. Overview............................................................................................................... 159 
2. Characteristics..................................................................................................... 159 
3. Pins and internal signals..................................................................................... 160 
4. Function overview................................................................................................ 161 
4.1. Foreground calibration function.......................................................................................... 161 
4.2. Dual clock domain architecture........................................................................................... 162 
4.3. ADC enable......................................................................................................................... 162 
4.4. Routine sequence............................................................................................................... 162 
4.5. Operation mode.................................................................................................................. 162 
4.6. Conversion result threshold monitor function ..................................................................... 165 
4.7. Data storage mode ............................................................................................................. 165 
4.8. Sample time configuration .................................................................................................. 167 
4.9. External trigger configuration.............................................................................................. 167 
4.10. DMA request ....................................................................................................................... 167 
4.11. ADC internal channels........................................................................................................ 167 
4.12. Programmable resolution (DRES) - fast conversion mode ................................................ 168 
4.13. On-chip hardware oversampling......................................................................................... 168 
4.14. ADC interrupts .................................................................................................................... 171 
5. Register definition................................................................................................ 172 
5.1. Status register (ADC_STAT)............................................................................................... 172 
5.2. Control register 0 (ADC_CTL0) .......................................................................................... 172 
5.3. Control register 1 (ADC_CTL1) .......................................................................................... 174 
5.4. Sample time register 0 (ADC_SAMPT0) ............................................................................ 175 
5.5. Sample time register 1 (ADC_SAMPT1) ............................................................................ 176 
5.6. Watchdog low threshold register (ADC_WDLT) ................................................................. 177 
5.7. Routine sequence register 0 (ADC_RSQ0)........................................................................ 177 
5.8. Routine sequence register 1 (ADC_RSQ1)........................................................................ 178 
5.9. Routine sequence register 2 (ADC_RSQ2)........................................................................ 179 

 GD32E23x User Manual

 
5.10. Routine data register (ADC_RDATA).................................................................................. 179 
5.11. Oversampling control register (ADC_OVSAMPCTL) ......................................................... 180 
Comparator (CMP)............................................................................................182 
1. Introduction.......................................................................................................... 182 
2. Main features........................................................................................................ 182 
3. Function description............................................................................................ 182 
3.1. CMP clock and reset........................................................................................................... 183 
3.2. CMP I/O configuration......................................................................................................... 183 
3.3. CMP operating mode.......................................................................................................... 183 
3.4. CMP hysteresis................................................................................................................... 184 
3.5. CMP register write protection ............................................................................................. 184 
4. CMP registers....................................................................................................... 185 
4.1. Control/status register (CMP_CS)...................................................................................... 185 
Watchdog timer (WDGT) ..................................................................................187 
1. Free watchdog timer (FWDGT)............................................................................ 187 
1.1. Overview............................................................................................................................ 187 
1.2. Characteristics.................................................................................................................. 187 
1.3. Function overview ............................................................................................................ 187 
1.4. Register definition ............................................................................................................ 190 
2. Window watchdog timer (WWDGT)..................................................................... 194 
2.1. Overview............................................................................................................................ 194 
2.2. Characteristics.................................................................................................................. 194 
2.3. Function overview ............................................................................................................ 194 
2.4. Register definition ............................................................................................................ 197 
Real-time clock(RTC)........................................................................................199 
1. Overview............................................................................................................... 199 
2. Characteristics..................................................................................................... 199 
3. Function overview................................................................................................ 200 
3.1. Block diagram..................................................................................................................... 200 
3.2. Clock source and prescalers .............................................................................................. 201 
3.3. Shadow registers introduction ............................................................................................ 201 
3.4. Configurable and field maskable alarm .............................................................................. 201 
3.5. RTC initialization and configuration .................................................................................... 202 
3.6. Calendar reading ................................................................................................................ 203 
3.7. Resetting the RTC .............................................................................................................. 204 
3.8. RTC shift function ............................................................................................................... 205 
3.9. RTC reference clock detection ........................................................................................... 205 
3.10. RTC smooth digital calibration............................................................................................ 206 
3.11. Time-stamp function (Only for GD32E230xx devices) ....................................................... 208 

 GD32E23x User Manual

 
3.12. Tamper detection ................................................................................................................ 208 
3.13. Calibration clock output ...................................................................................................... 209 
3.14. Alarm output........................................................................................................................ 209 
3.15. RTC power saving mode management.............................................................................. 210 
3.16. RTC interrupts..................................................................................................................... 210 
4. Register definition................................................................................................ 212 
4.1. Time register (RTC_TIME).................................................................................................. 212 
4.2. Date register (RTC_DATE)................................................................................................. 212 
4.3. Control register (RTC_CTL)................................................................................................ 213 
4.4. Status register (RTC_STAT) ............................................................................................... 217 
4.5. Prescaler register (RTC_PSC) ........................................................................................... 220 
4.6. Alarm 0 time and date register (RTC_ALRM0TD).............................................................. 220 
4.7. Write protection key register (RTC_WPK).......................................................................... 221 
4.8. Sub second register (RTC_SS) .......................................................................................... 222 
4.9. Shift function control register (RTC_SHIFTCTL)................................................................ 222 
4.10. Time of time stamp register (RTC_TTS)............................................................................. 223 
4.11. Date of time stamp register (RTC_DTS)............................................................................. 224 
4.12. Sub second of time stamp register (RTC_SSTS)............................................................... 224 
4.13. High resolution frequency compensation register (RTC_HRFC) ....................................... 225 
4.14. Tamper register (RTC_TAMP) ............................................................................................ 226 
4.15. Alarm 0 sub second register (RTC_ALRM0SS) ................................................................. 230 
4.16. Backup registers (RTC_BKPx) (x=0..4).............................................................................. 231 
Timer (TIMERx) .................................................................................................232 
1. Advanced timer (TIMERx, x=0)............................................................................ 233 
1.1. Overview............................................................................................................................. 233 
1.2. Characteristics.................................................................................................................... 233 
1.3. Block diagram..................................................................................................................... 234 
1.4. Function overview............................................................................................................... 235 
1.5. TIMERx registers(x=0)........................................................................................................ 262 
2. General level0 timer (TIMERx, x=2)..................................................................... 290 
2.1. Overview............................................................................................................................. 290 
2.2. Characteristics.................................................................................................................... 290 
2.3. Block diagram..................................................................................................................... 290 
2.4. Function overview............................................................................................................... 291 
2.5. TIMERx registers(x=2)........................................................................................................ 305 
3. General level2 timer (TIMERx, x=13)................................................................... 328 
3.1. Overview............................................................................................................................. 328 
3.2. Characteristics.................................................................................................................... 328 
3.3. Block diagram..................................................................................................................... 328 
3.4. Function overview............................................................................................................... 330 
3.5. TIMERx registers(x=13)...................................................................................................... 338 

 GD32E23x User Manual

 
4. General level3 timer (TIMERx, x=14)................................................................... 348 
4.1. Overview............................................................................................................................. 348 
4.2. Characteristics.................................................................................................................... 348 
4.3. Block diagram..................................................................................................................... 348 
4.4. Function overview............................................................................................................... 349 
4.5. TIMERx registers(x=14)...................................................................................................... 366 
5. General level4 timer (TIMERx, x=15, 16)............................................................. 386 
5.1. Overview............................................................................................................................. 386 
5.2. Characteristics.................................................................................................................... 386 
5.3. Block diagram..................................................................................................................... 386 
5.4. Function overview............................................................................................................... 387 
5.5. TIMERx registers(x=15, 16)................................................................................................ 401 
6. Basic timer (TIMERx, x=5) ................................................................................... 417 
6.1. Overview............................................................................................................................. 417 
6.2. Characteristics.................................................................................................................... 417 
6.3. Block diagram..................................................................................................................... 417 
6.4. Function overview............................................................................................................... 417 
6.5. TIMERx registers(x=5)........................................................................................................ 422 
Infrared ray port (IFRP) ....................................................................................427 
1. Overview............................................................................................................... 427 
2. Characteristics..................................................................................................... 427 
3. Function overview................................................................................................ 427 
Universal synchronous/asynchronous receiver /transmitter (USART)........429 
1. Overview............................................................................................................... 429 
2. Characteristics..................................................................................................... 429 
3. Function overview................................................................................................ 431 
3.1. USART frame format .......................................................................................................... 431 
3.2. Baud rate generation .......................................................................................................... 432 
3.3. USART transmitter.............................................................................................................. 433 
3.4. USART receiver.................................................................................................................. 434 
3.5. Use DMA for data buffer access......................................................................................... 435 
3.6. Hardware flow control......................................................................................................... 437 
3.7. Multi-processor communication.......................................................................................... 438 
3.8. LIN mode ............................................................................................................................ 439 
3.9. Synchronous mode............................................................................................................. 440 
3.10. IrDA SIR ENDEC mode ...................................................................................................... 441 
3.11. Half-duplex communication mode ...................................................................................... 442 
3.12. Smartcard (ISO7816-3) mode ............................................................................................ 442 
3.13. ModBus communication ..................................................................................................... 444 
3.14. Receive FIFO...................................................................................................................... 445 

 GD32E23x User Manual

 
3.15. Wakeup from Deep-sleep mode......................................................................................... 445 
3.16. USART interrupts................................................................................................................ 446 
4. Register definition................................................................................................ 448 
4.1. Control register 0 (USART_CTL0)...................................................................................... 448 
4.2. Control register 1 (USART_CTL1)...................................................................................... 450 
4.3. Control register 2 (USART_CTL2)...................................................................................... 453 
4.4. Baud rate generator register (USART_BAUD)................................................................... 456 
4.5. Prescaler and guard time configuration register (USART_GP).......................................... 456 
4.6. Receiver timeout register (USART_RT) ............................................................................. 457 
4.7. Command register (USART_CMD) .................................................................................... 458 
4.8. Status register (USART_STAT) .......................................................................................... 459 
4.9. Interrupt status clear register (USART_INTC).................................................................... 462 
4.10. Receive data register (USART_RDATA) ............................................................................ 464 
4.11. Transmit data register (USART_TDATA)............................................................................ 464 
4.12. USART coherence control register (USART_CHC)............................................................ 465 
4.13. USART receive FIFOcontrol and status register (USART_RFCS)..................................... 465 
Inter-integrated circuit interface (I2C).............................................................467 
1. Overview............................................................................................................... 467 
2. Characteristics..................................................................................................... 467 
3. Function overview................................................................................................ 467 
3.1. SDA and SCL lines ............................................................................................................. 468 
3.2. Data validation.................................................................................................................... 469 
3.3. START and STOP signal .................................................................................................... 469 
3.4. Clock synchronization......................................................................................................... 469 
3.5. Arbitration............................................................................................................................ 470 
3.6. I2C communication flow...................................................................................................... 470 
3.7. Programming model ........................................................................................................... 471 
3.8. SCL line stretching.............................................................................................................. 479 
3.9. Use DMA for data transfer.................................................................................................. 480 
3.10. Packet error checking......................................................................................................... 480 
3.11. SMBus support ................................................................................................................... 480 
3.12. SAM_V support................................................................................................................... 482 
3.13. Status, errors and interrupts............................................................................................... 482 
4. Register definition................................................................................................ 484 
4.1. Control register 0 (I2C_CTL0) ............................................................................................ 484 
4.2. Control register 1 (I2C_CTL1) ............................................................................................ 486 
4.3. Slave address register 0 (I2C_SADDR0) ........................................................................... 487 
4.4. Slave address register 1 (I2C_SADDR1) ........................................................................... 487 
4.5. Transfer buffer register (I2C_DATA)................................................................................... 488 
4.6. Transfer status register 0 (I2C_STAT0).............................................................................. 488 
4.7. Transfer status register 1 (I2C_STAT1).............................................................................. 491 
4.8. Clock configure register (I2C_CKCFG) .............................................................................. 492 

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