Freescale Semiconductor MCF52230 ColdFire Manuel utilisateur

MCF52235 ColdFire®Integrated

Microcontroller Reference Manual

Devices Supported:

MCF52230

MCF52231

MCF52232

MCF52233

MCF52234

MCF52235

MCF52236

Document Number:

MCF52235RM

Rev. 6

07/2010

Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not

available from Freescale for import or sale in the United States prior to September 2010:MCF52234CVM60, MCF52235CVM60

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Document Number: MCF52235RM

Rev. 6

07/2010

Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not

available from Freescale for import or sale in the United States prior to September 2010:MCF52234CVM60, MCF52235CVM60

MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6

Freescale Semiconductor iii

Chapter 1

Overview

1.1 MCF52235 Family Configurations ............................................................................................... 1-2

1.2 Block Diagram .............................................................................................................................. 1-3

1.3 Part Numbers and Packaging ........................................................................................................ 1-3

1.4 Features ......................................................................................................................................... 1-4

1.5 Memory Map Overview .............................................................................................................. 1-14

Chapter 2

Signal Descriptions

2.1 Introduction ................................................................................................................................... 2-1

2.2 Overview ....................................................................................................................................... 2-1

2.3 Reset Signals ................................................................................................................................. 2-9

2.4 PLL and Clock Signals .................................................................................................................. 2-9

2.5 Mode Selection .............................................................................................................................. 2-9

2.6 External Interrupt Signals .............................................................................................................. 2-9

2.7 Queued Serial Peripheral Interface (QSPI) ................................................................................. 2-10

2.8 Fast Ethernet Controller PHY Signals ........................................................................................2-11

2.9 I2C I/O Signals ............................................................................................................................ 2-11

2.10 UART Module Signals ................................................................................................................ 2-12

2.11 DMA Timer Signals .................................................................................................................... 2-12

2.12 ADC Signals ................................................................................................................................ 2-12

2.13 General Purpose Timer Signals ................................................................................................... 2-13

2.14 Pulse Width Modulator Signals ................................................................................................... 2-13

2.15 Debug Support Signals ................................................................................................................ 2-13

2.16 EzPort Signal Descriptions .......................................................................................................... 2-14

2.17 Power and Ground Pins ............................................................................................................... 2-15

Chapter 3

ColdFire Core

3.1 Introduction ................................................................................................................................... 3-1

3.2 Memory Map/Register Description ............................................................................................... 3-2

3.3 Functional Description .................................................................................................................. 3-8

Chapter 4

Enhanced Multiply-Accumulate Unit (EMAC)

4.1 Introduction ................................................................................................................................... 4-1

4.2 Memory Map/Register Definition ................................................................................................. 4-3

4.3 Functional Description .................................................................................................................. 4-8

Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not

available from Freescale for import or sale in the United States prior to September 2010:MCF52234CVM60, MCF52235CVM60

MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6

iv Freescale Semiconductor

Chapter 5

Cryptographic Acceleration Unit (CAU)

5.1 Introduction ................................................................................................................................... 5-1

5.2 Memory Map/Register Definition ................................................................................................. 5-2

5.3 Functional Description .................................................................................................................. 5-4

5.4 Application/Initialization Information ........................................................................................ 5-10

Chapter 6

Random Number Generator (RNG)

6.1 Introduction ................................................................................................................................... 6-1

6.2 Memory Map/Register Definition ................................................................................................. 6-2

6.3 Functional Description .................................................................................................................. 6-5

6.4 Initialization/Application Information .......................................................................................... 6-6

Chapter 7

Clock Module

7.1 Introduction ................................................................................................................................... 7-1

7.2 Features ......................................................................................................................................... 7-1

7.3 Modes of Operation ....................................................................................................................... 7-1

7.4 Low-power Mode Operation ......................................................................................................... 7-2

7.5 Block Diagram .............................................................................................................................. 7-2

7.6 Signal Descriptions ....................................................................................................................... 7-4

7.7 Memory Map and Registers .......................................................................................................... 7-5

7.8 Functional Description ................................................................................................................ 7-11

Chapter 8

Real-Time Clock

8.1 Introduction ................................................................................................................................... 8-1

8.2 Memory Map/Register Definition ................................................................................................. 8-2

8.3 Functional Description ................................................................................................................ 8-11

8.4 Initialization/Application Information ........................................................................................ 8-12

Chapter 9

Power Management

9.1 Introduction ................................................................................................................................... 9-1

9.2 Memory Map/Register Definition ................................................................................................. 9-1

9.3 IPS Bus Timeout Monitor ............................................................................................................. 9-9

9.4 Functional Description ................................................................................................................ 9-11

Chapter 10

Reset Controller Module

10.1 Introduction ................................................................................................................................. 10-1

10.2 Features ....................................................................................................................................... 10-1

10.3 Block Diagram ............................................................................................................................ 10-1

10.4 Signals ......................................................................................................................................... 10-2

Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not

available from Freescale for import or sale in the United States prior to September 2010:MCF52234CVM60, MCF52235CVM60

MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6

Freescale Semiconductor v

10.5 Memory Map and Registers ........................................................................................................ 10-2

10.6 Functional Description ................................................................................................................ 10-5

Chapter 11

Static RAM (SRAM)

11.1 Introduction ................................................................................................................................. 11-1

11.2 Memory Map/Register Description ............................................................................................. 11-1

11.3 Initialization/Application Information ........................................................................................ 11-3

Chapter 12

Chip Configuration Module (CCM)

12.1 Introduction ................................................................................................................................. 12-1

12.2 External Signal Descriptions ....................................................................................................... 12-2

12.3 Memory Map/Register Definition ............................................................................................... 12-2

12.4 Functional Description ................................................................................................................ 12-5

12.5 Reset ............................................................................................................................................ 12-6

Chapter 13

System Control Module (SCM)

13.1 Introduction ................................................................................................................................. 13-1

13.2 Overview ..................................................................................................................................... 13-1

13.3 Features ....................................................................................................................................... 13-1

13.4 Memory Map and Register Definition ........................................................................................ 13-2

13.5 Register Descriptions .................................................................................................................. 13-3

13.6 Internal Bus Arbitration .............................................................................................................. 13-9

13.7 System Access Control Unit (SACU) ....................................................................................... 13-12

Chapter 14

General Purpose I/O Module

14.1 Introduction ................................................................................................................................. 14-1

14.2 Overview ..................................................................................................................................... 14-2

14.3 Features ....................................................................................................................................... 14-3

14.4 Signal Descriptions ..................................................................................................................... 14-3

14.5 Memory Map/Register Definition ............................................................................................... 14-3

14.6 Register Descriptions .................................................................................................................. 14-5

14.7 Ports Interrupts .......................................................................................................................... 14-15

Chapter 15

Interrupt Controller Module

15.1 68K/ColdFire Interrupt Architecture Overview .......................................................................... 15-1

15.2 Memory Map ............................................................................................................................... 15-4

15.3 Register Descriptions .................................................................................................................. 15-5

15.4 Low-Power Wakeup Operation ................................................................................................. 15-17

Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not

available from Freescale for import or sale in the United States prior to September 2010:MCF52234CVM60, MCF52235CVM60

MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6

vi Freescale Semiconductor

Chapter 16

Edge Port Modules (EPORTn)

16.1 Introduction ................................................................................................................................. 16-1

16.2 Low-Power Mode Operation ....................................................................................................... 16-2

16.3 Signal Descriptions ..................................................................................................................... 16-2

16.4 Memory Map/Register Definition ............................................................................................... 16-3

Chapter 17

ColdFire Flash Module (CFM)

17.1 Introduction ................................................................................................................................. 17-1

17.2 External Signal Description ........................................................................................................ 17-3

17.3 Memory Map and Register Definition ........................................................................................ 17-3

17.4 Functional Description .............................................................................................................. 17-16

Chapter 18

Fast Ethernet Controller (FEC)

18.1 Overview ..................................................................................................................................... 18-1

18.2 Modes of Operation ..................................................................................................................... 18-1

18.3 FEC Top-Level Functional Diagram ........................................................................................... 18-2

18.4 Functional Description ................................................................................................................ 18-4

18.5 Programming Model ................................................................................................................. 18-18

18.6 Buffer Descriptors ..................................................................................................................... 18-47

Chapter 19

Ethernet Physical Transceiver (EPHY)

19.1 Introduction ................................................................................................................................. 19-1

19.2 External Signal Descriptions ....................................................................................................... 19-3

19.3 Memory Map and Register Descriptions .................................................................................... 19-5

19.4 Functional Description .............................................................................................................. 19-22

Chapter 20

DMA Controller Module

20.1 Introduction ................................................................................................................................. 20-1

20.2 DMA Transfer Overview ............................................................................................................ 20-3

20.3 Memory Map/Register Definition ............................................................................................... 20-3

20.4 Functional Description .............................................................................................................. 20-11

Chapter 21

EzPort

21.1 Features ....................................................................................................................................... 21-1

21.2 Modes of Operation ..................................................................................................................... 21-1

21.3 External Signal Description ........................................................................................................ 21-2

21.4 Command Definition ................................................................................................................... 21-3

21.5 Functional Description ................................................................................................................ 21-7

21.6 Initialization/Application Information ........................................................................................ 21-8

Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not

available from Freescale for import or sale in the United States prior to September 2010:MCF52234CVM60, MCF52235CVM60

MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6

Freescale Semiconductor vii

Chapter 22

Programmable Interrupt Timers (PIT0–PIT1)

22.1 Introduction ................................................................................................................................. 22-1

22.2 Memory Map/Register Definition ............................................................................................... 22-2

22.3 Functional Description ................................................................................................................ 22-5

Chapter 23

General Purpose Timer Module (GPT)

23.1 Introduction ................................................................................................................................. 23-1

23.2 Features ....................................................................................................................................... 23-1

23.3 Block Diagram ............................................................................................................................ 23-2

23.4 Low-Power Mode Operation ....................................................................................................... 23-3

23.5 Signal Description ....................................................................................................................... 23-3

23.6 Memory Map and Registers ........................................................................................................ 23-3

23.7 Functional Description .............................................................................................................. 23-17

23.8 Reset .......................................................................................................................................... 23-21

23.9 Interrupts ................................................................................................................................... 23-21

Chapter 24

DMA Timers (DTIM0–DTIM3)

24.1 Introduction ................................................................................................................................. 24-1

24.2 Memory Map/Register Definition ............................................................................................... 24-3

24.3 Functional Description ................................................................................................................ 24-8

24.4 Initialization/Application Information ........................................................................................ 24-9

Chapter 25

Queued Serial Peripheral Interface (QSPI)

25.1 Introduction ................................................................................................................................. 25-1

25.2 External Signal Description ........................................................................................................ 25-2

25.3 Memory Map/Register Definition ............................................................................................... 25-3

25.4 Functional Description ................................................................................................................ 25-9

25.5 Initialization/Application Information ...................................................................................... 25-15

Chapter 26

UART Modules

26.1 Introduction ................................................................................................................................. 26-1

26.2 External Signal Description ........................................................................................................ 26-3

26.3 Memory Map/Register Definition ............................................................................................... 26-3

26.4 Functional Description .............................................................................................................. 26-16

26.5 Initialization/Application Information ...................................................................................... 26-26

Chapter 27

I2C Interface

27.1 Introduction ................................................................................................................................. 27-1

27.2 Memory Map/Register Definition ............................................................................................... 27-3

Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not

available from Freescale for import or sale in the United States prior to September 2010:MCF52234CVM60, MCF52235CVM60

MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6

viii Freescale Semiconductor

27.3 Functional Description ................................................................................................................ 27-7

27.4 Initialization/Application Information ...................................................................................... 27-12

Chapter 28

Analog-to-Digital Converter (ADC)

28.1 Introduction ................................................................................................................................. 28-1

28.2 Features ....................................................................................................................................... 28-1

28.3 Block Diagram ............................................................................................................................ 28-2

28.4 Memory Map and Register Definition ........................................................................................ 28-2

28.5 Functional Description .............................................................................................................. 28-21

Chapter 29

Pulse-Width Modulation (PWM) Module

29.1 Introduction ................................................................................................................................. 29-1

29.2 Memory Map/Register Definition ............................................................................................... 29-2

29.3 Functional Description .............................................................................................................. 29-13

Chapter 30

FlexCAN

30.1 Introduction ................................................................................................................................. 30-1

30.2 External Signal Description ........................................................................................................ 30-5

30.3 Memory Map/Register Definition ............................................................................................... 30-5

30.4 Initialization/Application Information ...................................................................................... 30-28

Chapter 31

Debug Module

31.1 Introduction ................................................................................................................................. 31-1

31.2 Signal Descriptions ..................................................................................................................... 31-2

31.3 Memory Map/Register Definition ............................................................................................... 31-3

31.4 Functional Description .............................................................................................................. 31-17

Chapter 32

IEEE 1149.1 Test Access Port (JTAG)

32.1 Introduction ................................................................................................................................. 32-1

32.2 External Signal Description ........................................................................................................ 32-2

32.3 Memory Map/Register Definition ............................................................................................... 32-4

32.4 Functional Description ................................................................................................................ 32-6

32.5 Initialization/Application Information ...................................................................................... 32-10

Appendix A

Appendix B

Revision History

Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not

available from Freescale for import or sale in the United States prior to September 2010:MCF52234CVM60, MCF52235CVM60

MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6

Freescale Semiconductor ix

Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not

available from Freescale for import or sale in the United States prior to September 2010:MCF52234CVM60, MCF52235CVM60

MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6

Freescale Semiconductor 1-1

Chapter 1

Overview

This chapter provides an overview of the major features and functional components of the MCF52235

family of microcontrollers. The MCF52235 family is a highly integrated implementation of the ColdFire®

family of reduced instruction set computing (RISC) microcontrollers that also includes the MCF52230,

MCF52231, MCF52232, MC52233, MC52234, and MCF52236. The differences between these parts are

summarized in Table 1-1. This document is written from the perspective of the MCF52235.

The MCF52235 represents a family of highly-integrated 32-bit microcontrollers based on the V2 ColdFire

microarchitecture. Featuring up to 32 Kbytes of internal SRAM and 256 Kbytes of flash memory, four

32-bit timers with DMA request capability, a 4-channel DMA controller, fast Ethernet controller, a CAN

module, an I2C™ module, 3 UARTs and a queued SPI, the MC52235 family has been designed for

general-purpose industrial control applications.

This 32-bit device is based on the Version 2 (V2) ColdFire reduced instruction set computing (RISC) core

with an enhanced multiply-accumulate unit (EMAC) and divider providing 56 Dhrystone 2.1 MIPS at a

frequency of up to 60 MHz from internal flash. On-chip modules include the following:

• V2 ColdFire core with enhanced multiply-accumulate unit (EMAC)

• Cryptographic Acceleration Unit (CAU)

• Up to 32 Kbytes of internal SRAM

• Up to 256 Kbytes of on-chip flash memory

• Fast Ethernet Controller (FEC) with on-chip transceiver (ePHY)

• Three universal asynchronous receiver/transmitters (UARTs)

• Controller area network 2.0B (FlexCAN) module

• Inter-integrated circuit (I2C) bus controller

• 10- or 12-bit analog-to-digital converter (ADC)

• Queued serial peripheral interface (QSPI) module

• Four-channel, 32-bit direct memory access (DMA) controller

• Four-channel, 32-bit input capture/output compare timers with optional DMA support

• Two 16-bit periodic interrupt timers (PITs)

• Programmable software watchdog timer

• Two interrupt controllers, each capable of handling up to 63 interrupt sources (126 total)

These devices are ideal for cost-sensitive applications requiring significant control processing for

connectivity, data buffering, and user interface, as well as signal processing in a variety of key markets

such as security, imaging, networking, gaming, and medical. This leading package of integration and high

performance allows fast time to market through easy code reuse and extensive third party tool support.

Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not

available from Freescale for import or sale in the United States prior to September 2010:MCF52234CVM60, MCF52235CVM60

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