Enclustra Mercury KX1 Manuel utilisateur

Mercury KX1 FPGA Module

User Manual

Purpose

The purpose of this document is to present the characteristics of Mercury KX1 FPGA module to the user, and

to provide the user with a comprehensive guide to understanding and using the Mercury KX1 FPGA module.

Summary

This document first gives an overview of the Mercury KX1 FPGA module followed by a detailed description

of its features and configuration options. In addition, references to other useful documents are included.

Product Information Code Name

Product ME-KX1 Mercury KX1 FPGA Module

Document Information Reference Version Date

Reference / Version / Date D-0000-411-002 07 16.02.2021

Approval Information Name Position Date

Written by DIUN Design Engineer 10.06.2016

Verified by GLAC Design Expert 24.06.2016

Approved by DIUN Manager, BU SP 16.02.2021

Enclustra GmbH – Räffelstrasse 28 – CH-8045 Zürich – Switzerland

Phone +41 43 343 39 43 – www.enclustra.com

Unauthorized duplication of this document, in whole or in part, by any means is prohibited without the prior

written permission of Enclustra GmbH, Switzerland.

Although Enclustra GmbH believes that the information included in this publication is correct as of the date

of publication, Enclustra GmbH reserves the right to make changes at any time without notice.

All information in this document is strictly confidential and may only be published by Enclustra GmbH,

Switzerland.

All referenced trademarks are the property of their respective owners.

Document History

Version Date Author Comment

07 16.02.2021 DIUN Cleaned-up product variants, added Mercury+ ST1 to accesories sec-

tion, added information on FPGA fuses and warranty, on differential

I/Os, on voltage monitoring outputs, other style updates

06 25.07.2019 DIUN Added information on voltage monitoring, power supplies, heat sink,

updated DDR memory types and EEPROM map description, other

style updates

05 21.08.2018 DIUN Minor corrections and style updates

04 04.05.2017 DIUN Updated EEPROM map, block diagram and footprint information

03 27.12.2016 DIUN Added tool support information

02 02.08.2016 DIUN Version 02, added information on MGTs

01 05.07.2016 DIUN Version 01

D-0000-411-002 2 / 50 Version 07, 16.02.2021

Table of Contents

1 Overview 5

1.1 General ................................................... 5

1.1.1 Introduction ................................................ 5

1.1.2 Warranty .................................................. 5

1.1.3 RoHS .................................................... 5

1.1.4 DisposalandWEEE ............................................ 5

1.1.5 Safety Recommendations and Warnings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.1.6 ElectrostaticDischarge .......................................... 6

1.1.7 Electromagnetic Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.2 Features................................................... 6

1.3 Deliverables ................................................ 7

1.4 Accessories................................................. 7

1.4.1 ReferenceDesign ............................................. 7

1.4.2 Mercury+PE1BaseBoard ........................................ 7

1.4.3 Mercury+ST1BaseBoard ........................................ 8

1.5 XilinxToolSupport ............................................ 8

2 Module Description 9

2.1 BlockDiagram............................................... 9

2.2 Module Configuration and Product Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.3 Article Numbers and Article Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.4 TopandBottomViews .......................................... 13

2.4.1 TopView .................................................. 13

2.4.2 BottomView................................................ 13

2.5 Top and Bottom Assembly Drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.5.1 TopAssemblyDrawing .......................................... 14

2.5.2 BottomAssemblyDrawing........................................ 14

2.6 ModuleFootprint ............................................. 15

2.7 MechanicalData.............................................. 16

2.8 ModuleConnector ............................................ 16

2.9 UserI/O................................................... 17

2.9.1 Pinout.................................................... 17

2.9.2 DifferentialI/Os .............................................. 18

2.9.3 I/OBanks.................................................. 18

2.9.4 VREFUsage................................................. 19

2.9.5 VCC_IOUsage ............................................... 19

2.9.6 SignalTerminations ............................................ 21

2.9.7 AnalogInputs ............................................... 21

2.10 Multi-Gigabit Transceiver (MGT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2.11 Power.................................................... 23

2.11.1 PowerGenerationOverview ....................................... 23

2.11.2 PowerEnable/PowerGood........................................ 23

2.11.3 VoltageSupplyInputs........................................... 24

2.11.4 VoltageSupplyOutputs ......................................... 24

2.11.5 PowerConsumption............................................ 25

2.11.6 HeatDissipation.............................................. 25

2.11.7 VoltageMonitoring ............................................ 25

2.12 ClockGeneration ............................................. 26

2.13 Reset .................................................... 26

2.14 LEDs..................................................... 27

2.15 DDR3SDRAM ............................................... 27

2.15.1 DDR3SDRAMType ............................................ 28

2.15.2 SignalDescription............................................. 28

2.15.3 Termination................................................. 28

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2.15.4 Parameters................................................. 28

2.15.5 DDR3LowVoltageOperation ...................................... 29

2.16 QSPIFlash ................................................. 29

2.16.1 QSPIFlashType .............................................. 29

2.16.2 SignalDescription............................................. 30

2.17 DualGigabitEthernet........................................... 31

2.17.1 EthernetPHYType............................................. 31

2.17.2 SignalDescription............................................. 31

2.17.3 ExternalConnectivity ........................................... 31

2.17.4 MDIOAddress............................................... 31

2.17.5 PHYConfiguration............................................. 31

2.18 CypressFX3USB3.0Controller ..................................... 32

2.18.1 CypressFX3Type ............................................. 32

2.18.2 CypressFX3Pinout ............................................ 32

2.18.3 FunctionalDescription .......................................... 32

2.19 Real-TimeClock(RTC)........................................... 33

2.19.1 RTCType .................................................. 33

2.20 SecureEEPROM .............................................. 34

2.20.1 EEPROMType ............................................... 34

3 Device Configuration 35

3.1 ConfigurationSignals........................................... 35

3.2 ConfigurationMode............................................ 36

3.3 Pull-UpDuringConfiguration ...................................... 36

3.4 JTAG..................................................... 38

3.4.1 JTAGonModuleConnector ....................................... 38

3.4.2 ExternalConnectivity ........................................... 38

3.4.3 FX3JTAGConnector............................................ 38

3.5 MasterSerialConfiguration ....................................... 38

3.5.1 SignalDescription............................................. 39

3.6 SlaveSerialConfiguration ........................................ 39

3.6.1 SignalDescription............................................. 39

3.7 QSPI Flash Programming via JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

3.8 QSPI Flash Programming from an External SPI Master . . . . . . . . . . . . . . . . . . . . . . . . 40

3.8.1 SignalDescription............................................. 41

3.9 Enclustra Module Configuration Tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

4 I2C Communication 42

4.1 Overview .................................................. 42

4.2 SignalDescription............................................. 42

4.3 I2CAddressMap ............................................. 42

4.4 SecureEEPROM .............................................. 43

4.4.1 MemoryMap ............................................... 43

5 Operating Conditions 46

5.1 AbsoluteMaximumRatings ....................................... 46

5.2 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

6 Ordering and Support 47

6.1 Ordering .................................................. 47

6.2 Support................................................... 47

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1 Overview

1.1 General

1.1.1 Introduction

The Mercury KX1 FPGA module combines the Xilinx Kintex-7® All Programmable FPGA device with fast

DDR3 SDRAM, USB 3.0 controller and PHY, dual Gigabit Ethernet, multi-gigabit transceivers, high-speed

LVDS I/O, and is available in industrial temperature range, forming a complete and powerful embedded

processing system.

The use of the Mercury KX1 FPGA module, in contrast to building a custom FPGA hardware, significantly

simplifies system design and thus shortens time to market and decreases the development effort of your

product.

Together with Mercury base boards, the Mercury KX1 FPGA module allows the user to quickly build a system

prototype and start with application development.

1.1.2 Warranty

Please refer to the General Business Conditions, available on the Enclustra website [1].

Warning!

Please note that the warranty of an Enclustra module is voided if the FPGA fuses are blown. This

operation is done at own risk, as it is irreversible. Enclustra cannot test the module in case of a warranty

product return.

1.1.3 RoHS

The Mercury KX1 FPGA module is designed and produced according to the Restriction of Hazardous Sub-

stances (RoHS) Directive (2011/65/EC).

1.1.4 Disposal and WEEE

The Mercury KX1 FPGA module must be properly disposed of at the end of its life.

The Waste Electrical and Electronic Equipment (WEEE) Directive (2002/96/EC) is not applicable for the Mer-

cury KX1 FPGA module.

1.1.5 Safety Recommendations and Warnings

Mercury modules are not designed to be “ready for operation” for the end-user. These can only be used in

combination with suitable base boards. Proper configuration of the hardware before usage is required.

Ensure that the power supply is disconnected from the board before inserting or removing the Mercury KX1

FPGA module, connecting interfaces, or connecting jumpers.

Touching the capacitors of the DC-DC converters can lead to voltage peaks and permanent damage; over-

voltage on power or signal lines can also cause permanent damage to the module.

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Warning!

It is possible to mount the Mercury KX1 FPGA module the wrong way round on the base board - always

check that the mounting holes on the base board are aligned with the mounting holes of the Mercury

KX1 FPGA module.

The base board and module may be damaged if the module is mounted the wrong way round and

powered up.

Warning!

Certain older revisions of the Mercury KX1 FPGA module cannot be used in combination with Mercury+

base boards (with three module connectors), due to a mechanical collision caused by large capacitors

on the bottom side of the module.

Always check that the mounting holes on the Mercury+ PE1 base board are aligned with the mount-

ing holes of the Mercury KX1 FPGA module. If the module cannot be mounted correctly due to the

mechanical collision, please contact Enclustra support.

1.1.6 Electrostatic Discharge

Electronic boards are sensitive to electrostatic discharge (ESD). Please ensure that the product is handled

with care and only in an ESD-protected environment.

1.1.7 Electromagnetic Compatibility

The Mercury KX1 FPGA module is a Class A product (as defined in IEC 61000-3-2 standard) and is not

intended for use in domestic environments. The product may cause electromagnetic interference, for which

appropriate measures must be taken.

1.2 Features

•Xilinx Kintex-7 28 nm FPGA XC7K160T/XC7K325T, FFG676/FBG676 package

•178 user I/Os up to 3.3 V

•158 FPGA I/Os (single-ended, differential or analog)

•20 MGT signals (clock and data)

•FBG package devices: 4 MGTs @ 6.6 Gbit/sec and 2 reference input clock differential pairs

•FFG package devices: 4 MGTs @ 10.3125 Gbit/sec and 2 reference input clock differential pairs

•PCIe Gen2 ×4 (Xilinx integrated PCIe block)

•Up to 2 GB + 512 MB DDR3 SDRAM

•64 MB quad SPI flash

•Cypress EZ-USB FX3 USB 3.0 device controller

•Dual Gigabit Ethernet

•Real-time clock

•High-power 16 A core power supply

•5 to 15 V supply voltage

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1.3 Deliverables

•Mercury KX1 FPGA module

•Mercury KX1 FPGA module documentation, available via download:

•Mercury KX1 FPGA Module User Manual (this document)

•Mercury KX1 FPGA Module Reference Design [2]

•Mercury KX1 FPGA Module IO Net Length Excel Sheet [3]

•Mercury KX1 FPGA Module FPGA Pinout Excel Sheet [4]

•Mercury KX1 FPGA Module User Schematics (PDF) [5]

•Mercury KX1 FPGA Module Known Issues and Changes [6]

•Mercury KX1 FPGA Module Footprint (Altium, Eagle, Orcad and PADS) [7]

•Mercury KX1 FPGA Module 3D Model (PDF) [8]

•Mercury KX1 FPGA Module STEP 3D Model [9]

•Mercury Mars Module Pin Connection Guidelines [10]

•Mercury Master Pinout [11]

•Mercury Heatsink Application Note [15]

1.4 Accessories

1.4.1 Reference Design

The Mercury KX1 FPGA module reference design features an example configuration for the Kintex-7 FPGA

device, together with an example top level HDL file for the user logic.

A number of software applications are available for the reference design, that show how to initialize the

peripheral controllers and how to access the external devices. Pre-compiled binaries are included in the

archive, so that the user can easily check that the hardware is functional.

The reference design can be downloaded from Github: https://github.com/enclustra.

1.4.2 Mercury+ PE1 Base Board

•168-pin Hirose FX10 module connectors (PE1-200: 2 connectors; PE1-300/400: 3 connectors)

•System controller

•Power control

•System monitor (PE1-300/400)

•Current sense (PE1-300/400)

•Low-jitter clock generator (PE1-300/400)

•microSD card holder

•User EEPROM

•eMMC managed NAND flash (PE1-300/400)

•PCIe ×4 interface

•USB 3.0 device connector

•USB 2.0 host connector (PE1-200: 1 connector; PE1-300/400: 4 connectors)

•Micro USB 2.0 device (UART, SPI, I2C, JTAG) connector

•2×RJ45 Gigabit Ethernet connectors

•mPCIe/mSATA card holder (USB only) (PE1-300/400)

•SIM card holder (optional, PE1-300/400 only)

•SMA clock and data in/out (optional, PE1-300/400 only)

•1×FMC LPC connector (PE1-200)

•1×FMC HPC connector (PE1-300)

•2×FMC LPC connector (PE1-400)

•2×40-pin Anios pin header

•3×12-pin IO headers

•5 to 15 V DC supply voltage

•USB bus power (with restrictions)

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Please note that the available features depend on the equipped Mercury module type and on the selected

base board variant.

1.4.3 Mercury+ ST1 Base Board

•168-pin Hirose FX10 module connectors (3 connectors)

•2×MIPI D-PHY connectors: CSI and CSI/DSI (requires FPGA support)

•Mini DisplayPort connector (requires FPGA support)

•HDMI connector (requires FPGA support)

•SFP+ connector

•Low-jitter clock generator

•USB 3.0 device connector

•USB 3.0 host connector

•FTDI USB 2.0 device controller with micro USB device connector (UART, SPI, I2C, JTAG)

•2×RJ45 Gigabit Ethernet connectors

•1×FMC HPC connector (note: not all pins are available)

•2×40-pin Anios pin header

•3×12-pin IO headers

•microSD card holder

•5 to 15 V DC supply voltage

•Form factor: 100 ×120 mm

Please note that the available features depend on the equipped Mercury module type.

1.5 Xilinx Tool Support

The FPGA devices equipped on the Mercury KX1 FPGA module are supported by the Vivado HL WebPACK

Edition or by the Vivado HL Design Edition software, depending on the device’s density. Table 1 presents

the correspondence between devices and tools. Please contact Xilinx for further information.

Module Xilinx Tool Support Costs

ME-KX1-160 Vivado HL WebPACK Edition Free of charge

ME-KX1-325 Vivado HL Design Edition Paid license required

Table 1: Xilinx Tool Support

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2 Module Description

2.1 Block Diagram

Figure 1: Hardware Block Diagram

The main component of the Mercury KX1 FPGA module is the Xilinx Kintex-7 FPGA device. Most of its I/O

pins are connected to the Mercury module connectors, making 158 regular user I/Os available to the user.

Further, four multi-gigabit transceivers with support for PCIe Gen2 ×4 are available on the module connector.

The FPGA device can be configured with a bitstream residing in the on-board QSPI flash, via Cypress FX3

USB 3.0 controller fitted on the module, via an external microcontroller or via the JTAG interface connected

to Mercury module connector.

The memory subsystem is built from a 64 MB QSPI flash and up to 2 GB + 512 MB DDR3 SDRAM in the

standard configuration.

Further, the module is equipped with two Gigabit Ethernet PHYs, making it ideal for communication appli-

cations.

A Cypress FX3 USB 3.0 controller is fitted on the module to easily implement a communication link to a host

PC.

A real-time clock is available on the module and is connected to the global I2C bus.

D-0000-411-002 9 / 50 Version 07, 16.02.2021

On-board clock generation is based on a 100 MHz crystal oscillator and on a 200 MHz LVDS oscillator.

The module’s internal supply voltages are generated from a single input supply of 5 - 15 V DC. Some of

these voltages are available on the Mercury module connectors to supply circuits on the base board.

Four LEDs are connected to the FPGA pins for status signaling. Another LED is connected to the Cypress

FX3 USB 3.0 controller user pin for the same purpose.

2.2 Module Configuration and Product Codes

Table 2 describes the available standard module configurations. Custom configurations are available; please

contact Enclustra for further information.

Product Code FPGA DDR3/DDR3L SDRAM USB 3.0 Temperature

Range

ME-KX1-160-1C-D10 XC7K160T-1FBG676C 1024 + 256 MB X0 to +70◦C

ME-KX1-325-2I-D11-P XC7K325T-2FFG676I 2048 + 512 MB X-40 to +85◦C

Table 2: Standard Module Configurations

The product code indicates the module type and main features. Figure 2 describes the fields within the

product code.

Figure 2: Product Code Fields

Please note that for the first revision modules or early access modules, the product code may not respect

entirely this naming convention. Please contact Enclustra for details on this aspect.

2.3 Article Numbers and Article Codes

Every module is uniquely labeled, showing the article number and serial number. An example is presented

in Figure 3.

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