Digilent Nexys2 Manuel utilisateur

www. d igilent inc.com

Revision: July 11, 2011 215 E Main Suite D | Pullman, WA 99163

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12 pages Doc: 502-134

Overview

The Nexys2 circuit board is a complete,

ready-to-use circuit development platform

based on a Xilinx Spartan 3E FPGA. Its on-

board high-speed USB2 port, 16Mbytes of

RAM and ROM, and several I/O devices and

ports make it an ideal platform for digital

systems of all kinds, including embedded

processor systems based on Xilinx’s

MicroBlaze. The USB2 port provides board

power and a programming interface, so the

Nexys2 board can be used with a notebook

computer to create a truly portable design

station.

The Nexys2 brings leading technologies to a

platform that anyone can use to gain digital

design experience. It can host countless

FPGA-based digital systems, and designs

can easily grow beyond the board using any

or all of the five expansion connectors. Four

12-pin Peripheral Module (Pmod) connectors

can accommodate up to eight low-cost

Pmods to add features like motor control, A/D

and D/A conversion, audio circuits, and a host

of sensor and actuator interfaces. All user-

accessible signals on the Nexys2 board are

ESD and short-circuit protected, ensuring a

long operating life in any environment.

The Nexys2 board is fully compatible with all

versions of the Xilinx ISE tools, including the

free WebPack. Now anyone can build real

digital systems for less than the price of a

textbook.

Power Supplies

The Nexys2 board input power input bus can be driven from a USB cable, from a 5VDC-15VDC,

center positive, 2.1mm wall-plug supply, or from a battery pack. A shorting block loaded on the

“power select” jumper selects the power source. The USB circuitry is always powered from the USB

cable – if no USB cable is attached, the USB circuitry is left unpowered.

•500K-gate Xilinx Spartan 3E FPGA

•USB2-based FPGA configuration and high-speed data

transfers (using the free Adept Suite Software)

•USB-powered (batteries and/or wall-plug can also be used)

•16MB of Micron PSDRAM &16MB of Intel StrataFlash ROM

•Xilinx Platform Flash for nonvolatile FPGA configurations

•Efficient switch-mode power supplies (good for battery

powered applications)

•50MHz oscillator plus socket for second oscillator

•60 FPGA I/O’s routed to expansion connectors (one high-

speed Hirose FX2 connector and four 6-pin headers)

•8 LEDs, 4-digit 7-seg display, 4 buttons, 8 slide switches

•Ships in a plastic carry case with USB cable

Figure 1: Nexys2 block diagram and features

Nexys2 Reference Manual

Digilent

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Figure 3: Nexys2 power supply jumpers

Figure 2: Nexys2 power supply block diagram

The input power bus drives a 3.3V voltage regulator

that supplies all required board current. Some devices

require 2.5V, 1.8V, and 1.2V supplies in addition to the

main 3.3V supply, and these additional supplies are

created by regulators that take their input from the

main 3.3V supply. The primary supplies are generated

by highly efficient switching regulators from Linear

Technology. These regulators not only use USB power

efficiently, they also allow the Nexys2 to run from

battery packs for extended periods.

Total board current depends on the FPGA configuration,

clock frequency, and external connections. In test

circuits with roughly 20K gates routed, a 50MHz clock

source, and all LEDs illuminated, about 200mA of

current is drawn from the 1.2V supply, 50mA from the

2.5V supply, and 100mA from the 3.3V supply. Required

current will increase if larger circuits are configured in

the FPGA, and if peripheral boards are attached. The

table above summarizes the power supply parameters.

The Nexys2 board can also receive power from (or

deliver power to) a peripheral board connected to a

Pmod connector or to the large 100-pin expansion

connector. Jumpers near the Pmod connectors and

large expansion connector (JP1 – JP5) can connect the

Nexys2’s input power bus to the connector’s power pins.

The Pmod jumpers can be used to route either the input

power bus or regulated 3.3V to the Pmod power pins,

while the expansion connector jumper can only make or

break a connection with the input power bus.

USB power is supplied to the USB circuitry directly, but

to the rest of the board through an electronic switch (Q1

in the Nexys2 schematic). The on-board USB controller

turns on switch Q1 only after informing the host PC that

Table 1: Nexys2 Power Supplies

Supply Device Amps (max/typ)

3.3V main IC6: LTC1765 3A/100mA

2.5V FPGA IC7: LTC3417 1.4A/50mA

1.2V FPGA IC7: LTC3417 1.4A/200mA

1.8V SRAM IC8: LTC1844 150mA/90mA

3.3V USB IC5: LTC1844 150mA/60mA

Nexys2 Reference Manual

Digilent

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more than 100mA will be drawn through the USB cable (as required by the USB specification). A USB

host can supply only 500mA of current at 5VDC. When using USB power, care must be taken to

ensure the Nexys2 board and any attached peripheral boards do not draw more than 500mA, or

damage to the host may result. The Nexys2 board typically consumes about 300mA of USB current,

leaving about 200mA for peripheral boards. If peripheral boards require more current than the USB

cable can supply, an external power supply should be used.

The Nexys2 board uses a six layer PCB, with the inner layers dedicated to VCC and GND planes.

The FPGA and the other ICs on the board all have a large complement of bypass capacitors placed

as close as possible to each VCC pin. The power supply routing and bypass capacitors result in a

very clean, stable, and low-noise power supply.

FPGA and Platform Flash Configuration

The FPGA on the Nexys2 board must be configured (or programmed) by the user before it can

perform any functions. During configuration, a “bit” file is transferred into memory cells within the

FPGA to define the logical functions and circuit interconnects. The free ISE/WebPack CAD software

from Xilinx can be used to create bit files from VHDL, Verilog, or schematic-based source files.

The FPGA can be programmed in two ways:

directly from a PC using the on-board USB port,

and from an on-board Platform Flash ROM (the

Flash ROM is also user-programmable via the

USB port). A jumper on the Nexys2 board

determines which source (PC or ROM) the

FPGA will use to load its configuration. The

FPGA will automatically load a configuration

from the Platform Flash ROM at power-on if the

configuration Mode jumper is set to “Master

serial”. If the Mode jumper is set to “JTAG”, the

FPGA will await programming from the PC (via

the USB cable).

Digilent’s freely available PC-based Adept

software can be used to configure the FPGA

and Platform Flash with any suitable file stored

on the computer. Adept uses the USB cable to

transfer a selected bit file from the PC to the FPGA or Platform Flash ROM. After the FPGA is

configured, it will remain so until it is reset by a power-cycle event or by the FPGA reset button

(BTNR) being pressed. The Platform Flash ROM will retain a bit file until it is reprogrammed,

regardless of power-cycle events.

To program the Nexys2 board using Adept, attach the USB cable to the board (if USB power will not

be used, attach a suitable power supply to the power jack or battery connector on the board, and set

the power switch to “wall” or “bat”). Start the Adept software, and wait for the FPGA and the Platform

Flash ROM to be recognized. Use the browse function to associate the desired .bit file with the FPGA,

and/or the desired .mcs file with the Platform Flash ROM. Right-click on the device to be

programmed, and select the “program” function. The configuration file will be sent to the FPGA or

Platform Flash, and the software will indicate whether programming was successful. The configuration

XCF02

Platform

Flash

JTAG

header

JTAG

PROG

DONE

Vdd

Done

LED

FPGA

Reset

B tton

(BTNR)

Spartan 3E

FPGA

Mode

J mper

USB miniB

connector

Cypress

EZ-USB

Slave

serial

port

JTAG

port

Figure 4: Nexys2 programming circuits

Nexys2 Reference Manual

Digilent

www.digilentinc.com

Figure 5: Nexys2 board programming circuits

Figure 7: Nexys2 board I/O devices

“done” LED will illuminate after the FPGA has been

successfully configured. For further information on

using Adept, please see the Adept documentation

available at the Digilent website.

The Nexys2 board can also be programmed using

Xilinx’s iMPACT software by connecting a suitable

programming cable to the JTAG header. Digilent’s

JTAG3 cable or any other Xilinx cable may be

used.

A demonstration configuration is loaded into the

Platform Flash on the Nexys2 board during

manufacturing. That configuration, also available

on the Digilent webpage, can be used to check all

of the devices and circuits on the Nexys2 board.

Clocks

The Nexys2 board includes a 50MHz oscillator and a socket for a

second oscillator. Clock signals from the oscillators connect to

global clock input pins on the FPGA so they can drive the clock

synthesizer blocks available in FPGA. The clock synthesizers

(called DLLs, or delay locked loops) provide clock management

capabilities that include doubling or quadrupling the input

frequency, dividing the input frequency by any integer multiple,

and defining precise phase and delay relationships between

various clock signals.

User I/O

The Nexys2 board includes several input devices, output devices, and data ports, allowing many

designs to be implemented without the need for any other components.

Inputs: Slide Switches and Pushbuttons

Four pushbuttons and eight slide switches are provided for circuit inputs. Pushbutton inputs are

normally low, and they are driven high only when the pushbutton is pressed. Slide switches generate

constant high or low inputs depending on their position. Pushbutton and slide switch inputs use a

Figure 6: Nexys2 clocks

Nexys2 Reference Manual

Digilent

www.digilentinc.com

series resistor for protection against short circuits (a short circuit would occur if an FPGA pin assigned

to a pushbutton or slide switch was inadvertently defined as an output).

Figure 8: Nexys2 I/O devices and circuits

Outputs: LEDs

Eight LEDs are provided for circuit outputs. LED anodes are driven from the FPGA via 390-ohm

resistors, so a logic ‘1’ output will illuminate them with 3-4ma of drive current. A ninth LED is provided

as a power-on LED, and a tenth LED indicates FPGA programming status. Note that LEDs 4-7 have

different pin assignments due to pinout differences between the -500 and the -1200 die.

Outputs: Seven-Segment Display

The Nexys2 board contains a four-digit common anode seven-segment LED display. Each of the four

digits is composed of seven segments arranged in a “figure 8” pattern, with an LED embedded in

each segment. Segment LEDs can be individually illuminated, so any one of 128 patterns can be

displayed on a digit by illuminating certain LED segments and leaving the others dark. Of these 128

possible patterns, the ten corresponding to the decimal digits are the most useful.

Nexys2 Reference Manual

Digilent

www.digilentinc.com

Figure 9: Nexys2 seven-segment displays

The anodes of the seven LEDs forming each digit are tied together into one “common anode” circuit

node, but the LED cathodes remain separate. The common anode signals are available as four “digit

enable” input signals to the 4-digit display. The cathodes of similar segments on all four displays are

connected into seven circuit nodes labeled CA through CG (so, for example, the four “D” cathodes

from the four digits are grouped together into a single circuit node called “CD”). These seven cathode

signals are available as inputs to the 4-digit display. This signal connection scheme creates a

multiplexed display, where the cathode signals are common to all digits but they can only illuminate

the segments of the digit whose corresponding anode signal is asserted.

A scanning display controller circuit can be used to show a four-digit number on this display. This

circuit drives the anode signals and corresponding cathode patterns of each digit in a repeating,

continuous succession, at an update rate that is faster than the human eye can detect. Each digit is

illuminated just one-quarter of the time, but because the eye cannot perceive the darkening of a digit

before it is illuminated again, the digit appears continuously illuminated. If the update or “refresh” rate

is slowed to around 45 hertz, most people will begin to see the display flicker.

In order for each of the four digits to appear bright and continuously illuminated, all four digits should

be driven once every 1 to 16ms, for a refresh frequency of 1KHz to 60Hz. For example, in a 60Hz

refresh scheme, the entire display would be refreshed once every 16ms, and each digit would be

illuminated for ¼ of the refresh cycle, or 4ms. The controller must drive the cathodes with the correct

pattern when the corresponding

anode signal is driven. To illustrate

the process, if AN0 is asserted while

CB and CC are asserted, then a “1”

will be displayed in digit position 1.

Then, if AN1 is asserted while CA, CB

and CC are asserted, then a “7” will

be displayed in digit position 2. If AN0

and CB, CC are driven for 4ms, and

then A1 and CA, CB, CC are driven

for 4ms in an endless succession, the

display will show “17” in the first two

digits. An example timing diagram for

a four-digit controller is provided.

An n-ill minated seven-segment display, and nine

ill mination patterns corresponding to decimal digits

AN1

AN2

AN3

AN4

Cathodes Digit 0

Refresh period = 1ms to 16ms

Digit period = Refresh / 4

Digit 1 Digit 2 Digit 3

Figure 10: Seven-segment display timing diagram

Nexys2 Reference Manual

Digilent

www.digilentinc.com

USB Port

The Nexys2 includes a high-speed USB2

port based on a Cypress CY7C68013A USB

controller. The USB port can be used to

program the on-board Xilinx devices, to

perform user-data transfers at up to

38Mbytes/sec, and to provide power to the

board. Programming is accomplished with

Digilent’s free Adept Suite Software. User

data transfers can also be accomplished

using the Adept software, or custom user

software can be written using Digilent’s

public API’s to access the Nexys2 USB

connection. Information on using Adept

and/or the public API’s to transfer data can

be found on the Digilent website.

The USB port can also provide power to the Nexys2 board if the power select jumper is set to “USB”.

The USB specification requires that attached devices draw no more than 100mA until they have

requested more current, after which up to 500mA may be drawn. When first attached to a USB host,

the Nexys2 board requests 500mA, and then activates a transistor switch to connect the USB cable

voltage to the main input power bus. The Nexys2 board typically draws around 300mA from the USB

cable, and care should be taken (especially when using peripheral boards) to ensure that no more

than 500mA is drawn.

PS/2 Port

The 6-pin mini-DIN connector can accommodate a PS/2 mouse or keyboard. Most PS/2 devices can

operate from a 3.3V supply, but older devices may require a 5VDC supply. A three-pin jumper on the

Nexys2 board immediately adjacent to the PS/2 connector selects whether regulated 3.3V or the main

input power bus voltage (VU) is supplied to the PS/2 connector. To send 5V to the PS/2 connector,

set the PS2 power jumper to Vswt (the main input power bus), and ensure the board is powered from

USB or a 5VDC wall-plug supply. To send 3.3V to the connector, set the jumper to 3.3V.

Both the mouse and keyboard use a two-wire serial bus (clock and data) to communicate with a host

device. Both use 11-bit words that include a start, stop and odd parity bit, but the data packets are

organized differently, and the keyboard interface allows bi-directional data transfers (so the host

Figure 12: Nexys2 PS/2 circuits

Figure 11: Nexys2 USB circuit

Nexys2 Reference Manual

Digilent

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device can illuminate state LEDs on the keyboard).

Bus timings are shown in the figure. The clock and

data signals are only driven when data transfers

occur, and otherwise they are held in the “idle”

state at logic ‘1’. The timings define signal

requirements for mouse-to-host communications

and bi-directional keyboard communications. A

PS/2 interface circuit can be implemented in the

FPGA to create a keyboard or mouse interface.

Keyboard

The keyboard uses open-collector drivers so the keyboard or an attached host device can drive the

two-wire bus (if the host device will not send data to the keyboard, then the host can use input-only

ports).

PS2-style keyboards use scan codes to communicate key press data. Each key is assigned a code

that is sent whenever the key is pressed; if the key is held down, the scan code will be sent repeatedly

about once every 100ms. When a key is released, a “F0” key-up code is sent, followed by the scan

code of the released key. If a key can be “shifted” to produce a new character (like a capital letter),

then a shift character is sent in addition to the scan code, and the host must determine which ASCII

character to use. Some keys, called extended keys, send an “E0” ahead of the scan code (and they

may send more than one scan code). When an extended key is released, an “E0 F0” key-up code is

sent, followed by the scan code. Scan codes for most keys are shown in the figure. A host device can

also send data to the keyboard. Below is a short list of some common commands a host might send.

ED Set Num Lock, Caps Lock, and Scroll Lock LEDs. Keyboard returns “FA” after receiving “ED”,

then host sends a byte to set LED status: Bit 0 sets Scroll Lock; bit 1 sets Num Lock; and Bit 2

sets Caps lock. Bits 3 to 7 are ignored.

EE Echo (test). Keyboard returns “EE” after receiving “EE”.

F3 Set scan code repeat rate. Keyboard returns “F3” on receiving “FA”, then host sends second

byte to set the repeat rate.

FE Resend. “FE” directs keyboard to re-send most recent scan code.

FF Reset. Resets the keyboard.

The keyboard can send data to the host only when both the data and clock lines are high (or idle).

Since the host is the “bus master”, the keyboard must check to see whether the host is sending data

before driving the bus. To facilitate this, the clock line is used as a “clear to send” signal. If the host

pulls the clock line low, the keyboard must not send any data until the clock is released. The keyboard

sends data to the host in 11-bit words that contain a ‘0’ start bit, followed by 8-bits of scan code (LSB

first), followed by an odd parity bit and terminated with a ‘1’ stop bit. The keyboard generates 11 clock

transitions (at around 20 - 30KHz) when the data is sent, and data is valid on the falling edge of the

clock.

Scan codes for most PS/2 keys are shown in the figure below.

Figure 13: PS/2 signal timings

Nexys2 Reference Manual

Digilent

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Mouse

The mouse outputs a clock and data signal when it is moved; otherwise, these signals remain at logic

‘1’. Each time the mouse is moved, three 11-bit words are sent from the mouse to the host device.

Each of the 11-bit words contains a ‘0’ start bit, followed by 8 bits of data (LSB first), followed by an

odd parity bit, and terminated with a ‘1’ stop bit. Thus, each data transmission contains 33 bits, where

bits 0, 11, and 22 are ‘0’ start bits, and bits 10, 21, and 33 are ‘1’ stop bits. The three 8-bit data fields

contain movement data as shown in the figure above. Data is valid at the falling edge of the clock, and

the clock period is 20 to 30KHz.

The mouse assumes a relative coordinate system wherein moving the mouse to the right generates a

positive number in the X field, and moving to the left generates a negative number. Likewise, moving

the mouse up generates a positive number in the Y field, and moving down represents a negative

number (the XS and YS bits in the status byte are the sign bits – a ‘1’ indicates a negative number).

The magnitude of the X and Y numbers represent the rate of mouse movement – the larger the

number, the faster the mouse is moving (the XV and YV bits in the status byte are movement overflow

indicators – a ‘1’ means overflow has occurred). If the mouse moves continuously, the 33-bit

transmissions are repeated every 50ms or so. The L and R fields in the status byte indicate Left and

Right button presses (a ‘1’ indicates the button is being pressed).

Figure 14: PS/2 keyboard scan codes

Figure 15: Mouse data format

Nexys2 Reference Manual

Digilent

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VGA Port

The Nexys2 board uses 10 FPGA signals to

create a VGA port with 8-bit color and the two

standard sync signals (HS – Horizontal Sync,

and VS – Vertical Sync). The color signals use

resistor-divider circuits that work in conjunction

with the 75-ohm termination resistance of the

VGA display to create eight signal levels on the

red and green VGA signals, and four on blue

(the human eye is less sensitive to blue levels).

This circuit, shown in figure 13, produces video

color signals that proceed in equal increments

between 0V (fully off) and 0.7V (fully on). Using

this circuit, 256 different colors can be

displayed, one for each unique 8-bit pattern. A

video controller circuit must be created in the

FPGA to drive the sync and color signals with

the correct timing in order to produce a working

display system.

VGA System Timing

VGA signal timings are specified, published,

copyrighted and sold by the VESA organization

(www.vesa.org). The following VGA system

timing information is provided as an example of

how a VGA monitor might be driven in 640 by 480 mode. For more precise information, or for

information on other VGA frequencies, refer to documentation available at the VESA website.

CRT-based VGA displays use amplitude-modulated moving electron beams (or cathode rays) to

display information on a phosphor-coated screen. LCD displays use an array of switches that can

impose a voltage across a small amount of

liquid crystal, thereby changing light

permittivity through the crystal on a pixel-

by-pixel basis. Although the following

description is limited to CRT displays, LCD

displays have evolved to use the same

signal timings as CRT displays (so the

“signals” discussion below pertains to both

CRTs and LCDs). Color CRT displays use

three electron beams (one for red, one for

blue, and one for green) to energize the

phosphor that coats the inner side of the

display end of a cathode ray tube (see

illustration). Electron beams emanate from

“electron guns” which are finely-pointed

heated cathodes placed in close proximity

to a positively charged annular plate called

a “grid”. The electrostatic force imposed by

the grid pulls rays of energized electrons

Figure 16: VGA pin definitions and Nexys2 circuit

Anode (entire screen)

High voltage

s pply (>20kV)

Deflection coils

Grid Electron g ns

(Red, Bl e, Green)

g n

control

grid

control

deflection

control

R,G,B signals

(to g ns)

Cathode ray t be

Cathode ray

VGA

cable

Figure 17: CRT deflection system

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