Cray X-MP Series Manuel utilisateur

RESEARCH

INC.

Any

shipment

country

outside

the

United States requires a U.S. Government

export

license.

CRAY COMPUTER SYSTEMS

CRAY X-MP SERIES

MODELS

MAINFRAME REFERENCE

MANUAL

HR-0032

CRAY RESEARCH, INC. This manual

parts thereof may

not

be reproduced in any form without

permission of CRAY RESEARCH, INC.

E i

RECORD OF REVISION

~ESEA~CHJ

INC.

PUBLICATION

NUMBER

HR-0032

Each time

thil

manuel il revised and reprinted, all

chan~

issued against

the

previous version in

the

form

change packets are

incorporated into

the

new version and

the

new version IS

Igned an alphabetic level. Between reprints, changes may be issued

against

the

current

version in

the

form of ch.ange peckets. Each change packet

assigned 8 numeric designator, starting with

for

the

first change packet

each revillon level.

Every

changed

a reprint

a change packet has

the

revision level

and

change packet number in

the

lower righthand

corner. Changes

part

P8SlI

are noted

a change bar along

the

margin

the

page. A change bar in

the

margin opposite

the

page number indicates

that

the

entire page is new; a

dot

ttle same place indicates

that

information hasbeen moved from

one

page

another,

but

has

not

otherwise

changed.

Requests for copies

Crav Research, Inc. publications and comments

about

these publications should

directed to:

CRAY RESEARCH, INC.,

1440

Northland Drive,

Mendota Heights, Minnesota

55120

Revision

BR-0032

Description

November, 1982 -

Original

printing.

July,

1984 -

Reprint

with

revision.

Instructions

were added

for

hardware

performance

monitoring

and

SECDED

maintenance

functions.

Information

was

also

added

explain

how

the

Second

Vector

Logical

functional

unit

used

although

this

functional

unit

not

available

all

systems.

Numerous

technical

and

editorial

changes

and

correccions

were

also

made.

This

revision

obsoletes

all

printings.

PREFACE

This

publication

describes

the

functions

CRAY

X-MP

Series

dual-processor

computer

systems,

models

and

24.

written

assist

programmers

and

engineers

and

assumes

familiarity

with

digital

computers.

The

manual

describes

the

overall

computer

system,

its

configurations,

and

equipment.

also

describes

the

operation

the

Central

Processing

Units

that

execute

instructions,

provide

memory

protection,

report

hardware

exceptions,

and

provide

interprocessor

communications

within

the

computer

systems.

Details

the

I/O

Subsystem,

the

disk

storage

units,

and

the

Solid-state

Storage

Device

are

given

the

following

publications:

HR-0030

HR-0630

HR-003l

I/O

Subsystem

Hardware

Reference

Manual

Mass

Storage

Subsystem

Hardware

Reference

Manual

Solid-state

Storage

Device

(SSO@)

Reference

Manual

HR-0032

///////////////////////////////////////////////////////

WARNING

This

equipment

generates,

uses,

and

can

radiate

radio

frequency

energy

and

not

installed

and

used

accordance

with

the

instructions

manual,

may

cause

interference

radio

communications.

has

been

tested

and

found

comply

with

the

limits

for

Class

computing

device

pursuant

Subpart

Part

FCC

Rules,

which

are

designed

provide

reasonable

protection

against

such

interference

when

operated

commercial

environment.

Operation

this

equipment

residential

area

likely

cause

interference

which

case

the

user

his

own

expense

will

required

take

whatever

measures

may

required

correct

the

interference.

///////////////////////////////////////////////////////

iii

CONTENTS,

PREFACE

SYSTEM

DESCRIPTION

•

INTRODUCTION

•

CONVENTIONS

Italics

•

conventions

Number

conventions

Clock

per

iod

SYSTEM

COMPONENTS

Central

Processing

Units

Interfaces

I/O

Subsystem

•

Disk

storage

units.

Solid-state

Storage

Device

Condensing

units

Power

distribution

units

Motor-generator

units

•

SYSTEM

CONFIGURATION

•

CPU

SHARED

RESOURCES

•

INTRODUCTION

•

CENTRAL

MEMORY

•

Memory

organization

•

Memory

addressing

•

Memory

addressing

for

6-co1umn

mainframe

•

Memory

addressing

for

12-co1umn

mainframe

Memory

access

•

Conflict

resolution

Bank Busy

conflict

Simultaneous

Bank

conflict

Section

Access

conflict

•

Memory

access

priorities

•

16-bank

phasing

•

Memory

error

correction

•

INTER-CPU

COMMUNICATION

SECTION

Real-time

clock

•

Inter-CPU

communication

and

control

•

Shared

Address

and

Shared

Scalar

registers

•

Semaphore

registers

HR-0032 v A

iii

1-1

1-4

1-5

1-7

1-9

1-11

1-12

1-13

1-14

1-15

1-16

2-1

2-2

2-3

2-4

2-7

2-8

2-10

2-11

2-12

CPU

SHARED

RESOURCES

(continued)

CPU

INPUT/OUTPUT

SECTION

• • • • • • • • • • • • • •

Data

transfer

for

Solid-state

Storage

Device

Data

transfer

for

I/O

Subsystem

• • • • • •

6 Mbyte

per

second

channels

• • • • •

Multi-CPU programming • • • • • •

6 Mbyte

per

second

channel

operation

••••

•

Input

channel

programming • • • • • •

Input

channel

error

conditions

••••••

Output

channel

programming

••••

Programmed

master

clear

external

device

Memory

access

• • • • •

I/O

lockout

• • • • • • • • • •

Memory

bank

conflicts

• • •

I/O

memory

conflicts

.......

. . .. . ...

. ...

· ....

. ..

·..

·.. ...

· .

·..

I/O

memory

request

conditions

•

I/O

memory

addressing

• • • • • .....

CPU

CONTROL

SECTION

.. ... .. ... .. . .. .. ... . .

INTRODUCTION

• • • • • • • • •

INSTRUCTION

ISSUE

AND

CONTROL

Program

Address

Instruction

Parcel

Current

Instruction

Parcel

Lower

Instruction

Parcel

•

Instruction

buffers

EXCHANGE

MECHANISM

• • • • • • • • •

Exchange

package

Processor

number

vector

not

used

(VNU)

Enable

second

vector

logical

(ESVL)

Memory

error

data

••••

Exchange

registers

Exchange

Address

Mode

••••••

Flag

••••••

Cluster

Number

Program

State

registers

••

• • •

registers

•••••

·...

· .

· ......

· ..

· .

Program

Address

•

Memory

field

registers

·.. ....

Active

Exchange Package • • • •

Exchange

sequence

• • • • • • •

Exchange

initiated

deadstart

sequence

•

Exchange

initiated

Interrupt

flag

set

•

Exchange

initiated

program

exit

• •

Exchange

sequence

issue

conditions

Exchange Package management • • · ..

. .

...

HR-0032

2-14

2-15

2-16

2-17

2-18

2-19

2-20

2-21

2-24

2-25

3-1

3-2

3-3

3-5

3-7

3-8

3-9

3-11

3-12

3-13

3-14

3-15

CPU

CONTROL

SECTION

(continued)

MEMORY

FIELD

PROTECTION

.....

Instruction

Base

Address

•

Instruction

Limit

Address

Data

Base

Address

Data

Limit

Address

•

Program

range

error

•

Operand

range

error

• •

PROGRAMMABLE

CLOCK

•

Instructions

Interrupt

Interval

•

Interrupt

Countdown

counter

•

Clear

programmable

clock

interrupt

request

PERFOBMANCE

MONITOR

DEADSTART

SEQUENCE

• • • • •

CPU

COMPUTATION

SECTION

INTRODUCTION

•

OPERATING

REGISTERS

ADDRESS

REGISTERS

registers

SCALAR

REGISTERS

registers

•

VECTOR

REGISTERS

•

registers

reservations

and

chaining

•

Vector

control

registers

Vector

Length

•

Vector

Mask

•

FUNCTIONAL

UNITS

• • • • • •

HR-0032

Address

functional

units

Address

Add

functional

unit

Address

Multiply

functional

unit

• •

Scalar

functional

units

•

Scalar

Add

functional

unit

•

Scalar

Shift

functional

unit

Scalar

Logical

functional

unit

•

Scalar

Population/Parity/Leading

Zero

functional

unit

Vector

functional

units

•

Vector

functional

unit

reservation

•

Vector

Add

functional

unit

•

Vector

Shift

functional

unit

•

Full

Vector

Logical

functional

unit

Second

Vector

Logical

functional

unit

Vector

Population/parity

functional

unit

vii

3-16

3-17

3-18

3-19

3-20

3-21

4-1

4-3

4-5

4-6

4-8

4-9

4-12

4-13

4-14

4-15

4-16

4-17

4-18

4-19

FONC'lIONAL

UNITS

(continued)

·..

Floating-point

functional

units

• • • •

Floating-point

Add

functional

unit

••

• • • • •

Floating-point

Multiply

functional

unit

Reciprocal

Approximation

functional

unit

• ·..

ARITHMETIC

OPERATIONS

• • • • • • • • • • • • • • • • • ..

Integer

arithmetic

•••••••••••

. ..

Floating-point

arithmetic

• • • • • • • • • • •

Normalized

floating-point

numbers

•••••

Floating-point

range

errors

• • •

Floating-point

Add

functional

unit

• • • • •

Floating-point

Multiply

functional

unit

• • •

Floating-point

Reciprocal

Approximation

functional

unit

• • • • • • • • • • •

Double-precision

numbers • • • • • • • • • •

Addition

algorithm

• • • • • • • • • • • • •

Multiplication

algorithm

• • • •

Division

algorithm

• • •

Newton's

method

•••

..... ...

Derivation

the

division

algorithm

• • ·.

LOGICAL

OPERATIONS

• • • • • • • • •

CPU

INSTRUCTIONS

••

.... .. .. · ..

INSTRUCTION

FORMAT

• .. · .

I-parcel

instruction

format

with

discrete

and k

fields

••

• • • • • • • • • • • • • • • •

I-parcel

instruction

format

with

combined j

and k

fields

•••

• • • • • • • • • • •

2-parcel

instruction

format

with

combined

and m

fields

• • • • • • • • • • • • • • • • •

2-parcel

instruction

format

with

combined

and m

fields

• • • • • • • • •

SPECIAL

VALUES

• • • •

INSTRUCTION

ISSUE

• • •

INSTRUCTION

DESCRIPTIONS

• •

APPENDIX

SECTION

4-20

4-21

4-22

4-23

4-24

4-25

4-27

4-28

4-30

4-31

4-35

5-1

5-2

5-3

5-4

5-5

5-6

INSTRUCTION

SUMMARY

FOR

CRAY

X-MP

MODELS

AND

24 • • • • • • •

A-I

B. 6

MBYTE

PER

SEOOND

CHANNEL

DESCRIPTIONS

... . . .

INTRODUCTION

• • • • • • • • • • .. ...

MBYTE

PER

SEOOND

INPUT

CHANNEL

SIGNAL

SEQUENCE.

Data

bits

through

• • • • • • • • • •

parity

bits

through

3 • • • • • • • • • • •

HR-0032

viii

...

.... . .

B-1

8-1

B-1

B-2

MBYTE

PER

SEOOND

INPUT

CHANNEL

SIGNAL

SEQUENCE

(continued)

Ready

signal

• • • • • • • • • • • • • • •

Resume

signal

• • • • • • • • • • • • • • • •

Disconnect

signal

• • • • • • • • • •

MBYTE

PER

SECOND

OUTPUT

CHANNEL

SIGNAL

SEQUENCE

Data

bits

through

••

• • • • • • • •

Parity

bits

through

3 •

Ready

signal

• • • •

Resume

signal

• • • • •

Disconnect

signal

• • • • .. .

. ...

PERFORMANCE

MONITOR

. . . . . .. . . .. . . ... . .. . . .

INTRODUCTION

• • • • • • • • •

SELECTING

PERFORMANCE

EVENTS

READING

PERFORMANCE

RESULTS

TESTING

PERFORMANCE

COUNTERS •

.... . .. . . . .

. .. .. . . .. . . . .

SECDED

MAINTENANCE

FUNCTIONS

. . . . . .. ... . . . . . . . .

INTRODUCTION

• • • • • • • • • • • • •

VERIFICATION

CHECK

BIT

STORAGE

VERIFICATION

CHECK

BIT

GENERATION

•

VERIFICATION

ERROR

DETECTION

AND

CORRECTION

•

CLEARING

MAINTENANCE

MODE

FUNCTIONS

••••••

.. .

FIGURES

1-1

CRAY

X-MP

Model 22

l2-column

mainframe

with

1-2

1-3

1-4

1-5

1-6

1-7

1-8

1-9

1-10

1-11

1-12

1-13

2-1

2-2

2-3

2-4

Cray

I/O

Subsystem

and

SSD

••••••

• • • • • • • •

Basic

organization

the

dual-processor

system

Control

and

data

paths

for

single

CPU

CRAY

X-MP

Models 22

6-column

mainframe

chassis

• • • • •

TYPical

interface

cabinet

• • • •

I/O

Subsystem

chassis

•••

• • • • ...

DD-29

Disk

Storage

Unit

• • • • • • •

Solid-state

Storage

Device

chassis

• • • • • • • • • • • • • •

Condensing

unit

••••••••••

• • •

Power

distribution

units

• • • • • • • • •

Motor-generator

equipment

• • •

Block

diagram

CRAY

X-MP

dual-processor

system

with

full

disk

capacity

•••••••••

• • • • • • • • • •

Block

diagram

CRAY

dual-processor

system

with

block

multiplexer

channels

•••••

• • • • • • •

Central

Memory

organization

for

dual-processor

system

6-column

memory

address

(32

banks)

• •

6-column

memory

address

(16

banks)

• • • •

12-co1umn memory

address

(32

banks)

•••

HR-0032

B-3

B-4

B-5

C-l

C-1

C-l

C-3

D-l

D-1

D-2

D-3

1-2

1-5

1-6

1-7

1-8

1-10

1-11

1-12

1-13

1-14

1-15

1-16

1-17

2-2

2-3

2-4

FIGURES

(continued)

2-5

2-6

2-7

2-8

2-9

2-10

2-11

3-1

3-2

3-3

4-1

4-2

4-3

4-4

4-5

4-6

4-7

4-8

4-9

4-10

5-1

5-2

5-3

5-4

5-5

5-6

5-7

5-8

5-9

5-10

5-11

5-12

l2-column

memory

address

(16

banks)

• • • • • • • • • • •

Memory

data

path

with

SECDED

• • • • • • • • •

Error

correction

matrix

• • • • • • • • •

Shared

registers

and

real-time

clock

• • • • • • • • •

Basic

I/O

program

flowchart

•••••••••

• •

Channel

I/O

control

(shown

for

one

processor)

Input/output

data

paths

••••••••

Instruction

issue

and

control

elements

• • • • • • • • • • • •

Instruction

buffers

•••••••••••••

Exchange

package

for

dual-processor

system

•

Address

registers

and

functional

units

•

Scalar

registers

and

functional

units

••••

vector

registers

and

functional

units

••••

Integer

data

formats

• • • • •

• • • •

. ..

Floating-point

data

format

• • • • • • • • • • • • • • • •

Exponent

matrix

for

Floating-point

Multiply

unit

• • • • •

Integer

multiply

Floating-point

Multiply

functional

unit

••••

• • • • • • • • • • • •

49-bit

floating-point

addition

• • • • • • • • • •

Floating-point

multiply

partial-product

sums

pyramid

• •

Newton's

method

•••••••••••••••••••••••

General

form

for

instructions

•••••••••••

I-parcel

instruction

format

with

discrete

j and k

fields

•

I-parcel

instruction

format

with

combined j and

fields

• • • • • • • • • • • • • • • • • • • • • • • • • • •

2-parcel

instruction

format

with

combined

k, and

fields

• • • • • • • • • • • • • • • • • • • • • • • • •

2-parcel

instruction

format

for

branch

with

combined

and m

fields

•••••••••

2-parcel

instruction

format

for

24-bit

immediate

constant

with

combined

and

fields

•••••••••••

vector

left

double

shift,

first

element,

greater

than

1 • •

vector

left

double

shift,

second

element,

greater

than

vector

left

double

shift,

last

element

• • • • • • • •

vector

right

double

shift,

first

element

•

vector

right

double

shift,

second

element,

greater

than

••••••

• • • • • •

vector

right

double

shift,

last

operation

••••

• • • • • •

TABLES

1-1

2-1

2-2

3-1

CRAY

x~p

dual-processor

system

characteristics

Access

conflicts

shared

registers

dual-processor

computer

• • • •

Channel

word

assembly/disassembly

Exchange

Package

assignments

• • • •

HR-0032 x A

2-4

2-8

2-9

2-11

2-19

2-22

2-23

3-1

3-3

3-6

4-4

4-7

4-10

4-22

4-23

4-25

4-27

4-28

4-29

4-31

5-1

5-2

5-3

5-4

5-71

5-72

5-73

1-3

2-13

2-18

3-7

Ce manuel convient aux modèles suivants

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