AN202
V1.0 | Page 3/73
4.1.21 OSCCON（Addr:0x8F）................................................................................................... 30
4.1.22 PR2（Addr:0x92）............................................................................................................ 31
4.1.23 WPUA（Addr:0x95）........................................................................................................ 31
4.1.24 IOCA（Addr:0x96）.......................................................................................................... 33
4.1.25 VRCON（Addr:0x99）...................................................................................................... 33
4.1.26 EEDAT（Addr:0x9A）....................................................................................................... 34
4.1.27 EEADR（Addr:0x9B）...................................................................................................... 34
4.1.28 EECON1（Addr:0x9C）................................................................................................... 34
4.1.29 EECON2（Addr:0x9D）................................................................................................... 35
4.1.30 Configuration Register UCFGx ......................................................................................... 35
4.1.31 PCL and PCLATH.............................................................................................................. 37
4.1.32 INDFand FSR Register ..................................................................................................... 38
5MCU SystemClock Source.................................................................................................................... 39
5.1 Clock Source Mode................................................................................................................... 39
5.1.1 Internal Clock Mode .......................................................................................................... 40
5.1.2 Frequency Select Bit（IRCF）......................................................................................... 40
5.1.3 Clock Switch Timing of HFINTOSC and LFINTOSC......................................................... 40
5.2 Clock Switching......................................................................................................................... 41
5.2.1 System Clock Select Bit (SCS) ......................................................................................... 41
5.2.2 Oscillator Start-up Timeout Status(OSTS) Bit................................................................... 42
5.3 Two-Speed Clock Start-up Mode.............................................................................................. 42
5.3.1 Two-Speed Start-up Mode Configuration.......................................................................... 42
5.3.2 Two-Speed Start-up Sequence......................................................................................... 43
5.4 Fail-Safe Clock Monitor............................................................................................................. 43
5.4.1 Fail-Safe Detection............................................................................................................ 43
5.4.2 Fail-Safe Operation........................................................................................................... 43
5.4.3 Fail-Safe Condition Being Cleared.................................................................................... 44
5.4.4 Reset or Wake-up from Sleep........................................................................................... 44
6Reset Timing........................................................................................................................................... 45
6.1 Power-on Reset (POR)............................................................................................................. 46
6.2 External Reset (MCLR)............................................................................................................. 46
6.3 Power-up Timer (PWRT)........................................................................................................... 46
6.4 Brown-out Reset (BOR（LVR）).............................................................................................. 47
6.5 Error Instruction Reset.............................................................................................................. 47
6.6 Timeout Action .......................................................................................................................... 47
7BOOT....................................................................................................................................................... 50
