Atmel AVR1306 Manuel utilisateur

8-bit

Microcontrollers

Application Note

Rev. 8045A-AVR-02/08

AVR1306: Using the XMEGA Timer/Counter

Features

• True 16 bit operation

• Double buffered timer period setting

• 4 (2) compare or capture channels per timer

- 4 channels on each Timer 0

- 2 channels on each Timer 1

- Double buffered

• 32 bit operation with 32 bit input capture by timer cascading

• Event counter

• Timer overflow and error interrupts (and events)

• Input capture interrupts (and events)

1 Introduction

The XMEGA™ Timer/Counter modules are true 16-bit Timer/Counters with Input

Capture and Pulse Width Modulation (PWM) functionality.

This application note gives an introduction on how to use the XMEGA

Timer/Counter modules for timing, Input Capture and PWM.

2 AVR1306 8045A-AVR-02/08

2 Definitions

The definitions listed in Table 2-1 will be used throughout this document.

Table 2-1. Definitions used in this document.

Name Description

BOTTOM The Timer/Counter reaches the BOTTOM when it becomes zero.

MAX The Timer/Counter reaches it MAXimum when it becomes 0xFFFF.

TOP The Timer/Counter reaches the TOP when it becomes equal to the highest value

in the count sequence. The TOP value can be equal to the period register

(PER[H:L]) or Compare or Capture register A (CCA[H:L]), depending on the

selected Waveform Generation Mode (WGM).

UPDATE The Timer/Counter signalizes an update when it reaches BOTTOM or TOP

depending on the selected waveform generation mode (WGM).

3 Module Overview

The XMEGA Timer/Counter (TC) modules are 16-bit Timer/Counters with input

capture and compare match with optional output to I/O pin. Typical applications

include:

•Timing.

•Periodic interrupt/event generation.

•Pulse Width Modulation.

•Event time stamping.

•Event counting.

•Signal parameter measurements (Period, duty cycle, etc.).

3.1 Timer/Counter Variants

An XMEGA TC module is related to an I/O port through the I/O pins it can control with

the output compare module. The naming of the TC modules reflects the I/O port it is

connected and the available features for that Timer/Counter. Each TC module has a

name that follows the form: TCxn. TC is short for Timer/Counter, xindicates the port it

is connected to and n is the TC number within PORTx. As an example, TCD0 is

Timer/Counter 0 connected to PORTD.

Timers are available on PORTC, PORTD, PORTE or PORTF, if available on device.

Timer0 on each port has 4 compare or capture channels, while Timer1 has 2

compare or capture channels. Figure 3-1 shows how the output compare channels

are connected to the associated I/O port. Timer0 has its outputs connected to pins 0-

3 within the port, while Timer1 is mapped to pins 4 and 5.

AVR1306

Figure 3-1. Output compare to I/O port pin mapping PORTx

TCx0

CCA

CCB

CCC

CCD

TCx1 CCA

CCB

Px0

Px1

Px2

Px3

Px4

Px5

Px6

Px7

3.2 Clock Sources

The available clock source selections for the XMEGA TC modules are listed in Table

3-1.

Table 3-1. XMEGA Timer/Counter clock sources.

Symbol Clock selection

TC_CSEL_OFF_gc TC off (no clock selected)

TC_CSEL_DIV1_gc fCLK,SYS

TC_CSEL_DIV2_gc fCLK,SYS / 2

TC_CSEL_DIV4_gc fCLK,SYS / 4

TC_CSEL_DIV8_gc fCLK,SYS / 8

TC_CSEL_DIV64_gc fCLK,SYS /64

TC_CSEL_DIV256_gc fCLK,SYS / 256

TC_CSEL_DIV1024_gc fCLK,SYS / 1024

TC_CSEL_EV0_gc Event channel 0

TC_CSEL_EV1_gc Event channel 1

TC_CSEL_EV2_gc Event channel 2

TC_CSEL_EV3_gc Event channel 3

TC_CSEL_EV4_gc Event channel 4

TC_CSEL_EV5_gc Event channel 5

TC_CSEL_EV6_gc Event channel 6

TC_CSEL_EV7_gc Event channel 7

3.3 Interrupts

Interrupts can be generated in the following situations:

8045A-AVR-02/08

4 AVR1306 8045A-AVR-02/08

•Timer overflow.

•Timer error (Input capture data lost because input capture buffer is full).

•Compare or capture. Separate interrupts for each channel.

3.4 Period Setting

Each TC module has a period register (PER[H:L]) that controls the TOP value of the

counter (except in frequency generation mode).

The PER[H:L] register is double buffered through the PERBUF[H:L] register. Double

buffered registers are covered in section 3.7.

The PER[H:L] register is automatically initialized to 0xFFFF after a reset.

3.5 Capture or Compare Channels

Each TC module has two or four capture or compare channels. The channels can be

set up for either input capture or compare match. It is not possible to use the same

TC module for both input capture and compare match at the same time. Input capture

can be used to time stamp event, measuring waveform parameters like frequency or

duty cycle. The compare match feature can be used to generate interrupts or events

at certain time points, or for PWM/waveform generation.

The compare or capture channels consist of a set of 16-bit registers named CCx[H:L],

where x indicates the channel. Timer0, with 4 channels, has CCA[H:L], CCB[H:L],

CCC[H:L] and CCD[H:L], while Timer1 has CCA[H:L] and CCB[H:L]. In addition, each

CCx[H:L] register has an associated buffer register CCxBUF[H:L]. Double buffered

registers are covered in detail in section 3.7.

When used for input capture, the value of the PER register determines how input

capture values are interpreted. If bit 15 of PER is set to one, the entire 16 bit counter

value is stored in the capture buffer. If bit 15 of PER is zero, the event polarity is

stored in bit 15 in the capture buffer. This can be used to measure frequency

parameters like duty cycle using only one input pin and one capture channel.

3.6 Event Input Selection

The TC input capture system uses the XMEGA event system to trigger an input

capture. Refer to application note AVR1001 for more information about the XMEGA

event system.

When the TC is used for input capture, all enabled input capture channels must be

associated with an event channel. The EVSEL[3:0] bits of the CTRLD register select

the event channels that are associated with the input capture channels. EVSEL3 must

be 1 to select an event source. EVSEL[2:0] selects between the 8 event channels.

The event channels associated with the different channels cannot be selected

individually. Table 3-2 shows the mapping between global event channels and input

capture channels when EVSEL3 = 1 and EVSEL[2:0] = N. The “%” is the modulo

operator. Note that when a set of event channels have been selected for the TC, this

does not mean that these event channels are used exclusively by the TC. The TC

simply “listens” to the selected channels and is able to receive events on these event

channels.

AVR1306

8045A-AVR-02/08

Table 3-2. Event channel to input capture channel mapping.

Input capture channel Global event channel

A N

B (N + 1) % 8

C (If available) (N + 2) % 8

D (If available) (N + 3) % 8

Example 1:

EVSEL3 = 1 and EVSEL[2:0] = 0 means that input capture channels A, B, C and D

are triggered by event channels 0, 1, 2 and 3 respectively.

Example 2:

EVSEL3 = 1 and EVSEL[2:0] = 6 means that input capture channels A, B, C and D

are triggered by event channels 6, 7, 0 and 1 respectively.

If the event source is subject to noise, e.g. caused by the bouncing of an external

switch, it is possible to enable digital filtering on the event channel. See application

note AVR1001 for more information on the event system and its digital filtering

capabilities.

3.7 Double Buffered Registers

The PER[H:L] and CCx[H:L] registers in the TC modules are double buffered. They

have dedicated buffer registers named PERBUF[H:L] and CCxBUF[H:L].

Using the PER[H:L] register as an example: when writing to PER[H:L] directly, the

value will be updated immediately. If the value is instead written to PERBUF[H:L], the

value of PER[H:L] will not be updated instantly, but instead transferred from

PERBUF[H:L] on the next UPDATE condition. Each buffer register has a related

“buffer valid” flag in the CTRLE register. The buffer valid flag is set when a new value

is written to the corresponding buffer register. The flag is cleared when the buffer

It is also possible to lock the automatic update from buffer registers. This enables

simultaneous updates of several registers at one update condition. Setting the Timer

Lock Update (LUPD) bit in the CTRLE register enables update locking.

When the TC module is used for PWM, the buffering is typically used to make sure

that the duty cycles are not altered in the middle of a PWM period, and to synchronize

changes to all PWM channels. New compare/TOP values are typically written to the

buffer registers instead of writing directly to the CCx registers. This way, all PWM

channels can be updated at the same time (on the UPDATE event).

In Input Capture mode, the input capture values are double-buffered. A new input

capture-value is first put in the CCxBUF[H:L] register. Values stored in CCxBUF[H:L]

are transferred to CCx[H:L] if the CCIFx flag is not set. The CCIFx flag is cleared

automatically when CCx[H:L] is read. In practice, this means that the user only needs

to read the CCx[H:L] register, while the rest is handled automatically.

3.8 Modes of Operation

The TC has six different modes of operation:

6 AVR1306

•Normal mode.

•Frequency Generation mode.

•Single Slope PWM.

•Dual Slope PWM, overflow on TOP.

•Dual Slope PWM, overflow on TOP and BOTTOM.

•Dual Slope PWM, overflow on BOTTOM.

3.8.1 Normal Mode

In Normal Mode, the counter will count in the direction set by the DIR bit in CTRLF for

each clock until it reaches TOP set by PER[H:L] or BOTTOM (zero). When TOP is

reached when up-counting the counter will be set to zero when the next clock is

given. If the TC is down-counting the value will wrap around to the value in PER[H:L]

after reaching BOTTOM.

Figure 3-2. Normal mode with period setting.

Time

Timer value

TOP

As shown in Figure 3-2, changing the counter value while the counter is running is

allowed. The write access has higher priority than count, clear, or reload and will be

immediate. However, if the value written is outside the BOTTOM-TOP boundary the

counter either has to count down until TOP is reached or count up until wraparound

(passing MAX) for the timer to re-stabilize to the period time.

This mode of operation must be used when using the Timer/Counter for Input

Capture.

3.8.2 Frequency Generation Mode

There is little difference between the frequency waveform generation mode (FRQ)

and the normal mode of operation. For FRQ the period (T) is controlled by the

CCA[H:L] register instead of PER[H:L], which in this case is not in use. In addition the

Waveform Generation (WG) output is toggled on each compare match between

CNT[H:L] and CCA[H:L] as shown in Figure 3-3.

8045A-AVR-02/08

AVR1306

Figure 3-3. Frequency Generation Mode

TCNT

MAX

"update"

TOP

CNTwrittenDirectionChange

Period (T)

BOT

WGOutput

The waveform generated will have a maximum frequency of fclk/2 when CCA[H:L] is

set to zero (0x0000). The waveform frequency is defined by Equation 3-1.

Equation 3-1. Frequency Calculation, Frequency generation mode

()

12 +⋅

=CCAN f

fCLK

FRQ

Where Nrepresents the TC clock prescaler.

The Overflow Status Flag (OVFIF) or Compare A Flag (CCAIF) can be used to

generate interrupts. If enabled, the interrupt handler routine can be used for updating

CCA[H:L] to change the output frequency.

3.8.3 Single Slope PWM Mode

As Figure 3-4 shows, in this mode of operation the counter counts from BOTTOM to

TOP then restarts from BOTTOM. The waveform generator output is set on the

compare match between the count and compare registers, and cleared at TOP.

Figure 3-4. Single slope PWM

CNT

MAX

TOP

Period (T) "match"

BOT

WGOutput

CCx=BOT

CCx

CCx=TOP "update"

The single-slope Pulse Width Modulation (PWM) provides twice the PWM frequency

compared to dual-slope PWM. The high frequency makes this mode well suited for

power regulation, rectification, and DAC applications. High frequency allows

physically small sized external filtering components, which reduces total system cost.

The period register (PER[H:L]) defines the PWM resolution. The minimum resolution

allowed for this module is 2-bit (PER[H:L]=0x0003), and maximum resolution is 16-bit

8045A-AVR-02/08

8 AVR1306

(PER[H:L]=MAX). Equation 3-2 can be used to calculate the exact bit resolution for

single-slope PWM.

Equation 3-2. PWM Resolution, Single Slope PWM Mode

(

)

1log2_

PERR SSPWM

The PWM base frequency depends on the period setting (PER[H:L]), system clock

frequency, and clock prescaler. The PWM base frequency can be calculated using

Equation 3-3.

Equation 3-3. Frequency calculation, Single Slope PWM Mode

()

=PERN f

fCLK

SSPWM

Where Nrepresents the TC clock prescaler.

The Overflow Status Flag (OVFIF) or Compare Flag (CCxIF) can be used to generate

interrupts. If enabled, the interrupt service routine can be used for updating the period

and compare buffer values.

3.8.4 Dual Slope PWM Modes

The counter behavior in dual-slope operation is shown in Figure 3-5. The counter

counts repeatedly from BOTTOM to TOP and then to BOTTOM. When the counter

hits BOTTOM or TOP, the counter changes direction immediately, holding the

BOTTOM and TOP values for only one TC clock cycle. The current counting direction

can be determined by inspecting the DIR flag in CTRLF.

The Waveform Generation (WG) output is set on BOTTOM and cleared on compare

match. The output duty cycle is thus proportional to the compare value.

Figure 3-5. Dual slope PWM

CNT

MAX

TOP

Period (T)

BOT

WGOutput

CCx=BOT

CCx

CCx=TOP "match"

"update"

The dual-slope PWM result in a lower operating frequency at equal resolution

compared to the single-slope PWM mode.

The period register (PER[H:L]) defines the PWM resolution. The minimum resolution

allowed for this module is 2-bit (PER[H:L]=0x0003), and maximum resolution is 16-bit

(PER[H:L]=0xFFFF). Equation 3-4 can be used for calculate the exact resolution for

dual-slope PWM.

8045A-AVR-02/08

AVR1306

Equation 3-4. PWM Resolution, Dual Slope PWM Mode

(

)

1log2_

PERR DSPWM

The PWM base frequency depends on the period setting (PER[H:L]), system clock

frequency and clock prescaler and can be calculated using Equation 3-5.

Equation 3-5. Frequency calculation, Dual Slope PWM Mode

PER

fCLK

DSPWM

⋅

Where Nrepresents the TC clock prescaler.

The Overflow Status Flag (OVFIF) or Compare Flag (CCxIF) can be used to generate

interrupts. If enabled, the interrupt service routine can be used for updating the period

and compare buffer values.

3.9 Timer/Counter Commands

The CMD[1:0] bits in CTRLFSET are used to issue special commands to the TC.

These are described below.

3.9.1 Force Update

The “Force update” command is used to force an UPDATE condition. Buffer registers

are copied to their destination when the UPDATE conditions are met. Issuing this

command forces an UPDATE condition regardless of the counter value. This can be

used to update both the period and compare registers at the exact same time. In input

capture mode, the “Force update” command only has effect on the PERBUF/PER

registers. See section 3.7 for more information about double buffered registers.

3.9.2 Force Restart

The “Force restart” command clears the CNT[H:L] registers and the direction bit to its

reset value.

3.9.3 Force Hard Reset

The “Force hard reset” command puts all registers in that TC instance back to their

reset state. For safety reasons, the TC clock selection must be set to OFF for this

command to have any effect.

4 Accessing 16-bit Registers

Since the XMEGA has a bus width of 8 bits, 16-bit registers are accessed as two 8-bit

registers. All accesses to 16-bit registers are performed using a hardware-controlled 8

bit temporary register to ensure concurrent update of the high and low byte registers.

Each Timer/Counter has one dedicated temporary register, TEMP, that is used for

this purpose. The TEMP register is shared for all 16-bit accesses in that TC module.

Usage of the TEMP register is automatically handled when the correct byte access

order is used, but it is important to understand the mechanism to avoid corruption of

registers.

Note that on the XMEGA, the byte order for multi-byte access is always from the least

significant byte to the most significant byte.

8045A-AVR-02/08

10 AVR1306

4.1 16-bit Read

Figure 4-1 illustrates how to perform a 16-bit read of CNT, and what happens

internally:

1. Read CNTL. This will cause the contents of CNTH to be transferred to TEMP in the

same clock cycle.

2. Read CNTH. This will automatically cause the contents of TEMP to be read instead

of the current value of CNTH.

The result is a snapshot of the 16-bit CNT[H:L] value at the time CNTL was read.

Figure 4-1. 16- bit read access.

CNTH CNTL

TEMP

CNTH CNTL

TEMP

R(n+1)

RnR(n+1)

4.2 16-bit Write

Figure 4-2 illustrates how to perform a 16-bit and what happens internally:

1. Write CNTL. This will cause the TEMP register to be updated with the new value

for CNTL.

2. Write CNTH. This will cause CNTL to be updated with the contents of the TEMP

The result is that the 16-bit CNT[H:L] value is updated in the same clock cycle.

8045A-AVR-02/08

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