Analog Devices AD9694 Guide de l'administrateur

AVDD_BUF

AVDD_0P9

AD9694 DUT

ANALOG INPUTS

HIGH SFDR VARIANT

INPUT A

AVDD_BUF

VIP_B

AVDD_1P8

PIN 55

DSYNCB_AB_P

DSYNCB_AB_N

FD_D

SDIO

VIP_C

AVDD_BUF

AVDD_1P8_SPI

CLKP

CLKN

VIN_A

CSB

SEROUT_CD_0N

DRVDD_0P9

SEROUT_CD_1P

AVDD_0P9

VCM_AB

VIN_B

SEROUT_AB_0N

PIN 64

PIN 9PIN 1

PIN 31PIN 15

SEROUT_CD_1N

SEROUT_AB_1P

PIN 22PIN 31PIN 22

DRIVER DECOUPLING CAPACITORS

SEROUT_AB_1N

INPUT B

INPUT D

AVDD_1P8

PIN 62

DRVDD2

DVDD_0P9

INPUT C

FD_A

PLACE 10 OHM SERIES R CLOSE TO DIFF C AND CLOSE TO DUT

FD_B

DRVDD_0P9

SEROUT_AB_0P

FAST_DET_C

FAST_DET_D

DSYNCB_CD_N

DSYNCB_CD_P

VIP_D

VIN_D

AVDD_1P8

AVDD_0P9

SEROUT_CD_0P

PDN_STBY

FAST_DET_A

FAST_DET_B

PIN 49

PLACE 10 OHM SERIES R CLOSE TO DIFF C AND CLOSE TO DUT

PIN 6

VIP_A

AVDD_0P9

AVDD_1P8

AVDD_0P9_DSYSREF

DSYSREFP

AVDD_1P8

AVDD_0P9

AGND_DSYSREF_ISO

AVDD_BUF

AVDD_1P8

DSYSREFN

AGND_DSYSREF

AVDD_0P9

AVDD_1P8

VIN_C

SCLK

DVDD_0P9

VCM_CD_VREF

PLACE 10 OHM SERIES R CLOSE TO DIFF C AND CLOSE TO DUT

PIN 70

FD_C

PIN 57

PIN 72

PIN 44PIN 11

PIN 72

PIN 5

PLACE 10 OHM SERIES R CLOSE TO DIFF C AND CLOSE TO DUT

PIN 4 PIN 40 PIN 42

DIGITAL DECOUPLING CAPACITORS

PIN 13

ANALOG DECOUPLING CAPACITORS

PIN 4PIN 54

AVDD_0P9_SAMPLE_2

AVDD_1P8

C152

1 7

LDO UPREV

AD9694

AD9694 EVALUATION BOARD

NONE

9694CE04

J.HARRIS

T106

4 3

T107

4 3

T105 5

1T104

4 3

T101 5

T100

C145C139

C183

R140

C136

R141

C137

TP100

TP101

C180C179

C154 C158C157C156C155

C172C169C168

C153C151

C150C149

C144C143C142C141C140

C147C148C146

4312

PAD

4213

4114

496

469

4411

U100

R105

R104

C119

C118

R120

R122

C121

R121

R123

C120

R124

R126

R128

C122

C123

R125

R127

R129

C124

C125

R158

5432

J104

C126

R159

5432

J105

C131

R137

C127

R130

R132

C128C130

R134

R136

R138

C132C134

R162

R131

R133

C129

R135R139

C133C135

R163

5432

J106

5432

J107

C110

C114

R117

C109

R110

R112

C112

R113

R111

C111

R114

R116

R118

C113

R115R119

C115

T102

C116

R154

4 3

T103

5432

J102

C117

R155

5432

J103

R150

5432

J100

C100

R100

C101

R102

C103

R106

R108

C104

C105C107

R101

R103

C102

R107

R109

C106C108

R151

J101

1TP102

TP103

1TP104

R146

R147

C138

R144

1P100

R142

1TP106

TP107

R145

R143

1TP108

LTI-SASF546GT-P26-X1

AGND

0.1UF

AGND

AVDD_1P8

VCM_CD_VREF DNI

VIP_D

0.1UF

AVDD_0P9

0.1UF

DNI DNI

AGND

DNI

LTI-SASF546GT-P26-X1

MABA-007159-000000 AGND AGND

2PF

VIP_A

2PF

DNI

0.1UF

FDC

LTI-SASF546GT-P26-X1

0.1UF

2PF

AGNDAGND

2PF

AGND

2PF2PF

AGND

2PF

AGND

2PF

AGND

2PF2PF

AGND

LTI-SASF546GT-P26-X1

DNI

0.1UF

VIN_C

0.1UF 0.1UF

AD9694BCPZ

VCM_AB

AVDD_1P8_PLL

VCM_AB

AGND

AVDD_BUF

AVDD_1P8

VIP_D

VIN_D

DNI

100

VIP_C

2PF

AVDD_1P8_PLL DRVDD_0P9

DVDD_0P9

0.1UF 1UF 1UF

DNI

2PF

0.1UF

AGND

0.1UF

0 10

VIP_B

49.9

DNI

AGND

0.1UF

AGND

VIN_B

0.1UF

AGND

0.1UF

PDWN/STBY

AGND

0.1UF

AVDD_1P8

0.01UF

DNI

DSYNC_CD-

DNI

0.1UF

FDD

AGND

DNI

AGND

DNI

AGND

DNI

AVDD_1P8_SPI

DNIDNI

0.01UF

AVDD_1P8_SPI

VIN_D

2PF

0.1UF

DNI

0.1UF

AGND

LTI-SASF546GT-P26-X1

DNI

MABA-007159-000000

AGND

LTI-SASF546GT-P26-X1

MABA-007159-000000

0.1UF

AGND

LTI-SASF546GT-P26-X1

DNI

49.9

MABA-007159-000000

0.1UF

VIN_A

0.1UF

MABA-007159-000000

AGND AGND

MABA-007159-000000

0.1UF

AGND

0.1UF

AGND

AVDD_BUF

DVDD_0P9

AVDD_1P8

VIP_C

VIN_C

FDA_TO_BUF FDB_TO_BUF

DSYNC_AB-

DRVDD_0P9

DOUT0_CD_N

DSYNC_CD+

AGND

DRVDD_0P9

AVDD_0P9

AGND

VIN_B

AVDD_1P8

AVDD_0P9

VIP_B

AVDD_BUF

AVDD_1P8

AVDD_0P9_SAMPLE_1

MABA-007159-000000

0.1UF

DNI

DSYNC_AB+

D_SYSREF_P

AVDD_0P9_SAMPLE_7

0.1UF

TSW-102-08-G-S

DNI

0.1UF

LTI-SASF546GT-P26-X1

DOUT0_CD_P

DOUT1_CD_N

DOUT1_CD_P

DOUT1_AB_P

DOUT1_AB_N

DOUT0_AB_P

DOUT0_AB_N

AVDD_0P9

AGND

0.1UF 0.1UF

AVDD_BUF

0.1UF 0.1UF

0.1UF

DNI

AGND

0.1UF

AGND

0.1UF

AGND

0.1UF

10K

100

DNI

AVDD_0P9

AGND

AVDD_1P8

AVDD_0P9

AVDD_1P8

AVDD_0P9

D_SYSREF_N

AVDD_1P8

VIP_A

DVDD_0P9

AVDD_1P8_SPI

CSB_DUT

SCLK_DUT

SDIO_DUT

PWDN_TO_BUF

0.1UF

100

AVDD_0P9_SAMPLE_3

DNI

0.1UF

DNI

100

0.1UF

100

0.1UF

DNI

AVDD_0P9_SAMPLE_8

AVDD_0P9_SAMPLE_6

DUT_CLK-

DUT_CLK+

AVDD_0P9_SAMPLE_5

AVDD_0P9_SAMPLE_4

VCM_CD_VREF

0.1UF

AVDD_0P9

DNI

VIN_A

AVDD_BUF

THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.

IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,

OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS

THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS

IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE OR DRAWING NO.

SCALE

SIZE

REV

SHEET

APPROVED

DESCRIPTION

REVISIONS

OL G

OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.

ANV

OF ANALOG DEVICES.

SCHEMATIC

PTD ENGINEER

DESIGN VIEW

REV DATE

SEC PRI

SECPRI

SECPRI SEC PRI

AGND

AGNDAGND

AGND

AGNDAGND

AGND

DRGND

DRVDD1

PAD

AVDD2

AVDD1

AGND_SR

SYSREF-

SYSREF+

AVDD1_SR

AGND_SR

AVDD1

CLK-

CLK+

AVDD1

AVDD2

AVDD3

VIN-C

VIN+C

AVDD2

AVDD3

VIN+D

VIN-D

AVDD2

AVDD1

VCM_CD/VREF

DVDD

DGND

SPIVDD

CSB

SCLK

SDIO

FD_C

FD_D

SYNCINB-CD

SYNCINB+CD

SERDOUTCD0-

SERDOUTCD0+

SERDOUTCD1-

SERDOUTCD1+

SERDOUTAB1+

SERDOUTAB1-

SERDOUTAB0+

SERDOUTAB0-

SYNCINB+AB

SYNCINB-AB

FD_B

FD_A

PDWN

DRVDD2

DGND

DVDD

VCM_AB

AVDD1

AVDD2

VIN-B

VIN+B

AVDD3

AVDD2

VIN+A

VIN-A

AVDD3

SEC PRISECPRI

AD9694 CLOCK INPUTS

PLACE ON BOTTOM OF BOARD

FROM FPGA

DSYNC

FROM FPGA

EEPROM - BOARD ID

PULLUP IS IN FPGA

100 OHM DIFF PAIR

LAYOUT: PLACE 100 OHM R CLOSE TO DUT

KEEP ADJACENT IF POSSIBLE

ENCODE/CLOCK INPUT

100 OHM DIFF PAIR

CLOSE TO SMA

EXTERNAL FPGA REFCLK

EXTERNAL SYSREF TO DUT

2 7

LDO UPREV

AD9694

AD9694 EVALUATION BOARD

NONE

9694CE04

J.HARRIS

R203

T200

5432

1J203

1U201

R202

R206

R214

R220

1TP200

1TP201

C210

R222

R221

R223

1TP202

R224

R225

1TP203

R226R228R230

R227R229R231

R232

R234

R235

R233

R213

R215R217

R216R218

R200

C200

R201

R205

R207

C201

R208

C205

R209

C206

C202

R210

T201

R211

C208

5432

J201

713

PAD

U200

C207R219

C203

C204

5432

J200

R212

DNI

0DSYNC_CD-

0.1UF

DNI DNI DNI

100K 100K100K

BRD_ID_SDA_B

BRD_ID_SCL

M24C02-WMN6TP

ADCLK905

130

3P3_DIG

3.3V_C2M_EEPROM

82.5

0.1UF

49.9

100K100K100K

0.1UF

DNI

DUT_CLK-

100

0.1UF

3P3_FROM_FPGA 3P3_DIG

0.1UF

3P3_DIG

0.1UF

82.5

0.1UF

DUT_CLK+

AGND

DSYNC_TO_DUT_AB+

DSYNC_AB+

DSYNC_AB-

DSYNC_TO_DUT_CD-

DSYNC_TO_DUT_CD+

DSYNC_CD+

100K

100

0.1UF

100

DSYNC_TO_DUT_AB-

130

3P3_DIG

0.1UF

DNI

100K

0EXT_REFCLK_TO_FPGA+

GA0

GA1

0 0

EXT_REFCLK_TO_FPGA-

DNI

YEL

DNI

YEL YEL

DNI

YEL

AGND MABA-007159-000000

10 D_SYSREF_P

MABA-007159-000000

DNI

AGND

D_SYSREF_N

49.9

100

49.9

LTI-SASF546GT-P26-X1

THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.

IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,

OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS

THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS

IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE OR DRAWING NO.

SCALE

SIZE

REV

SHEET

APPROVED

DESCRIPTION

REVISIONS

OL G

OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.

ANV

OF ANALOG DEVICES.

SCHEMATIC

PTD ENGINEER

DESIGN VIEW

REV DATE

SECPRI

-(NC)

VSS

SCL

SDA

WC_N

E0 VCC AGND

AGND

AGNDAGND

AGND

SECPRI

-(NC)

PAD

VREF

Q_N

VCC

VEE

D_N

PIN 68

PIN 71

PIN 69

PIN 58

PIN 56

PIN 59

PIN 45

PIN 10

AD9694 POWER CONNECTIONS

3 7

LDO UPREV

AD9694

AD9694 EVALUATION BOARD

NONE

9694CE04

J.HARRIS

R307

R306

R305

R304

R303

R302

R301

C331

C330

C329

21E314

C328

21E313

21E312

21E315

C327

C326

21E311

21E310

C325

21E309

21E308

C324 R300

P312

P313

P311

P310

P309

P308

P307

P304

1TP300

1TP301

C302

C305

C301

C304

C300

PC303

21E300

21E301

1TP311

1TP309

1TP308

1TP302

C308C307

PC306

1TP303

C311

1TP304

C314

C310

C309

C313

PC312

21E302

21E303

21E304

1TP306

C320C319

C318

1TP307

C323C322

C321

21E306

21E307

P303

P305

AVDD_0P9_SAMPLE_1

AVDD_0P9_SAMPLE_2

AVDD_0P9_SAMPLE_3

AVDD_0P9_SAMPLE_4

AVDD_0P9_SAMPLE_5

AVDD_0P9_SAMPLE_6

AVDD_0P9_SAMPLE_7

AVDD_0P9_SAMPLE_8AVDD_0P9

AVDD_0P9_REG

RED

AVDD_1P8_REG

AVDD_BUF_REG

TSW-102-08-G-S

AVDD_1P8_PLL_IN

DRVDD_0P9_IN

DVDD_0P9_IN

AVDD_1P8_SPI_IN

DNI

AVDD_BUF_IN

DNI

AVDD_1P8_IN

DNI

TSW-102-08-G-S

10UF

AVDD_0P9_IN

10UF

50OHMS

DVDD_0P9_REG

TSW-102-08-G-S

0.1UF

TSW-106-14-T-D

50OHMS

0.1UF

AVDD_SPI_REG

50OHMS

TSW-106-14-T-D

10UF

0.1UF10UF

50OHMS

10UF

TSW-102-08-G-S

TSW-106-14-T-D

AVDD_0P9

10UF

AGND

AVDD_0P9

AGND

0.1UF

AGND

AVDD_0P9

AGND

AVDD_0P9

AGND

DRVDD_0P9_REG

TSW-102-08-G-S

AVDD_PLL_REG

AVDD_0P9

AVDD_BUF

DVDD_0P9

AVDD_1P8_SPI

50OHMS

0.1UF

AVDD_0P9

AVDD_1P8

0.1UF

DRVDD_0P9

AVDD_1P8_PLL

0.1UF

TSW-102-08-G-S

100UF

BLK BLK BLK

THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.

IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,

OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS

THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS

IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE OR DRAWING NO.

SCALE

SIZE

REV

SHEET

APPROVED

DESCRIPTION

REVISIONS

OL G

OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.

ANV

OF ANALOG DEVICES.

SCHEMATIC

PTD ENGINEER

DESIGN VIEW

REV DATE

AGND

FROM BNX024H01 D.S.

12V 1A FROM FMC

SUPPLY REGULATORS

AD9694 POWER SUPPLY CIRCUITRY

OUTPUTS

3.0V OUT FOR 2.5V ANALOG

6VDC, 2A MAX

USE RECOMMENDED PCB

1.3V OUT FOR AVDD1

ERROR AMPLIFIER OUTPUTS

ERJ-2RKF7680X

600KHZ

USE 15.1K FOR 1.2MHZ

1.3V OUT FOR DIGITAL 2.4V OUT FOR 1.8V ANALOG AND PLL

SWITCHING MOSFETS

PIN30

4 7

LDO UPREV

AD9694

AD9694 EVALUATION BOARD

NONE

9694CE04

J.HARRIS

R428

R415

R425

R426

TP409

TP408

R403

R405

R406

R401

R402

R409

R407

R408

R424

R404

C403

L400

C404

C428

C429

PAD

U400

C420

TP405

TP404

TP407

TP406

5 6 Q400

C415

R414

C414

R413

C413

R412

C424C423C422

L406

R420

R421

C412

TP401

TP400

C427C426C425

L407

R422

R423

TP403

TP402

7 8 Q400

C418C417C416

L404

R416

R417

C421C419

L405

R418

R419

1P401

1F401

21 FL400

1F400

P400

CCR401

R400

C407

R410

C408

CCR400

C402

C409

C410

C411

R411

LTST-C193KGKT-5A

VREG_ADP5054

DNI

EN 0

VREG_ADP5054

DNI

ENPG_C2M 0

DNI

VREG_ADP5054 0

0.0027UF

BST1

0.1UF

BST2

BST3

0.1UF

BST4

0.1UF

47K SI7232DN-T1-GE3

DNI

DL1

22UF

6.8UH

23.2K

46.4K

23.2K

14.3K

22UF

SW3

COMP3

1UF

SW1

COMP1

VREG_ADP5054

10UF

31.6K

AGND

2.0K

C2M_12P0V

1.5UH

14.3K

23.2K

22UF22UF22UF

22UF

3V0_AVDD

SW4

FB1

0.012UF0.012UF

4.53K619619

22UF22UF22UF

BST4

FB3

DL2

BST2

FB1

DL1

BST1

PWR_IN

VDD_ADP5054

0.47UH

47K

DNI

COMP2

PWR_IN

FB4

1UF

S2A-TP

10K

COMP3

COMP4

SW1

SW2

COMP2

COMP4

22-10-2031

C2M_12P0V

PGND

SW2 1.5UH

DL2

SI7232DN-T1-GE3

SW1

SW4

FB3

FB4FB2

1V3_AVDD1

1V3_DVDD

COMP1

1.43K

2V4_AVDD

22UF

SW3 10UH

BNX024H01

6V_IN

PJ-002AH-SMT

64.9K 22UF 22UF

FB2

BST3

ADP5054ACPZ

10UF

25V

10UF

25V

10UF

0.1UF

0.0082UF

THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.

IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,

OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS

THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS

IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE OR DRAWING NO.

SCALE

SIZE

REV

SHEET

APPROVED

DESCRIPTION

REVISIONS

OL G

OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.

ANV

OF ANALOG DEVICES.

SCHEMATIC

PTD ENGINEER

DESIGN VIEW

REV DATE

EN3 COMP3

FB3

VREG

SYNC/MODE

VDD

FB1

COMP1

EN1

PVIN1 SW1

BST1

DL1

PGND

DL2

BST2

SW2PVIN2

EN2 COMP2

FB2

CFG12

PWRGDFB4 COMP4

EN4

CFG34

BST4

PGND4

SW4

PVIN4

PVIN3 SW3

PGND3

BST3

AGND

AGNDAGNDAGNDAGND

AGND

AGND AGND

AGNDAGND

AGND

AVDD1 0.95V

DRVDD 1.8V

AVDD2 1.8V

DRVDD 1.8V

AVDD3 2.5V

DRVDD 0.95V

DVDD 0.95V

AD9694 POWER SUPPLY CIRCUITRY - LDOS

5 7

LDO UPREV

AD9694

AD9694 EVALUATION BOARD

NONE

9694CE04

J.HARRIS

R517

R516

L501

R504

L500

PAD

U505

PAD

U504

C549 C548

21E519

5 2

PAD

U506

R514

C546

21E518

C547

C515C514C513

21E504

C512

C544

R506C545C511

C516

21E506

C533

21E503

C543C538

C510

C509C508C507

21E502

C550

C541

C542

R502C506C505

C540

21E501

C536

C504

C539

C535

C534

21E507

PAD

C523C522

21E509

C521

PAD

R508

21E508

C517

C530C529

21E511

C528

C532

R509

C520C519C518

21E510

C524

R511

R510

C527C526C525

21E512

PAD52 3

U503

C531

DNI

1UF

ADP7159ACPZ

40.2K

22.1K

10UF10UF

10UF

ADP7159ACPZ

120OHM1000PF 120OHM

DNI

1000PF

22UF

120OHM

ADP151ACPZ-1.8

DVDD_0P9_REG

22UF

120OHM 120OHM

AVDD_0P9_REG

2V4_AVDD

1UF

AVDD_1P8_REG

1UH

DNI

10UF

4.7UF

ADP7118ACPZN-1.8

ADP1762

22UF

AVDD_BUF_REG

10UF

PWR_IN AVDD_SPI_REG

4.7UF

25V

0.001UF

4.7UF

AVDD_PLL_REG

10UF

2V4_AVDD

120OHM

10UF

3V0_AVDD

10UF

1UF 1UF

120OHM 10UF 120OHM

10UF

1UF

10UF

1UF

22UF

120OHM

10UF

1UF

1V3_AVDD1

1UH

DNI

22UF

6.34K

10UF

1V3_DVDD

10UF

1UF

22UF

120OHM

6.34K

120OHM

22UF

10UF

120OHM

10UF

120OHM 10UF

DRVDD_0P9_REG

22UF

10UF

22.1K

THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.

IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,

OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS

THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS

IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE OR DRAWING NO.

SCALE

SIZE

REV

SHEET

APPROVED

DESCRIPTION

REVISIONS

OL G

OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.

ANV

OF ANALOG DEVICES.

SCHEMATIC

PTD ENGINEER

DESIGN VIEW

REV DATE

VIN

VIN VOUT

VOUT

VREG

REF

REF_SENSE

BYP

VOUT_SENSE

AGND

VIN

VIN VOUT

VOUT

VREG

REF

REF_SENSE

BYP

VOUT_SENSE

AGND

PAD

VIN

EN GNDNC

VOUT

AGND

AGND AGND

AGND

PAD

SENSE

VOUT

ADJ

GND

VREG

REFCAP

VIN

PAD

SENSE

VOUT

ADJ

GND

VREG

REFCAP

VIN

PAD

VIN

EN GND

SENSE/ADJ

VOUT

AGND

AD9694 SPI/BUFFER CIRCUIT

6 7

LDO UPREV

AD9694

AD9694 EVALUATION BOARD

NONE

9694CE04

J.HARRIS

R612

R608

R609

R610

R611

C601

1P601

C600

U600R603

R602

P600

1P603

C603C602

U601

P602

R601

R605

R607

R600

R604

R606

DNI 10K

DNI

10K

DNI

SDIO_DUT

SCLK_DUT

CSB_DUT

TSW-104-08-G-S

AVDD_1P8_SPI

FXLA104UM12X

TSW-104-08-G-S

0.1UF 0.1UF

DNI

CSB_FPGA_TO_DUT

FDA_TO_FPGA

AVDD_1P8_SPI

0.1UF0.1UF

FDA_TO_BUF

DNI

SCLK_FROM_FPGA

SDO_TO_FPGA

DNI

SDI_FROM_FPGA

AVDD_1P8_SPI

DNI

100K

PWDN_TO_BUF

TSW-104-08-G-S

AVDD_1P8_SPI

VADJ

FDB_TO_BUF

DNI

PWDN_TO_FPGA

FDB_TO_FPGA

VADJ VADJ

DNI

100K

TSW-104-08-G-S

DNI

100K

THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.

IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,

OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS

THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS

IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE OR DRAWING NO.

SCALE

SIZE

REV

SHEET

APPROVED

DESCRIPTION

REVISIONS

OL G

OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.

ANV

OF ANALOG DEVICES.

SCHEMATIC

PTD ENGINEER

DESIGN VIEW

REV DATE

OE_N

GND

VCCA VCCB

AGND

AGNDAGND

AGND

AGNDAGND

AGND

OE_N

GND

VCCA VCCB

HA04_P

VREF_A_M2C

PRSNT_M2C_L

CLK0_M2C_P

LA02_N

LA04_P

LA04_N

DP7_M2C_N

DP7_M2C_P

DP8_M2C_N

DP3_M2C_P

GBTCLK1_M2C_P

DP9_M2C_N

DP9_M2C_P

DP0_C2M_P

DP0_C2M_N

LA09_P

LA09_N

LA14_P

LA14_N

DP6_M2C_N

DP6_M2C_P

VIO_B_M2C

LA01_P_CC

LA01_N_CC

LA13_P

HA20_N

AD9694 ADS7 FMC CONNECTIONS

GBTCLK0_M2C_P

DP0_M2C_P

GBTCLK0_M2C_N

HA01_N_CC

HA05_P

PG_C2M

HA16_N

HA16_P

HA13_N

HA13_P

HA01_P_CC

LA17_P_CC

LA17_N_CC

LA10_P

LA26_P

LA27_N

RES0

LA00_N_CC

CLK2_BIDIR_P

CLK2_BIDIR_N

HA23_P

HB10_N

HB14_P

HB14_N

HB17_P_CC HB18_N

VADJ

HB12_N

HB12_P

LA15_P

HB10_P

VIO_B_M2C

HB17_N_CC

HA23_N

HA21_N

HA21_P

HA10_N

HA10_P

HA02_N

HA06_P

HA06_N

HB06_P_CC

HB00_N_CC

HA17_P_CC

HA17_N_CC

HA02_P

VREF_B_M2C

HB15_N

HB18_P

HB15_P

HB07_N

HB11_P

HB11_N

LA32_P

LA28_N

LA30_N

LA32_N

LA30_P

LA24_P

LA24_N

LA28_P

LA33_N

LA31_N

LA33_P

LA31_P

LA25_N

LA29_P

LA29_N

HB07_P

HB01_N

HA22_N

HA18_P

HA14_N

HA03_P

HA03_N LA02_P

LA07_N

LA11_P

LA21_N

LA21_P

LA19_N

LA19_P

LA11_N

CLK0_M2C_N

LA07_P

LA25_P

LA22_P

LA22_N

LA20_P

LA16_P

LA20_N

LA12_N

LA12_P

LA08_N

LA08_P

LA03_P

CLK1_M2C_P

CLK1_M2C_N

VADJ

HB20_N

HB16_N

HB20_P

HB16_P

HB08_P

HB08_N

VADJ

HB21_N

HB21_P

HB19_N

HB19_P

HB09_N

HB13_P

HB13_N

HB02_N

HB04_P

HB04_N

HA19_N

HA19_P

HB02_P

HA15_N

HA12_P

HA15_P

HA12_N

HA08_N

HA04_N

PG_M2C

HB05_P

HB05_N

HB03_N

HB03_P

HB09_P

HA05_N

3P3V

GA1

3P3V

TMS

TDI

TCK

TDO

3P3VAUX

TRST_L

12POV

GA0

12P0V

SCL

SDA

DP8_C2M_P

DP8_C2M_N

DP7_C2M_P

DP7_C2M_N

DP6_C2M_P

DP6_C2M_N

LA26_N

LA23_P

LA23_N

LA13_N

LA05_N

LA05_P

LA27_P

LA10_N

LA06_N

LA06_P

DP0_M2C_N

LA18_N_CC

LA18_P_CC

DP9_C2M_P

DP9_C2M_N

DP8_M2C_P

CLK_DIR

GBTCLK1_M2C_N

DP4_C2M_P

DP5_C2M_P

DP4_C2M_N

DP3_C2M_P

DP3_C2M_N

DP5_C2M_N

DP4_M2C_N

DP5_M2C_P

DP5_M2C_N

DP1_C2M_N

DP1_C2M_P

DP4_M2C_P

DP3_M2C_N

DP2_C2M_P

DP2_C2M_N

DP2_M2C_P

DP2_M2C_N

DP1_M2C_N

DP1_M2C_P

OUTSIDE OF SOCKET

PLACE AS CLOSE TO DUT AS POSSIBLE

HA20_P

HB00_P_CC

3P3V

LA15_N

HA07_N

HA07_P

HA11_N

HA11_P

CLK3_BIDIR_P

CLK3_BIDIR_N

HA18_N

HA22_P

HB01_P

HB06_N_CC

HA14_P

HA09_NHA08_P

LA00_P_CC

LA03_N

HA09_P

LA16_N

HA00_N_CC

HA00_P_CC

7 7

LDO UPREV

AD9694

AD9694 EVALUATION BOARD

NONE

9694CE04

J.HARRIS

R703

A40

A39

A38

A37

A36

A35

A34

A33

A32

A31

A30

A29

A28

A27

A26

A25

A24

A23

A22

A21

A20

A19

A18

A17

A16

A15

A14

A13

A12

A11

A10

A1 P700

1TP703

R702

B40

B39

B38

B37

B36

B35

B34

B33

B32

B31

B30

B29

B28

B27

B26

B25

B24

B23

B22

B21

B20

B19

B18

B17

B16

B15

B14

B13

B12

B11

B10

B1 P700

C40

C39

C38

C37

C36

C35

C34

C33

C32

C31

C30

C29

C28

C27

C26

C25

C24

C23

C22

C21

C20

C19

C18

C17

C16

C15

C14

C13

C12

C11

C10

C1 P700

1TP701

C700

R701

D40

D39

D38

D37

D36

D35

D34

D33

D32

D31

D30

D29

D28

D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

D15

D14

D13

D12

D11

D10

D1 P700

1TP702

E40

E39

E38

E37

E36

E35

E34

E33

E32

E31

E30

E29

E28

E27

E26

E25

E24

E23

E22

E21

E20

E19

E18

E17

E16

E15

E14

E13

E12

E11

E10

E1 P700

F40

F39

F38

F37

F36

F35

F34

F33

F32

F31

F30

F29

F28

F27

F26

F25

F24

F23

F22

F21

F20

F19

F18

F17

F16

F15

F14

F13

F12

F11

F10

F1 P700

C702

C704

C706

C701

C703

C705

C708

G40

G39

G38

G37

G36

G35

G34

G33

G32

G31

G30

G29

G28

G27

G26

G25

G24

G23

G22

G21

G20

G19

G18

G17

G16

G15

G14

G13

G12

G11

G10

G1 P700

H40

H39

H38

H37

H36

H35

H34

H33

H32

H31

H30

H29

H28

H27

H26

H25

H24

H23

H22

H21

H20

H19

H18

H17

H16

H15

H14

H13

H12

H11

H10

H1 P700

1TP700

R800

C707

J40

J39

J38

J37

J36

J35

J34

J33

J32

J31

J30

J29

J28

J27

J26

J25

J24

J23

J22

J21

J20

J19

J18

J17

J16

J15

J14

J13

J12

J11

J10

J1 P700

K40

K39

K38

K37

K36

K35

K34

K33

K32

K31

K30

K29

K28

K27

K26

K25

K24

K23

K22

K21

K20

K19

K18

K17

K16

K15

K14

K13

K12

K11

K10

K1 P700 WHT

WHT

10K

DNI

PG_C2M

DNI

10K

DNI

10K

DOUT1_CD_N

DOUT_2+

DOUT_2-

SCLK_FROM_FPGA

DNI

ASP-134488-01

0.1UF

ASP-134488-01

0.1UF

ASP-134488-01ASP-134488-01

DOUT_3-

DOUT_3+

DOUT_0+

DOUT_0-

DOUT_1+

BRD_ID_SCL

GA0

BRD_ID_SDA_B

C2M_12P0V

3P3_FROM_FPGA

3.3V_C2M_EEPROM

TDO_TDI

GA1

DOUT_1-

DOUT_0+

DOUT_2+

FDA_TO_FPGA

FDB_TO_FPGA

DOUT_3-

VADJ

0.1UF

ASP-134488-01 ASP-134488-01

DOUT_0-

0.1UF

DOUT_1+

DOUT_3+

ASP-134488-01 ASP-134488-01

DOUT0_AB_P

DOUT0_AB_N

0.1UF

DOUT1_AB_P

DOUT1_AB_N

DOUT1_CD_P

DOUT0_CD_P

DOUT_1-

0.1UF

DOUT_2-

SDO_TO_FPGA

PWDN_TO_FPGA

DSYNC_TO_DUT_CD+

DSYNC_TO_DUT_CD-

DSYNC_TO_DUT_AB+

DSYNC_TO_DUT_AB-

CSB_FPGA_TO_DUT

DOUT0_CD_N

ASP-134488-01

SDI_FROM_FPGA

0.1UF

EXT_REFCLK_TO_FPGA-

EXT_REFCLK_TO_FPGA+

3P3_DIG

THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.

IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,

OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS

THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS

IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE OR DRAWING NO.

SCALE

SIZE

REV

SHEET

APPROVED

DESCRIPTION

REVISIONS

OL G

OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.

ANV

OF ANALOG DEVICES.

SCHEMATIC

PTD ENGINEER

DESIGN VIEW

REV DATE

AGNDAGNDAGNDAGNDAGNDAGNDAGNDAGNDAGNDAGND

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