Alinx AC7010C Manuel utilisateur

ZYNQ7000 FPGA

Core Board

AC7010C/AC7020C

User Manual

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Version Record

Revision

Date

Release By

Description

Rev 1.0

2022-09-07

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Table of Contents

Version Record .............................................................................................2

Part 1: Introduction ....................................................................................... 5

Part 2: Dimensional structure .......................................................................8

Part 3: Power Supply ....................................................................................8

Part 4: ZYNQ Chip ......................................................................................10

Part 4.1: JTAG Interface ..................................................................... 13

Part 4.2: FPGA Power System ........................................................... 14

Part 4.3: ZYNQ boot configuration ..................................................... 15

Part 5: Clock Configuration ........................................................................ 15

Part 5.1: PS system clock source .......................................................15

Part 5.2: PL system clock source ....................................................... 16

Part 6：ZYNQ Processor System (PS) peripherals ..................................16

Part 6.1: QSPI Flash ........................................................................... 17

Part 6.2: DDR3 DRAM ........................................................................ 18

Part 6.3: Gigabit Ethernet Interface ....................................................23

Part 6.4: USB2.0 Interface ..................................................................25

Part 6.5: USB to Serial Port ................................................................ 27

Part 6.6: SD Card Slot ........................................................................ 28

Part 6.7: User LEDs ............................................................................ 29

Part 6.8: Reset Key .............................................................................30

Part 7：ZYNQ PL Peripherals ................................................................... 31

Part 7.1: User LEDs ............................................................................ 31

Part 7.2: Expansion Port J10 ..............................................................32

Part 7.3: Expansion Port J11 .............................................................. 34

Part 7.4: Expansion Port J12 ..............................................................37

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The two core boards of the ALINX XILINX ZYNQ7000 development

platform were officially released in 2022, models: AC7010C and AC7020C

(industrial grade). Their development platform is the solution for XILINX's

Zynq7000 SOC chip. It uses ARM+FPGA SOC technology to integrate

dual-core ARM Cortex-A9 and FPGA programmable logic on a single chip. The

AC7010C core board uses Xilinx's Zynq7000 series XC7Z010-1CLG400C as

the core processor, and the AC7020C core board uses the industrial grade

XC7Z020-2CLG400I chip. Extensive peripheral interfaces such as Gigabit

Ethernet, USB2.0, serial port, SD card, etc. are extended on the ARM side. In

addition, the core board expands a large number of IOs to the outer three

connectors, including 94 IO ports of the PL (47 pairs of LVDS differential) and 8

MIO ports of the PS. For users who need a lot of IO, this core board will be a

good choice, and it is also very suitable for secondary development.

The design of the core board adheres to the design concept of “exquisite,

practical and concise”. It is not only suitable for the software verification of the

software staff, but also suitable for the hardware design of hardware

developers, that is, the system cooperation of software and hardware, and

accelerated the development process of the project.

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Part 1: Introduction

Here, a brief introduction to the ZYNQ7000 core board

AC7010C/AC7020C is provided.

The core board uses Xilinx's Zynq7000 series of chips, the AC7010C uses

the Zynq7000's XC7Z010-1CLG400C chip, and the AC7020C uses the

Zynq7000's XC7Z020-2CLG400I chip, both of which are 400-pin FBGA

packages. The ZYNQ7000 chip can be divided into a processor system part

processor system (PS) and a programmable logic part Programmable Logic

(PL).

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On the AC7010C/AC7020C core board, the PS part of the ZYNQ7000 is

equipped with a wealth of external interfaces and devices for user convenience

and function verification. The IO ports on the PL side are all led to the 2.54mm

connector on the board for user expansion. In addition, there is a 7 x 2 JTAG

connector on the core board that can be downloaded and debugged via the

ALINX Xilinx USB Cable Downloader. Figure 1-2 shows the structure of the

entire AC7010C/AC7020C system:

Figure 1-1: The Schematic Diagram of the AC7010C/AC7020C

Through this diagram, you can see the interfaces and functions that the

AC7010C/AC7020C FPGA Core Board contains:

DC5V power input, maximum current does not exceed 500mA

Xilinx ARM+FPGA chip Zynq-7000 XC7Z010-1CLG400C for AC7010C,

Zynq-7000 XC7Z020-2CLG400I for AC7020C

DDR3

Two large-capacity 2Gbit (A total of 4Gbit) high-speed DDR3 SDRAMs

can be used as a cache for ZYNQ chip data or as a memory for the

operating system

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QSPI FLASH

A 256Mbit QSPI FLASH memory chip can be used as a Uboot file for

ZYNQ chips, storage of system files and user data;

Gigabit Ethernet Interface

1-channel 10/100M/1000M Ethernet RJ45 interface for Ethernet data

exchange with computers or other network devices.

USB2.0 HOST Interface

1-channel USB HOST interface, to connect with external USB slave

devices, such as connecting a mouse, keyboard, USB flash drive etc.

The USB interface uses a flat USB interface (USB Type A).

USB OTG Interface

1-channel high-speed USB2.0 OTG interface for OTG communication

with PC or USB devices

USB Uart Interface

1-channel USB Uart interface for serial communication with PC or

external devices

LED Light

2 LEDs, 1 PS control LED, 1 PL control LED.

Key

1 reset button for CPU reset

Clock

An on-board 33.333Mhz active crystal oscillator provides a stable clock

source for the PS system, a 50MHz active crystal oscillator that

provides additional clocking for the PL logic

3-way 40-pin expansion port (0.1inch Spacing)

3-way 40-pin 0.1inch spacing expansion port for extending the IOs of

ZYNQ PL and PL parts, and can be connect to various ALINX modules

(binocular camera, TFT LCD screen, high-speed AD module, etc.)

14-pin JTAG Interface (0.08inch Spacing)

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Used to debug and download the ZYNQ system

Micro SD card holder

1-channel Micro SD card holder, to insert SD card for stores operating

system images and file systems.

Part 2: Dimensional structure

The size of the development board is 2.95 inch x 2.52 inch, and the PCB is

designed with an 8-layer board. There are 4 screw positioning holes around the

board for fixing the development board. The holes diameter of the positioning

hole is 0.09 inch, and the dxf structure diagram is provided in the documents.

Figure 2-1: FPGA Size Dimension

Part 3: Power Supply

The power input voltage of the development board is DC5V, The

schematic diagram of the power supply design on the AX7010 FPGA

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development board is shown in Figure 3-1

Power input: The core board supply voltage is DC5V. When the core board

works alone, connect the USB cable to the USB port of the computer to supply

power to the core board. When working with carrier board together, the core

board can also be powered through the carrier board. If the

AC7010C/AC7020C core board is powered by the carrier board, remove the

0Ω resistor (R161) on the board. Please do not use other specifications of the

power supply to avoid damage to the core board. The power supply design on

the core board is as follows:

Figure 3-1: Power Supply Schematic

The development board is powered by +5V, and is converted into +1.5V,

+1.8V, +1.0V three-way power supply through three DC/DC power supply chip

TLV62130RGT. Each output current can be up to 3A. The 3.3V, VCCIO34 and

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VCCI35 power supplies are generated by the three LDOs “SPX3819M5-3-3”,

the VCCIO34 is powered by the BANK34 of ZYNQ, and the VCCIO35 is

and BANK35IO adapts to different voltage standards. +1.5V Generates VTT

and VREF voltages required by DDR3 via TI's TPS51200

The functions of each power distribution are shown in the following table

below:

Power Supply

Function

+1.0V

ZYNQ Core Voltage

+1.5V

DDR3, ZYNQ Bank502

+1.8V

ZYNQ auxiliary voltage, ZYNQ PLL, ZYNQ BANK501, VCCIO,

Ethernet, USB 2.0

+3.3V

ZYNQ VCCIO, Gigabit Ethernet, Serial Port, HDMI, RTC,

FLASH,EEPROM SD Card

VREF, VTT

DDR3

VCCIO34

ZYNQ Bank34

VCCIO35

ZYNQ Bank35

Because the power supply of the PS and PL parts of ZYNQ has the

power-on sequence requirements, in the circuit design, we have designed

according to the power requirements of ZYQN. The power-on sequence is

+1.0V->+1.8V->+1.5 V-> (3.3V, VCCIO34, VCCIO35). Figure 3-2 shows the

circuit design of the power supply:

In the PCB design, an 8-layer PCB is used, and a separate power supply

layer and GND layer are reserved, so that the power supply of the entire

development board has very good stability.

Part 4: ZYNQ Chip

The Core development board uses Xilinx's Zynq7000 series chip,

AC7010C chip model is XC7Z010-1CLG400C (AC7020C chip model is

XC7Z020-2CLG400I). The chip's PS system integrates two ARM CortexTM-A9

processors, AMBA® interconnects, internal memory, external memory

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