Alinx AX301 Manuel utilisateur

ALINX FPGA BOARD

AX301

User Manual

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AX301 User Manual

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Revsion History

Revision

Description

1.0

First Release

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AX301 User Manual

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Development Environment:

Quartus 17.1 is from Xilinx website

https://www.altera.com

Official website:

Http://www.alinx.com.cn

E-mail:

[email protected]

Tel:

+86-021-67676997

WeChat public number：

ALINX-HEIJIN

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AX301 User Manual

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Contents

1. Overview.........................................................................................................................................5

2. Power..............................................................................................................................................6

3. FPGA..............................................................................................................................................7

3.1 JTAG..........................................................................................................................................8

3.2 Power and GND.........................................................................................................................8

4. 50M Crystal ....................................................................................................................................9

5. SPI Flash.......................................................................................................................................10

6. SDRAM........................................................................................................................................11

7. EEPROM......................................................................................................................................12

8. RTC...............................................................................................................................................13

9. USB TO UART.............................................................................................................................14

10. VGA PORT...................................................................................................................................15

11. SD CARD SLOT..........................................................................................................................17

12. LED...............................................................................................................................................17

13. KEY..............................................................................................................................................18

14. CAMERA PORT...........................................................................................................................19

15. Digital Tube ..................................................................................................................................19

16. BUZZER.......................................................................................................................................21

17. Expansion port..............................................................................................................................22

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This development board is an entry-level product of ALTERA FPGA, mainly for FPGA

beginners, model EP4CE6F17C8, is a 256-pin FBGA package. The development of the

entire development board is practical, there are two 40-pin 2.54 standard expansion port, a

total of 68 IO, in addition to retain the 5V power supply, 3.3V power supply, there are

multiple GND, for the likes of DIY players, is a very Good choice. In addition, many

supporting modules can also be directly connected to the expansion port of this FPGA

development board, such as ADDA module, 4.3’TFT screen, audio modules, cameras, etc.,

to provide players with more choices for learning. Here we will make a detailed introduction

to this development board.

1. Overview

Here is a brief introduction to this FPGA development platform. This development board

uses ALTERA's Cyclone IV series FPGA, model EP4CE6F17C8, 256-pin FBGA package.

The resources of this FPGAare shown in Table 1-1:

parameter

value

Logic elements(LEs)

6272

Embedded memory(Kbits)

270

Embedded 18x18multipliers

PLLs

Global Clock Networks

Kernel voltage

1.2V

Work temperature

0-85℃

Table 1-1

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The structure of the entire system is shown in Figure 1-1.

FPGA

EP4CE6

256Mbit

SDRAM

50M

晶振 EEPROM

24LC04

实时时钟

蜂鸣器

CP2102

复位键按键1按键2按键3

Micro

SD卡座

VGA接口

JTAG口摄像头

接口

40针扩展口（34个IO口，1路5V，2路3.3V，3路GND

电源

开关

USB供电接

口及串口

电池座

6位数码管 4个用户LED灯

2路电源转换芯片

16Mbit

FLASH

40针扩展口（34个IO口，1路5V，2路3.3V，3路GND

Figure 1-1

Through this diagram, we can see the functions that this development platform can achieve.

- USB interface power supply, while USB to serial port function.

- 1 large-capacity 256Mbit SDRAM, which can be used as data cache.

- 1 16Mbit SPI FLASH that can be used to store FPGAconfiguration files and user data;

- 1 camera interface, can connect OV5640 camera.

- 1 VGA port, 16-bit VGA port, can display 65536 colors, can display color pictures and

other information.

- 1 RTC real-time clock with battery holder, battery model CR1220.

- 1 piece IIC interface EEPROM 24LC04.

- 4 red LEDs for water flow function.

- 4 buttons, a reset button, 3 user buttons.

- 50M crystal oscillator to provide a stable clock source to the development board.

- Two 40-pin black gold standard AX expansion ports (2.54mm pitch), of which 34 IO ports,

1 5V power supply, 2 3.3V power supplies, 3 GND. Two expansion modules can be

connected at the same time, such as 4.3-inch TFT module andAD/DA module.

- The JTAG port is reserved for debugging and solidifying the FPGA.

- 1 Micro SD slot with SPI mode support.

- A 6-bit digital tube, 6-digit dynamic display.

2. Power

The AX301 development board is powered by USB, and the MINI USB cable is used to

connect the development board with the USB of the computer. Pressing the power switch

will not only supply power to the development board. The power supply design Figure 2-1

on the development board is as follows:

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USB POWER

PORT

FUSE

AMS1117-

3.3

AMS1117-

1.2V

3.3V

1.2V

SWITCH

SW1

AMS1117-

2.5

2.5V

Figure 2-1

The development board is powered by USB and generates three power supplies of +3.3V,

+2.5V, and +1.2V through the 3 LDO power chip, respectively, to meet the BANK voltage

and core voltage of the FPGA.

When designing the PCB, we use a 4-layer PCB, leaving an independent GND plane,

which allows the entire development board to have a complete ground plane, ensuring that

the development board has very good stability. On the PCB, we set aside test points for

each power supply so that the user can confirm the voltage on the board.

3. FPGA

The FPGA model is EP4CE6F17C8, which belongs to ALTERA Cyclone IV. This model is

BGA package, 256 pins. The pin names are in the form of letter + number, such as E3, G3,

etc. When we look at the schematic, we see the letter + number in this form, which

represents the pins of the FPGA. Figure 3-1 shows the FPGA chip physical map used for

the development board.

Figure 3-1

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3.1 JTAG

First of all ,we talk about FPGA configuration and debugging interface: JTAG interface.

The function of the JTAG interface is to download the compiled program (.sof) to the

FPGA or download the FLASH configuration program (.jic) to the SPI FLASH.After the

sof file is downloaded to the FPGA, it will be lost after power-off ,so we need to download

it again after the power-on. At this time, we can use the Quartus software to convert the sof

file into a jic file.After downloading the jic file to the development board's FLASH via

JTAG, it will not be lost after power-off. After the power-on, the FPGA will read the jic

configuration file in the FLASH and run.

Figure 3-2 shows the schematic part of the JTAG port, which involves the four signals

TCK, TDO, TMS, and TDI. These four signals are directly derived from the FPGA pins.

Each signal has a diode overvoltage protection circuit on the development board.

Figure 3-2

3.2 Power and GND

The power supply pin portion of the FPGAincludes each bank's power pin, core voltage pin,

analog voltage, and phase-locked loop power supply pin. VCCINT is the FPGA core power

supply pin, which is connected to 1.2V; VCCIO is for each BANK of the FPGA. Power

supply voltage, where VCCIO0 is the power supply pin of the BANK0 of the FPGA.

Similarly, VCCIO1~VCCIO3 are power supply pins of the BANK~BANK3 of the FPGA

respectively. In the development board, VCCIO is connected to 3.3V voltage, that is to say,

this The development board FPGA pins are 3.3V inputs and outputs. VCCA is the FPGA

analog supply pin, followed by 2.5V, VCCD_PLL is the FPGAPLL power supply pin, also

connected to 1.2V, FPGA power supply connection diagram shown in Figure 3-3.

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Figure 3-3

In addition, there are many pins in the FPGA that need to be connected to GND to ensure a

stable reference ground within the FPGA. The GND connected to the FPGA is shown in

Figure 3-4.

Figure 3-4

4. 50M Crystal

Figure 4-1 is the 50M active crystal circuit that we mentioned above to provide the clock

source for the development board. The crystal oscillator output is connected to the FPGA's

global input clock pin (CLK1 pin E1). This CLK1 can be used to drive the user logic within

the FPGA. The user can configure the FPGA's internal PLL (phase-locked loop) to achieve

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frequency division and frequency multiplication. Other frequency clocks.

Figure 4-1

Clock pin assignment:

Signal Name

CLK

5. SPI Flash

The development board uses a 16Mbit-sized SPI FLASH chip, M25P16, which uses the

3.3V CMOS voltage standard and completely replaces the ALTERA configuration chip

EPCS16. Because of its non-volatile nature, SPI FLASH can be used as the boot image of

an FPGA system. These images mainly include FPGA JIC configuration files, soft core

application code, and other user data files.

SPI FLASH specific models and related parameters are shown in Table 5-1。

Position

Model

Capacity

Factory

M25P16

16M bit

Table 5-1

The SPI Flash schematic is shown in Figure 5-1.

Figure 5-1

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