Alinx ALTERA AC4040 Manuel utilisateur

ALINX ALTER Core Board

AC4040

User Manual

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Version Record

Version

Date

Release By

Description

Rev 1.0

2020-11-18

Rachel Zhou

First Release

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Table of Contents

Version Record.......................................................................................................2

Part 1: AC4040 Core Board Introduction...........................................................4

Part 2: DDR2 DRAM............................................................................................. 5

Part 3: SPI Flash....................................................................................................8

Part 4: FPGA Power Supply................................................................................ 9

Part 5: Expansion Ports......................................................................................12

Part 6: Power interface on Core Board........................................................... 14

Part 7: Crystal oscillator on Core Board..........................................................15

Part 8: LED Light on Core Board......................................................................17

Part 9: Structure Diagram.................................................................................. 19

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Part 1: AC4040 Core Board Introduction

FPGA+ 2DDR2 core board is based on ALTERA CYCLONE IV series

EP4CE40F23C8. This chip develops a high-performance core board with high

speed, high bandwidth and high capacity. It is suitable for video image

processing and high-speed data acquisition.

This core board uses two pieces of MICRON's MT47H64M16HR-3IT

DDR2 chip with a total capacity of 2Gbit; two DDR2s form a 32-bit bus mode,

and the read/write data bandwidth between FPGA and DDR2 is up to 8.5Gb;

this configuration can satisfy 4 channels of 1080p video processing needs.

This core board extends 168 IO ports (73 pairs of LVDS differential), which

is a good choice for users who need a lot of IO. Moreover, the FPGA chip to the

interface is treated with the same length, and the core board size is only 60*60

(mm), which is very suitable for secondary development.

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Part 2: DDR2 DRAM

Figure 2-1 detailed part of the DDR2 schematic (For details, please refer to

the schematic provided by us.)

Figure 2-1: DDR2 schematic

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Further, in order to allow DDR2 work properly, it is necessary to provide a

reference voltage VREF and the termination voltage VTT is DDR2 DDR2 chip

address lines and control lines, and VTT voltage VREF are 0.9V. Figure 3-2-1

detailed the power supply schematic below:

Figure 2-2: DDR2 Power for VTT/VREF

Figure 2-3: DDR2 Power Circuit on the Core Board

DDR2 connected to the BANK3 and BANK4 of the FPGA.

DDR2 Pin Assignment

Pin Name

FPGA Pin

Pin Name

FPGA Pin

DDR2_A[0]

U10

DDR2_A[11]

AB3

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DDR2_A[1]

DDR2_A[12]

U14

DDR2_A[2]

T16

DDR2_BA[0]

DDR2_A[3]

R14

DDR2_BA[1]

AB10

DDR2_A[4]

AA4

DDR2_BA[2]

DDR2_A[5]

T11

DDR2_nCAS

R15

DDR2_A[6]

AB5

DDR2_CKE

DDR2_A[7]

T14

DDR2_CLK_P

AA17

DDR2_A[8]

AA3

DDR2_CLK_N

AB17

DDR2_A[9]

U13

DDR2_DQ[16]

AB15

DDR2_A[10]

DDR2_DQ[17]

W13

DDR2_nRAS

T10

DDR2_DQ[18]

AB14

DDR2_nWE

DDR2_DQ[19]

AA13

DDR2_ODT

R16

DDR2_DQ[20]

AB13

DDR2_DM[0]

DDR2_DQ[21]

AA14

DDR2_DM[1]

AA7

DDR2_DQ[22]

U12

DDR2_DM[2]

AA10

DDR2_DQ[23]

AA15

DDR2_DM[3]

AA16

DDR2_DQ[24]

T15

DDR2_DQ[0]

DDR2_DQ[25]

V15

DDR2_DQ[1]

DDR2_DQ[26]

W17

DDR2_DQ[2]

DDR2_DQ[27]

AB16

DDR2_DQ[3]

DDR2_DQ[28]

V14

DDR2_DQ[4]

DDR2_DQ[29]

AB20

DDR2_DQ[5]

DDR2_DQ[30]

W15

DDR2_DQ[6]

AA5

DDR2_DQ[31]

AB18

DDR2_DQ[7]

DDR2_DQS[0]

V10

DDR2_DQ[8]

AA9

DDR2_DQS[1]

AB9

DDR2_DQ[9]

AB8

DDR2_DQS[2]

Y13

DDR2_DQ[10]

Y10

DDR2_DQS[3]

V13

DDR2_DQ[11]

AA8

DDR2_DQ[12]

AB7

DDR2_DQ[13]

V11

DDR2_DQ[14]

DDR2_DQ[15]

W10

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Part 3: SPI Flash

The AC4040 FPGA core board A is equipped with one 64MBit SPI FLASH,

and the model is M25P64, which uses the 3.3V CMOS voltage standard. Due

to the non-volatile nature of SPI FLASH, it can be used as a boot device for the

system to store the boot image of the system. These images mainly include

FPGA bit files, core application code and other user data files. The specific

models and related parameters of SPI FLASH are shown in Table 3-1.

Position

Model

Capacity

Factory

M25P64

64M Bit

Table 3-1: SPI FLASH Specification

Figure 3-1: SPI Flash schematic

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Figure 3-2: M25P64 chip on the FPGA Board

SPI Flash pin assignments:

Pin Name

FPGA Pin

DCLK

nCSO

DATA0

ASDO

Part 4: FPGA Power Supply

In order for FGPA to work properly, we need to provide 3.3V, 1.8V, 2.5V,

1.2V and VCCIO five-way power for the FPGA. Let's talk about the power pin

portion of the FPGA, which includes the power pins for each bank, the core

voltage pins, the analog voltage, and the phase-locked loop power supply pins.

VCCINT is the FPGA core power supply pin, connected to 1.2V; VCCIO

is the power supply voltage of each BANK of the FPGA, where VCCIO1 is the

power supply pin of the BANK1 of the FPGA. Similarly, VCCIO2~VCCIO8 are

the power supply of the BANK2~BANK8 of the FPGA respectively. In the

AC4040 core board, VCCIO3 and VCCIO4 are connected to 1.8V, because

BANK3 and BANK4 are IOs connected to DDR2. The other BANK (BANK1~2,

BANK5~8) voltages are connected to the adjustable VCCIO, which enables the

BANK IO voltage of the FPGA to be flexibly adjusted. By adjusting the

resistance value of the VCCIO power supply part, different output voltages are

obtained, so that the FPGA core The board's IO level can be applied to different

voltages (the default VCCIO voltage is 3.3V). In addition, with DDR2 on the

core board, a termination power supply VTT and a reference power supply

VREF for DDR2 are required.

The power supply (VCCIO, 1.2V, 1.8V) with three large current

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requirements on the FPGA development board adopts the TLV62130RGT

DCDC chip imported from TI Company of the United States. It has high

efficiency, small size, no heat, can provide large current, small ripple, etc. It is

an excellent power solution for FPGA; a large number of high-grade imported

capacitors are used to ensure the system's power supply is stable and reliable.

The three-way DCDC power supply circuit is designed as follows:

Ce manuel convient aux modèles suivants

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