YASKAWA ANTAIOS Manuel utilisateur

ANTAIOS

Evaluation Kit

User Guide

PAAE1000/1001 | Revision 1.03

PAAE1000/1001 Evaluation Kit Revision 1.03 2/28

Liability Exclusion

We have tested the contents of this document regarding agreement with the hardware

and software described. Nevertheless, there may be deviations and we do not guarantee

complete agreement. The data in the document is tested periodically, however. Required

corrections are included in subsequent versions. We gratefully accept suggestions for

improvements.

Unless permission has been expressly granted, passing on this document or copying it, or

using and sharing its content are not allowed. Offenders will be held liable. All rights re-

served, in the event a patent is granted or a utility model or design is registered.

This document is subject to changes without prior notice.

Table of Contents

PAAE1000/1001 Evaluation Kit Revision 1.03 3/28

1Evaluation Kit Contents ..................................................................6

2Evaluation Board Overview ............................................................7

3Coreboard ........................................................................................9

3.1 Antaios ASIC (IC3)................................................................................................ 9

3.2 DDR2 SDRAM (IC4).............................................................................................. 9

3.3 JTAG Connector (X5)............................................................................................ 9

3.4 ETM Connector (X4).............................................................................................10

3.5 PortE - Debug Connector (X3)..............................................................................10

3.6 Test Pads.............................................................................................................11

4Mainboard ......................................................................................12

4.1 Power Supply.......................................................................................................12

4.2 Boot source select (X19)......................................................................................12

4.3 PortA - Quad SPI, NAND, SD/MMC .....................................................................12

4.4 PortB - Extension PCB connectors for Gigabit and external MII (X16, X17, X18) .13

4.5PortC –VPC, UART, CAN, PBM and GPIO(X55, X56).........................................14

4.6 PortD - Asynchronous External Interface (AEI), GPIOs, UART and TechIO.........15

4.7 I2C .......................................................................................................................15

4.8 UART 1/2 and USB to serial converter .................................................................16

4.9 SPI.......................................................................................................................16

4.10 Test pads and debug connectors X31, X30, X50..................................................17

4.11 Board to Board connectors (X27, X33).................................................................19

4.12 Boundary Scan (X22)...........................................................................................19

4.13 32MHz clock source.............................................................................................20

5Extension PCBs.............................................................................21

5.1 LP5480, ExtPHY_TI .............................................................................................21

5.2 LP5481, TechIO_Dv4...........................................................................................21

5.3 LP5482, SerialD...................................................................................................22

5.4 LP5483, GPHY.....................................................................................................23

5.5 LP5484, TechIO_Bv4...........................................................................................23

5.6 LP5485, ExtPHY_MC...........................................................................................23

5.7 LP5486, ExtPHY_BC............................................................................................24

5.8 LP5487, BroadR...................................................................................................24

5.9 Debug PCB LP5966C...........................................................................................25

6Order Information..........................................................................26

7Revision History ............................................................................27

List of Figures

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List of Figures

Figure 2-1 Mainboard.................................................................................................. 7

Figure 2-2 Coreboard.................................................................................................. 8

Figure 3-1 JTAG connector X5.................................................................................... 9

Figure 3-2 ETM connector X4 ....................................................................................10

Figure 3-3 PortE debug connector X3........................................................................11

Figure 4-1 24V DC connector X83 .............................................................................12

Figure 4-2 Bootsource selector X19...........................................................................12

Figure 4-3 QSPI CS selector X36...............................................................................13

Figure 4-4 MII interface of internal GMAC X16...........................................................13

Figure 4-5 External MII connectors X17 and X18.......................................................14

Figure 4-6 PortC box header X55 and X56 ................................................................15

Figure 4-7 I²C channel selector..................................................................................15

Figure 4-8 SPI0 CS selector.......................................................................................16

Figure 4-9 SPI master/slave selector..........................................................................17

Figure 4-10 PortA debug connector X30 and X31........................................................18

Figure 4-11 PortC debug connector X50......................................................................18

Figure 4-12 Board to board connectors X27 and X33...................................................19

Figure 4-13 Crystal oscillator Q1 as 32MHz clock source.............................................20

Figure 5-1 Extension PCB LP5480.............................................................................21

Figure 5-2 Extension PCB LP5481.............................................................................22

Figure 5-3 Extension PCB LP5482.............................................................................22

Figure 5-4 Extension PCB LP5483.............................................................................23

Figure 5-5 Extension PCB LP5484.............................................................................23

Figure 5-6 Extension PCB LP5485.............................................................................24

Figure 5-7 Extension PCB LP5486.............................................................................24

Figure 5-8 Debug PCB LP5966C...............................................................................25

List of Tables

PAAE1000/1001 Evaluation Kit Revision 1.03 5/28

List of Tables

Table 3-1 Coreboard test pads..................................................................................11

Table 4-1 UART2 to connector configuration ............................................................16

Table 4-2 Test pads mainboard ................................................................................17

Table 6-1 Order Information......................................................................................26

Table 7-1 Revision history.........................................................................................27

Evaluation Kit Contents

PAAE1000/1001 Evaluation Kit Revision 1.03 6/28

1 Evaluation Kit Contents

1x Evaluation board with extension PCBs

- 1x LP5483 (external GigaBit Phy)

- 1x LP5481 (technology IO)

1x Debug PCB LP5966

1x USB cable

2x Ribbon cable

1x DC connector

Evaluation Board Overview

PAAE1000/1001 Evaluation Kit Revision 1.03 7/28

2 Evaluation Board Overview

The ANTAIOS evaluation board consists of two basic components:

- The “mainboard” with all external interfaces, switches, LEDs, jumpers and power

supply powered by 24V DC

- The “coreboard” with the ANTAIOS ASIC itself, DDR2 Ram and JTAG/ETM interface

Figure 2-1 Mainboard

PortC

PortB

Power

Switch

PortA

PortD

USB 2.0

SliceBus

BootSource

select:

RTGPIO

GPIO

GMAC

SPI

BootStrap

UART 1/2

USB Debug

UART1

Serial Physics

(SSI, RS485, CAN)

Reset

Power

measurement

Copper/

Fiber

Connectors

24V

NAND

AEI

I²C

QSPI

Eth1Eth2

Evaluation Board Overview

PAAE1000/1001 Evaluation Kit Revision 1.03 8/28

Figure 2-2 Coreboard

The coreboard is plugged onto the mainboard using the connectors X27 and X33.

To ensure the mechanical connection the coreboard is additionally fixed with two screws.

The functionality of the evaluation board can be extended by adding so called extension

PCBs. See chapter “5 - Extension PCBs” for more details.

Coreboard

PAAE1000/1001 Evaluation Kit Revision 1.03 9/28

3 Coreboard

Antaios ASIC (IC3)3.1

LP5998: TFBGA380 15x15mm² with 0.65mm pitch.

LP5999: TFBGA385 19x19mm² with 0.80mm pitch.

DDR2 SDRAM (IC4)3.2

One Micron MT47H64M16NF-25E:M DDR 2 memory chip is assembled on the coreboard.

The usable memory is 64MByte of DDR2 SDRAM.

For debugging the DDR2 interface the contactless debug interface Keysight Soft Touch

E5394A is supported on connectors Y1 and Y2 but not assembled by default.

JTAG Connector (X5)3.3

The JTAG connector is used for connecting an in circuit debugger like “Power Debug” from

Lauterbach for on-chip debugging. The maximum JTAG frequency is 48MHz.

Figure 3-1 JTAG connector X5

Coreboard

PAAE1000/1001 Evaluation Kit Revision 1.03 10/28

ETM Connector (X4)3.4

In conjunction with a trace device like “PowerTrace” from Lauterbach the ETM connector can

be used to trace the program and data flow. The trace clock frequency is 144MHz.

Figure 3-2 ETM connector X4

PortE - Debug Connector (X3)3.5

PortE of ANTAIOS can be used to extend the ETM trace width from 16 to 32 data lines.

Additionally 16 real time GPIOs or debug signals for Profibus Master, ARAC and PPU tracing

can be driven to X3 by configuring the PinController of ANTAIOS.

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