Xilinx ML403 Instructions d'installation et d'utilisation

XAPP979 (v1.0) February 26, 2007 www.xilinx.com 1

a trademark of IBM Inc. All other trademarks and registered trademarks are the property of their respective owners. All speciﬁcations are subject to change without notice.

NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design, code, or information as one possible implementation of this feature,

application, or standard, Xilinx makes no representation that this implementation is free from any claims of infringement. You are responsible for obtaining any rights you may

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or representations that this implementation is free from claims of infringement and any implied warranties of merchantability or ﬁtness for a particular purpose.

Summary This application note describes how to build a reference system for the On-Chip Peripheral Bus

Inter IC (OPB IIC) core using the IBM PowerPC™ 405 Processor (PPC405) based embedded

system in the ML403 Embedded Development Platform. The reference system is Base System

Builder (BSB) based.

An IIC primer is given and an OPB IIC register reference is provided. The Xilinx Microprocessor

Debugger (XMD) commands are used for verifying that the OPB IIC core operates correctly.

Several software projects illustrate how to conﬁgure the OPB IIC core, set up interrupts, and do

read and write operations. Some of the software projects interface the OPB IIC to the

MicroChip 24LC04B serial EEPROM with an IIC interface, while others interface to the

TotalPhaseAardvark Adapter, whichprovidesIICmaster andslavefunctionality.The procedure

for using ChipScope™ to analyze OPB IIC functionality is provided. The steps used to build a

Linux kernel using MontaVista are listed. Simulation output ﬁles for analyzing basic IIC

transactions are provided.

Included

Systems This application note includes one reference system:

www.xilinx.com/bvdocs/appnotes/xapp979.zip

The project name used in xapp979.zip is ml403_ppc_opb_iic.

Required

Hardware/Tools Users must have the following tools, cables, peripherals, and licenses available and installed:

•Xilinx EDK 8.2.02i

•Xilinx ISE 8.2.03

•Xilinx Download Cable (Platform Cable USB or Parallel Cable IV)

•Monta Vista Linux v2.4 Development Kit

•Modeltech ModelSim v6.1d

•ChipScope v8.2

Application Note: Embedded Processing

XAPP979 (v1.0) February 26, 2007

Reference System: OPB IIC Using the

ML403 Evaluation Platform

Author: Paul Glover, Ed Meinelt, Lester Sanders

Introduction

XAPP979 (v1.0) February 26, 2007 www.xilinx.com 2

Introduction This application note accompanies a reference system built on the ML403 development board.

Figure 1 is a block diagram of the reference system.

The system uses the embedded PowerPC (PPC) as the microprocessor and the OPB IIC core.

IIC Primer

Figure 2 shows components on an IIC bus.Two IIC masters and three IIC slaves are shown.

The master is responsible for setting up transactions. This includes generating the clock on

SCL and deﬁning which slave is involved in the communication, with an address ﬁeld, and

which component is transmitting and which component is receiving. Some components are

slave only, while others can transition between master and slave operation.

Figure 3 shows the START and STOP conditions. A START condition is a falling edge on SDA

when SCL is high. A STOP condition is a rising edge on SDA when SCL is high. During data

transfer, the data line is stable on SDA when SCL is high. Data transitions on SDA when SCL

is low. Note that the START and STOP conditions are special conditions, violating the rule that

data cannot transition while SCL is high.

Figure 1: OPB IIC Reference System Block Diagram

Figure 2: IIC Bus

Figure 3: Start and Stop Conditions

PowerPC™

405 Processor

OPB

INTC OPB UART

16550

PLB

DDR PLB

BRAM

OPB

IIC

OPB

PLB

X979_01_022307

S1S2

M1 M2

X979_02_022307

SCL SDA

X979_03_022307

SDA

Start Stop

SCL

Introduction

XAPP979 (v1.0) February 26, 2007 www.xilinx.com 3

Figure 4 shows the format of the data transfer of two bytes on the IIC bus, beginning with the

START (S) condition and ending with the STOP (P) condition, bounded by an idle IIC (F) bus.

After a START condition, an eight bit ﬁeld is transmitted containing a 7 bit address and a single

Read/Write (R/W) bit. This 8 bit address/direction ﬁeld is followed by an Acknowledge bit. After

the address/data ﬁeld, an eight bit data ﬁeld is followed by an acknowledge bit (A). The last 8-

bit data ﬁeld is followed by a not acknowledge bit (A). This is followed by the STOP condition

(P).

A single message can contain multiple start conditions, or a repeated start, without intervening

STOP conditions.

In this data transfer, there are two acknowledge bits and one Not Acknowledge on the IIC bus.

The distinction between a Not Acknowledge and a No Acknowledge is that Not Acknowledge

occursafter a master has read a bytefrom a slave and a NoAcknowledgeoccurs after a master

has written a byte to a slave.

A synchronized SCL is generated with its LOW period determined by the device with the

longest low period and its HIGH period determined by the device with the shortest HIGH

period.

Figure 5 shows the data transfer on the IIC bus, beginning with the START condition and

ending with the STOP condition.

Figure 4: Data Transfer on the IIC Bus

Figure 5: Generic Data Transer on the IIC Bus

SDA

Slave

Address

FAAR/WSPF

SCL X979_04_012907

DataDataA

12 127893- 89

Acknowledgment

signal from slave Acknowledgment

signal from receiver

Byte complete;

interrupt within slaveClock linesheld low while

interruptsare serviced

X979_05_022307

START or

repeated START

condition

STOP or

repeated START

condition

MSB

SCL

SDA

ACKACK

Reference System Speciﬁcs

XAPP979 (v1.0) February 26, 2007 www.xilinx.com 4

Figure 6 shows the acknowledge bit on the IIC bus.

Figure 7 shows bus arbitration of two masters. The IIC bus is a multi-master bus. Masters

monitor the IIC bus to determine if the bus is active. The bus is inactive when SCL and SDA are

high for a bus free period tBUF of 1.3 us (FAST) or 4.7 us (STD). If two or more masters

monitoring the IIC bus determine that the bus is free and begin a bus transaction

simultaneously, the IIC bus is arbitrated to determine which master owns the bus. The IIC is a

wired AND bus. This means that the bus is HIGH unless any component is driving it LOW.

Masters monitor the bus even after they have started a transaction as the master. If a master is

not driving the IIC bus low and the bus is low, the master knows that another master is driving

the IIC bus. If a master cannot get the SDA or SCL to go high it loses arbitration. When a master

loses arbitration, it stops transmission. The master driving the bus with the last low when the

other master(s) drives high becomes the master of the bus.

Reference

System

Speciﬁcs

In addition to the PowerPC405 processor and OPB IIC, this system includes DDR and BRAM

memory on the PLB, and a UART and interrupt controller on the OPB. Figure 1 provides the

block diagram. Table 1 provides the address map of the ML403 XC4VFX12. This is in the

system.mhs.

Figure 6: Acknowledge on the IIC Bus

Figure 7: Arbitration of two Masters

12 89

Clock pulse for

acknowledgment

X979_06_012907

START

condition

Not acknowledge

Acknowledge

Dataoutput

by transmitter

Dataoutput

by receiver

SCL from

master

Master 1

Master 2

SDA

SCL

SX979_07_012907

Reference System Speciﬁcs

XAPP979 (v1.0) February 26, 2007 www.xilinx.com 5

ML403 XC4VFX12 Address Map

OPB IIC Registers

Table 2 provides the register map for the OPB IIC core.

Table 3 provides a description of the OPB IIC control register.

Table 1: ML403 XC4VSX12 System Address Map

Peripheral Instance Base Address High Address

PLB_DDR DDR_SDRAM_32Mx64 0x00000000 0x03FFFFFF

OPB UART16550 RS232_Uart_1 0x40400000 0x4040FFFF

OPB INTC opb_intc_0 0x41200000 0x4120FFFF

PLB BRAM plb_bram_if_cntlr_0 0xFFFF8000 0xFFFFFFFF

OPB IIC IIC_EEPROM 0x40800000 0x4080FFFF

Table 2: OPB IIC Registers

Device Global Interrupt Enable C_BASEADDR + 0x01C

Interrupt Status Register C_BASEADDR + 0x020

Interrupt Enable Register C_BASEADDR + 0x028

Software Reset Register C_BASEADDR + 0x040

Control Register C_BASEADDR + 0x100

Status Register C_BASEADDR + 0x104

Transmit FIFO C_BASEADDR + 0x108

Receive FIFO C_BASEADDR + 0x10C

Slave Address Register C_BASEADDR + 0x110

Transmit FIFO Occupancy C_BASEADDR + 0x114

Receive FIFO Occupancy C_BASEADDR + 0x118

Ten Bit Slave Address Register C_BASEADDR + 0x11C

Receive FIFO Programmable Depth Interrupt Register C_BASEADDR + 0x120

General Purpose Output C_BASEADDR + 0x124

Table 3: OPB IIC Control Register

Bit(s) Name Description

0- 24 Reserved Reserved.

25 GC_EN General Call Enable. Setting this bit High allows the OPB IIC to respond to a

general call address.

26 RSTA

Repeated Start. Writing a “1” to this bit generates a repeated START condition

on the bus if the OPB IIC Bus Interface is the current bus Master. Attempting a

repeatedSTARTatthewrongtime,if the bus is ownedby another Master, results

in a loss of arbitration. This bit is reset when the repeated start occurs. This bit

must be set prior to writing the new address to the Tx FIFO or DTR.

Reference System Speciﬁcs

XAPP979 (v1.0) February 26, 2007 www.xilinx.com 6

Status Register (SR)

This register contains the status of the OPB IIC Bus Interface. All bits are cleared upon reset.

Table 4 provides a deﬁnition of the status register.

27 TXAK

Transmit AcknowledgeEnable. Thisbit speciﬁesthe valuedrivenontothe SDA

line during acknowledge cycles for both Master and Slave receivers.

Because Master receivers indicate the end of data reception by not

acknowledging the last byte of the transfer, this bit is used to end a Master

receiver transfer. As a slave, this bit must be set prior to receiving the byte to no

acknowledge.

28 TX

Transmit/Receive Mode Select. This bit selects the direction of Master/Slave

transfers. This bit does not control the Read/Write bit that is sent on the bus with

the address. The Read/Write bit that is sent with an address must be the LSB of

the address written into the transmit FIFO.

29 MSMS

Master/Slave Mode Select. When this bit is changed from 0 to 1, the OPB IIC

Bus Interface generates a START condition in Master mode. When this bit is

cleared, a STOP condition is generated and the OPB IIC Bus Interface switches

to Slave mode. When this bit is cleared by the hardware, because arbitration for

the bus has been lost, a STOP condition is not generated.

30 Tx FIFO

Reset Transmit FIFO Reset.This bit must be set if arbitration is lost or if a transmit error

occurs to ﬂush the FIFO.

31 EN OPB IIC Enable. This bit must be set before any other CR bits have any effect.

Table 4: Status Register Bit Deﬁnitions

Bit(s) Name Description

0 - 23 N/A Reserved.

24 Tx_FIFO_

Empty Transmit FIFO empty. This bit is set High when the transmit FIFO is

empty.

25 Rc_FIFO_

Empty Receive FIFO empty. Thisis set High when the receiveFIFO is empty.

26 Rc_FIFO_

Full Receive FIFO full. This bit is set High when the receive FIFO is full.

This bit is set only when all sixteen locations in the FIFO are full,

regardless of the value written into Rc_FIFO_PIRQ.

27 Tx_FIFO_F

ull Transmit FIFO full. This bit is set High when the transmit FIFO is full.

28 SRW Slave Read/Write. WhentheIIC Bus Interfacehas been addressedas

a Slave (AAS is set), this bit indicates the value of the read/write bit

sent by the Master. This bit is only valid when a complete transfer has

occurred and no other transfers have been initiated. A “1” indicates

Master reading from Slave. A “0” indicates Master writing to Slave.

29 BB Bus Busy. This bit indicates the status of the IIC bus. This bit is set

when a START condition is detected and cleared when a STOP

condition is detected.

Table 3: OPB IIC Control Register (Contd)

Bit(s) Name Description

Reference System Speciﬁcs

XAPP979 (v1.0) February 26, 2007 www.xilinx.com 7

Table 5 provides a register description of the Interrupt Status register.

30 AAS Addressed as Slave. When the address on the IIC bus matches the

Slave address in the Address Register (ADR), the IIC Bus Interface is

being addressed as a Slave and switches to Slave mode. If 10-bit

addressing is selected this device will only respond to a 10-bit address

or general call if enabled. This bit is cleared when a stop condition is

detected or a repeated start occurs.

31 ABGC Addressed By a General Call. This bit is set high when another

master has issued a general call and the general call enable bit is set

high, CR(1) = ’1’.

Table 5: Interrupt Status Register

Bit Name Description

24 TFHE Transmit FIFO Half Empty

25 NAAS Not Addressed as Slave

26 AAS Addressed as Slave

27 BNB Bus is not Busy

28 RFF Receive FiFO Full

29 TFE Transmit FIFO Empty

30 TE/STC Transmit Error/Slave Transmit Complete

31 AL Arbitration Lost

Table 4: Status Register Bit Deﬁnitions (Contd)

Bit(s) Name Description

Reference System Speciﬁcs

XAPP979 (v1.0) February 26, 2007 www.xilinx.com 8

Conﬁguring the OPB IIC Core

Figure 8 shows how to specify the values of IIC generics in EDK. To access the dialog box in

the ﬁgure, double click on the OPB IIC core in the EDK System Assembly View..

Microchip 24LC04

The Microchip Technology 24LC04B-I/ST with 4-KB EEPROM is provided on the ML403 board

to store non-volatile data. The EEPROM write protect is tied off on the board to disable its

hardware write protect. The IIC bus is extended to the expansion connector to allow additional

devices to be added to the IIC bus.

Figure 9 shows IIC Bus Devices on the ML403.

Figure 9: ML403 IIC Bus

The 24LC04 is organized as two blocks of 256 bytes. It has a page write buffer of up to 16

bytes. The 24LC04 operates as an IIC slave. The 24LC04 accepts a control byte which

contains control code, block select, and Read/Write ﬁelds shown in Figure 10. The control code

Figure 8: Specifying the Values of OPB IIC Generics in EDK

X979_08_012907

XC4VSX12

FPGA Microchip

24LC04B

I/O

Expansion

Header

X979_09_022307

SCL

SDA

ML403 Board Information

XAPP979 (v1.0) February 26, 2007 www.xilinx.com 9

is ‘1010 for read and write operations. The A2, A1 bits are dont cares. The A0 bit is used by the

master device to select which of the two 256-word blocks of memory are accessed. The

24LC04 write transactions are either a byte write or a page write. The page write begins the

same as the byte write but instead of generating a stop condition the master transmits up to 16

data bytes to the 24LC04B. The 24LC04 supports current address, random, and sequential

read operations.

ML403 Board

Information According to the MicroChip 24L024B data sheet, the ML403 board has a low-level output

current (IOL) of 3.0 mA at a VCC of 2.5v. The ML403 boards are shipped in the conﬁguration

shown in Figure 11. The board must be modiﬁed for this design to work correctly. Replace the

10K Ohm R70 and R71resistors with 833 or 1K Ohm resistors. See Answer Record 24049 for

additional information.

Figure 10: 24LC04 Control Byte Allocation

Slave

Address

AR/W

A01

X979_10_012907

010A2A1

Figure 11: ML40x Schematic for IIC Connections

24LC04B - I / ST

VCC2V5

IIC_SCL

IIC_SDA

VCC

SCL

SDA

TSSOPSU9

R71

10k

R70

10k

C280

0.1 µF

X979_11_022307

ML403 Board Information

XAPP979 (v1.0) February 26, 2007 www.xilinx.com 10

The resistors are located on the board as shown in Figure 12.

Figure 12: ML40x Resistors

X979_12_022307

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