Wiener AVM16 Manuel utilisateur
1
16 channel ADC, 160 MHz
with features extraction
User’s Manual
W-I
e
–N
e
-R
AVM16 / AVX16
3
General Remarks
The only purpose of this manual is a description of the product. It must not be interpreted as a
declaration of conformity for this product including the product and software.
W-I
e
-N
e
-R revises this product and manual without notice. Differences between the description
in manual and the product are possible.
W-I
e
-N
e
-R excludes completely any liability for loss of profits, loss of business, loss of use or
data, interrupt of business, or for indirect, special incidental, or consequential damages of any
kind, even if
W-I
e
-N
e
-R has been advises of the possibility of such damages arising from any defect or error
in this manual or product.
Any use of the product which may influence health of human beings requires the express written
permission of W-I
e
-N
e
-R.
Products mentioned in this manual are mentioned for identification purposes only. Product names
appearing in this manual may or may not be registered trademarks or copyrights of their respective
companies.
No part of this product, including the product and the software may be reproduced, transmitted,
transcribed, stored in a retrieval system, or translated into any language in any form by any means
without the express written permission of W-I
e
-N
e
-R.
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Table of contents:
1 GENERAL SPECIFICATIONS 5
2 GENERAL DESCRIPTION 6
3 INPUT CIRCUITRY 8
4 TRIGGERING 9
4.1 Internal trigger functionality 9
4.2 External trigger functionality 9
4.3 Software trigger 9
5 TECHNICAL DESCRIPTION OF AVM-16 / AVX-16 10
5.1 Technical description 11
5.2 FPGA logic 12
5.2.1 Window control 12
5.2.2 Feature Extraction 12
5.3 VME addressing 13
5.4 Software registers 14
5.4.1 Overview of registers 14
5.4.2 First group of registers (control FPGA) 15
5.4.3 Registers that are sent to all ADC FPGAs too. 18
5.4.4 Registers that are individually available for every channel. 20
5.4.5 Registers for data readout in single or block transfer mode. 20
5.5 Decoding output 21
5.6 Example of data readout 25
5.6.1 Sample column 28
5.6.2 Raw data column 28
5.6.3 Time column 28
5.6.4 Hex column 28
5.6.5 Dec column 28
5.6.6 Absolute column 28
5.6.7 Absolute hex 29
5.6.8 Register value 29
5
1General Specifications
Bus standard VME-64, VME-64/VXS
No. of channels 16
Input standard LEMO
Sampling speed 160 MHz
Input voltage range +/- 1.000 V
Bandwidth - 10 Hz..100 MHz (DC, full bandwidth option)
- 200 kHz..user limited (AC, limited bandwidth)
Resolution 12 bit
Noise 0.8 LSB (RMS)
Buffer length 1024 samples (6.4 us). 4 buffers for 16 channe1s
Synchronization - External front panel connector ECL/PECL/LVDS
- Dedicated VME pins for customizations
Clock - Internal clock 160 MHz
- External front panel connector ECL/PECL/LVDS
- Dedicated VME pins for customizations
Trigger options - External front panel connector ECL/PECL/LVDS,
- Internal self-triggering mode
Integration time window - relative to trigger time or to pulse arrival time
Time resolution 1.5625 ns (interpolated signal t0)
Feature extraction - Amplitude
- Integral
- Time of arrival
- Multiple pulses (times, minima, maxima, partial charges)
Zero-suppression - amplitude threshold common for all channels
- integral threshold individual for every channel
Readout mode - Limited verbosity (only charge and time for the main pulse)
- Extended verbosity (full set of extracted parameters)
- Raw data mode (plus extracted parameters)
Self-Test Internal pulse generator with programmable amplitude
Configuration - Remote via VME
- Local via JTAG connector
Addressing space 256 locations (0..FF)
Base address 00FF8000-00FFBF00 (32 locations)
Addressing mode A24/D16, A24/D32, A32/D16, A32/D32, AD64
Power requirements VME-32 +5V/ 4A,
VME-64 +5V / 2A, +3.3V/2A
6
2General description
The AVM-16 / AVX-16 modules contain four quad-channel ADC blocks, a VME / VXS control
part and a clock and synchronization utility, see figure 1.
Figure 1:AVM-16 / AVX-16 design overview. Please note that the SYNCH section is meant
customizations. Only the external trigger input is present on all boards.
AMP+ADC
AMP+ADC
AMP+ADC
AMP+ADC
Feature
extraction
FPGA
AMP+ADC
AMP+ADC
AMP+ADC
AMP+ADC
Feature
extraction
FPGA
AMP+ADC
AMP+ADC
AMP+ADC
AMP+ADC
Feature
extraction
FPGA
AMP+ADC
AMP+ADC
AMP+ADC
AMP+ADC
Feature
extraction
FPGA
Control
FPGA
P1
P2
P0
VXS
SYNCH
(ECL, PECL, LVDS
SIGNAL INPUTS (LEMO)
Clock
MUX
CLK
SYNC
TRG
PRE_TRG
CLK
SYNC
Clock, Synch, Trigger &
Config
uration
Data Local Bus
Data Local Bus
VME Bus
VME Bus
VME interface
VME interface
Status
LED
AVM-16 / AVX-16
7
Each of the ADC channel is equipped with a symetrizing amplifier, anti-aliasing filter and an
individual 12-bit Analog-to-Digital converter running at 160 Msamples/s.
After conversion, the digital data is passed to 4 FPGA circuits providing buffers for data retention
and a feature extraction logic. One Spartan-3 FPGA from Xilinx is used for a block of four
channel keeping a history of 1024 samples for each channel in it’s internal registers. Feature
extraction algorithms are used for calculate important parameters of the input pulses, such as
amplitude, time, intergrals and many others, which allows for minimizing of the readout data
volume and thus increasing the readout speed. The user may still choose to read a full set of
samples, recorded in the buffer or read s ubset of those samples within specified time boundaries,
being in relation to the trigger.
After a trigger request from a Data acquisition system, the stored and/or extracted data is passed to
a control FPGA chip via four Data Local Busses and then transferred over a VME bus or a VXS
backplane P2P connection fabric.
In multichannel systems, where a common time base is required, a global clock and
synchronization signals are provided over a front panel connector or over a non-legacy user VME
connector pins. The clocking and synchronization circuitry allows for choosing of the clock
source.
8
3Input circuitry
The input AC filter provides an effective cut-off for bacground low frequency noise and mains
pick-up. DC coupling is possible on demand. The symmetrizing amplifiers provide a differential
input for the ADC circuits, reducing PCB noise pickup. The anti-aliasing filter allows for precise
parametrization of input pulses as short as 10 ns FWHM. The anti-aliasing filter can be
customized or removed by the manufacturer or by an authorized person, see figure 2.
An on-board pulse generator provides test pulses for every channel.
R1
51
1
2
3
4
5
67
8
V+
V-
Vcm
U1
AD8132AR
R5 51
R7 51
R3
1k
R6
510
R4
510
R2
1k
C1
100nF C2
C_fil
C3
100nF
VCC
TEST PULSE
COMMON LEVEL
1
2
J1
BNC
ADCp
ADCn
Figure 2: Input symetrizing amplifier and anti-aliasing filter (R5, R7, C2). The gain
resistors, the location of the test pulse and the values and locations of capacitors may
depend on AVM16 version or be customized.
9
4Triggering
AVM16 / AVX16 can either be trigger internally or externally. The external trigger time is
distributed via a broadcast command. Trigger time is used to set time boundaries for scanning the
Dual-Ported RAM’s, given user defined trigger latency and trigger window, see figure 3.
The trigger source configuration is in register 0x100.
4.1 Internal trigger functionality
When the signal in one of the non inhibited channels overcomes the trigger level set in the register
0x110 with reference to the actual baseline, all non inhibited channels are read out. The trigger
condition is
ADC_VALUE > BASE_LINE + TRIGGER_LEVEL
and is checked at 80 MHz rate, each time for two samples sequentially. The trigger uncertainty is
thus +/- 1 sample, corresponding to a range of 12.5 ns.
4.2 External trigger functionality
All non inhibited channels are read out when a LVDS singal is feed into the TRG port on the front
panel.
4.3 Software trigger
All non inhibited channels are read out upon write on bit 2 of register 0x104
Figure 3: Data window for feature extraction
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5Technical description of AVM-16 / AVX-16
Figure 6. shows location of key connectors user may interface to
Figure 4: The AVM-16 / AVX-16 Printed circuit board
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