Toshiba TMP91C824F Guide produit

REV2.6July. 12, 2002

Rev. 2.6 12/July/2002

16bit Micro controlle

TLCS-900/L1 series

TMP91C824F

Data Book

contents

Table of Contents

TLCS-900/L1 Devices

TMP91C824F

1. OUTLINE AND DEVICE CHARACTERISTICS ……………………… 91C824-1

2. PIN ASSIGNMENT AND PIN FUNCTIONS ……………………… 91C824-4

3. OPERATION …………………………………………………………91C824-9

3.1 CPU …………………………………………………………………… 91C824-9

3.2 Memory Map ………………………………………………………… 91C824-11

3.3 Triple clock, Stand-by function, Noise reduction ………………………… 91C824-12

3.4 Interrupts ……………………………………………………………………91C824-36

3.5 Functions of Ports …………………………………………………………… 91C824-51

3.5.1 Port 1 ……………………………………………………………… 91C824-55

3.5.2 Port 2 ……………………………………………………………… 91C824-56

3.5.3 Port 5 ……………………………………………………………… 91C824-58

3.5.4 Port 6 ……………………………………………………………… 91C824-61

3.5.5 Port 7 ……………………………………………………………… 91C824-62

3.5.6 Port 8 ……………………………………………………………… 91C824-66

3.5.7 Port B ……………………………………………………………… 91C824-67

3.5.8 Port C ……………………………………………………………… 91C824-70

3.5.9 Port D ……………………………………………………………… 91C824-73

3.6 Chip Select / Wait Controller ……………………………………………… 91C824-78

3.7 8-bit Timers(TMRA) ……………………………………………………… 91C824-88

3.8 Memory Management Unit ……………………………………………… 91C824-108

3.9 Serial Channel ……………………………………………………………… 91C824-119

3.10Serial Bus Interface ………………………………………………………… 91C824-151

3.11 Analog / Digital Converter ………………………………………………… 91C824-179

3.12 Watch Dog Timer ………………………………………………………… 91C824-189

3.13 RTC ………………………………………………………………………… 91C824-195

3.14 Melody / Alarm Generator ………………………………………………… 91C824-209

4. ELECTRICAL CHARACTERISTICS ……………………… 91C824-215

5. TABLE OF SFR ……………………………………………………… …91C824-227

8. PACKAGES …………………………………………………………………… 91C824-252

Data Book modification history

Rev./Date page Modification item Reason

109 Bank Operation S/W Example in MMU

218 Recommended Crystal oscillation Circuit

165 Stop condition generation

Rev12/Mar-15-2001

166 Timing diagram for TMP91C824 Restart

Rev14/July-16-2001 12-24 DFM(triple cock modify)

17,240 EMCCR3

159,168

Add ed the sentence and diagram at SBI

155 Modify bit6(TRX)

Rev14/July-26-2001

114 Added the diagram and sentence of MMU

Rev21/August-21-2001 14 CPU: modify the figure

Rev22/September-21-2001

222 Electric Specification

Rev22/September-7-2001 226 Murata factory URL added

Rev23/October-26-2001 217 33MHZ AC added

216 Syntax err

“2V SLOW ICC”-> “2V NORMAL ICC”

Unit “uA”-> “mA”

Rev24/January-18-2002

221 Spec modify

AD converter

IREF max 1.20mA -> 1.35mA

contents

Remove “TENTATIVE”of ELECTRICAL

CHARACTERISTICS

1Add the comment about JTMP91C824

Modify the frequency of Micro DMA Change the

reference

2Add the comment about package Mistake

16,240 Modify the input frequency of (DFMCR1) Mistake

29 Modify the name SBI0BR1àSBI0BR0 in the

table 3.3.2 Mistake

30,251 Add the limitation about HALT mode Mistake

*Important

matter

48,236 Add the comment to the register IIMC bit6

Mistake

55 Modify the comment in the figure Mistake

87 Add the figure for connecting SRAM Shortage

97,98 Modify WàR/W and remove the note Mistake

100,104

106 Modify the name of the register in the

program P7àPB Mistake

146 Modify the name of the register in the

program P9àPC Mistake

208 Add the limitation about RTC Mistake

*Important

matter

212 Modify the name of scale in the table Change

expression

226 Change the comment about MURATA at

the bottom Change

expression

Rev2.5/June-21-2002

240 Remove the note Mistake

15,239 Add the word “IDLE1”to the bit0 of

(SYSCR2) register MistakeRev2.6/July-12-2002

30,251 Add the INTALM0 to 4 in the(note) Mistake

※Each page number depends on the revision when it’s made.

TMP91C824

91C824-1

CMOS 16-Bit Microcontrollers

TMP91C824F/JTMP91C824-S

1. OUTLINE AND FEATURES

TMP91C824F is a high-speed 16-bit microcontroller designed for the control of various mid- to large-scale

equipment.

TMP91C824F comes in a 100-pin flat package and a 100-pad Dice form. JTMP91C824-S is a chip form

product.

Listed below are the features.

(1) High-speed 16-bit CPU (900/L1 CPU)

• Instruction mnemonics are upward-compatible with TLCS-90

• 16 Mbytes of linear address space

• General-purpose registers and register banks

• 16-bit multiplication and division instructions; bit transfer and arithmetic instructions

• Micro DMA: 4 channels (0.5 µs/2 bytes at 33 MHz)

(2) Minimum instruction execution time: 121 ns (at 33 MHz)

(3) Built-in RAM: 8 Kbytes

Built-in ROM: None

(4) External memory expansion

• Expandable up to 106M bytes (shared program/data area)

• Can simultaneously support 8-/16-bit width external data bus

…Dynamic data bus syzing

• Separate bus system

(5) 8-bit timers: 4 channels

(6) General-purpose serial interface: 2 channels

• UART/Synchronous mode: 2 channels

• IrDA Ver.1.0 (115.2kbps) mode selectable: 1 channel

(7) Serial bus interface: 1 channel

• I2C bus mode/clock synchronous mode selectable

Purchase of TOSHIBA I

C components conveys a license under the Philips I

C Patent Rights to use these components in a

C system, provided that the system conforms to the I

C Standard Specification as defined by Philips.

• For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3 of the chapter entitled Quality and

Reliability Assurance / Handling Precautions.

• TOSHIBA is continually working to improve the quality and the reliability of its products. Nevertheless, semiconductor devices in general can

malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when

utilizing TOSHIBA products, to observe standards of safety, and to avoid situations in which a malfunction or failure of a TOSHIBA product

could cause loss of human life, bodily injury or damage to property. In developingyour designs, please ensure that TOSHIBA products are used

within specified operating ranges as set forth in the most recent products specifications. Also, please keep in mind the precautions and conditions

set forth in the TOSHIBA Semiconductor Reliability Handbook.

• The products described in this document are subject to foreign exchange and foreign trade laws.

• The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA

CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is

granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others.

• The information contained herein is subject to change without notice.

980508TBA1

TMP91C824

91C824-2

(8) Timer for real-time clock (RTC)

• Based on TC8521A

(9) 10-bitA/D converter : 8 channels

(10) Watch dog timer

(11) Melody/Alarm generator

• Melody: Output of clock 4 to 5461Hz

• Alarm: Output of the 8 kinds of alarm pattern

• Output of the 5 kinds of interval interrupt

(12) Chip select/Wait controller: 4 channels

(13) Memory Management Unit

• Expandable up to 106M bytes (4 local area/8bank method)

(14) Interrupts: 37 interrupts

• 9 CPU interrupts: Software interrupt instruction and illegal instruction

• 23 internal interrupts: 7 priority levels are selectable

• 5 external interrupts: 7 priority levels are selectable (among 4 interrupts are selectable

edge mode)

(15) Input/output ports: 35 pins (@External 16-bit data bus memory)

(16) Stand-by function

Three Halt modes: Idle2 (programmable), Idle1 and Stop

(17) Triple-clock controller

• Clock doubler (DFM) circuit is inside

• Clock gear function: Select a High-frequency clock fc/1 to fc/16

• RTC (fs=32.768kHz)

(18) Operating voltage

• VCC = 2.7 V to 3.6 V (fc max = 33 MHz)

• VCC = 1.8 V to 3.6 V (fc max = 10 MHz)

(19) Package

• 100-pin QFP: LQFP100 - P -1414 - 0.5D

• Chip form supply also available. For details, contact your local Toshiba sales

representative.

TMP91C824

91C824-3

Figure 1.1 TMP91C824F Block Diagram

8KB RAM

CPU (TLCS-900/L1)

10-BIT 8CH

A/D

CONVERTER

H-OSC

SIO/UART/IrDA

(SIO0)

8BIT TIMER

(TMRA0)

32 bit F

XWA

XBC

XDE

XHL

XIX

XIY

XIZ

XSP

W A

TXD0

(

PC0

)

RXD0 (PC1

)

TXD1

(

PC3

)

RXD1 (PC4)

DVCC [3]

DVSS [3]

D0 toD7

A0 to A7

A8 to A15

P10 to P17(D8 to D15)

P20 to P27

(A16 toA23)

N0 to

(P80 to P87)

AVCC, AVSS

VREFH, VREFL

SCOUT(PD5)

RESET

AM0

AM1

WDT

(Watch

DogTimer)

Clock Gear,

Clock Doubler

SIO/UART

(SIO1)

HWR(P52)

WAIT (P53)

BUSRQ (P54)

BUSAK(P55)

R/W (P56)

L-OSC

EMU0

EMU1

PORT 5

CS/WAIT

CONTROLLER

(4-BLOCK)

PORT 2

CS0 toCS3

,CS2A〜CS2E

INTERRUPT

CONTROLLER

INT0 to INT3

MELODY/

ALARM-OUT MLDALM(PD7)

8BIT TIMER

(TMRA1)

TA1OUT (PB1)

8BIT TIMER

(TMRA2)

8BIT TIMER

(TMRA3)

TA3OUT (PB2

)

( ) : Initial Function After Reset

B C

D E

H L

ADTRG(P83)

SCLK1/ CTS1(PC5

)

(P60 to P67)

PORT 1

PORT 6

PORT 8

PORT B

PORT C

PORT D

(PB3 to PB6),

SCLK0/CTS0 (PC2)

OPTRX0,SCK

(

P70

)

OPTTX0,SO/SDA

(P71) SERIAL BUS

I/F(SBI)

SI/SCL

(P72

)

RTC ALARM,MLDALM(PD6)

XT1

XT2

TA0IN (PB0)

NMI

MMU

TMP91C824

91C824-4

2. PIN ASSIGNMENT AND PIN FUNCTIONS

The assignment of input/output pins for the TMP91C824F, their names and functions are as follows:

2.1 Pin Assignment Diagram

Figure 2.1.1 shows the pin assignment of the TMP91C824F.

VREFL

TMP91C824

QFP100

TOPVIEW

100

AVSS

P80/AN0

P81/AN1

P82/AN2

P83/AN3/ADTRG

P84/AN4

P85/AN5

P86/AN6

P87/AN7

AVCC

P70/SCK/OPTRX0

P71/S0/SDA/OPTTX0

P72/SI/SCL

TA0IN/PB0

TA1OUT/PB1

TA3OUT/PB2

INT0/PB3

INT1/PB4

INT2/PB5

INT3/PB6

P55/BUSAK

DVCC1

A11

A12

A13

A14

A15

P20/A16

P21/A17

P22/A18

P23/A19

P24/A20

P25/A21

DVCC2

NMI

DVSS2

P26/A22

P27/A23

P17/D15

P16/D14

P15/D13

P14/D12

P13/D11

P12/D10

P11/D9

P10/D8

PD7/MLDALM

PD6/ALARM/MLDALM

PD5/SCOUT

SCLK1/CTS1/PC5

RXD1/PC4

TXD1/PC3

SCLK0/CTS0/PC2

RXD0/PC1

TXD0/PC0

EMU1

EMU0

XT2

XT1

RESET

AM1

DVSS1

P64/EA24/CS2B

P56/WAIT

P65/EA25/CS2C

P63/CS3

P62/CS2/CS2

P61/CS1

P60/CS0

P67/CS2E

PZ3/R/W

PZ2/HWR

VREFH

AM0

P66/CS2D

P54/BUSRQ

Figure 2.1.1 Pin assignment diagram (100-pin QFP)

TMP91C824

91C824-

2.2 Pad Layout

(Chip size 4.37mm ×4.37mm) unit (μm)

no Name X

point Y

point PIN

No Name X

point Y

point PIN

No Name X

point Y

point

1 VREFL -2050 1721 35 PC0 -140 -2050 69 P21 2045 939

2 AVSS -2050 1596 36 PC1 -14 -2050 70 P20 2045 1075

3 AVCC -2050 1470 37 PC2 112 -2050 71 A15 2045 1207

4 P80 -2050 1337 38 PC3 238 -2050 72 A14 2045 1337

5 P81 -2050 1209 39 PC4 365 -2050 73 A13 2045 1464

6 P82 -2050 1076 40 PC5 491 -2050 74 A12 2045 1592

7 P83 -2050 943 41 PD5 618 -2050 75 A11 2045 1721

8 P84 -2050 810 42 PD6 744 -2050 76 A10 1720 2045

9 P85 -2050 677 43 PD7 871 -2050 77 A9 1591 2045

10 P86 -2050 544 44 D0 998 -2050 78 A8 1464 2045

11 P87 -2050 416 45 D1 1124 -2050 79 A7 1337 2045

12 P70 -2050 148 46 D2 1251 -2050 80 A6 1197 2045

13 P71 -2050 15 47 D3 1377 -2050 81 A5 1058 2045

14 P72 -2050 -118 48 D4 1504 -2050 82 A4 918 2045

15 PB0 -2050 -251 49 D5 1630 -2050 83 A3 778 2045

16 PB1 -2050 -384 50 D6 1757 -2050 84 A2 639 2045

17 PB2 -2050 -517 51 D7 2045 -1750 85 A1 499 2045

18 PB3 -2050 -650 52 P10 2045 -1614 86 A0 359 2045

19 PB4 -2050 -783 53 P11 2045 -1478 87 /RD 219 2045

20 PB5 -2050 -916 54 P12 2045 -1341 88 /WR 80 2045

21 PB6 -2050 -1049 55 P13 2045 -1205 89 PZ2 -59 2045

22 P54 -2050 -1182 56 P14 2045 -1069 90 PZ3 -199 2045

23 P55 -2050 -1315 57 P15 2045 -933 91 P56 -338 2045

24 AM0 -2050 -1448 58 P16 2045 -796 92 P60 -478 2045

25 VCC -2050 -1581 59 P17 2045 -660 93 P61 -618 2045

26 X2 -1551 -2050 60 P27 2045 -524 94 P62 -757 2045

27 VSS -1330 -2050 61 P26 2045 -388 95 P63 -897 2045

28 X1 -1205 -2050 62 VSS 2045 -234 96 P64 -1037 2045

29 AM1 -1075 -2050 63 /NMI 2045 -80 97 P65 -1176 2045

30 /RESET -948 -2050 64 VCC 2045 240 98 P66 -1316 2045

31 XT1 -822 -2050 65 P25 2045 394 99 P67 -1456 2045

32 XT2 -520 -2050 66 P24 2045 530 100 VREFH -1725 2045

33 EMU0 -394 -2050 67 P23 2045 666

34 EMU1 -267 -2050 68 P22 2045 803

TMP91C824

91C824-6

2.3 Pin Names and Functions

The names of the input/output pins and their functions are described below.

Table 2.2 Pin names and functions.

Pin Name Number

of Pins I/O Functions

D0 to D7 8 I/O Data (lower): bits 0 to 7 of data bus

P10 to P17

D8 to D15

8 I/O

I/O

Port 1: I/O port that allows I/O to be selected at the bit level

(When used to the external 8bit bus)

Data (upper): bits 8 to15 of data bus

P20 to P27

A16 to A23

8 Output

Output

Port 2: Output port

Address: bits 16 to 23 of address bus

A8 to A15 8 Output Address: bits 8 to 15 of address bus

A0 to A7 8 Output Address: bits 0 to 7 of address bus

/RD 1 Output Read: strobe signal for reading external memory

/WR 1 Output Write: strobe signal for writing data to pins D0 to D7

PZ2

/HWR

1 I/O

Output

Port Z2: I/O port (with pull-up resistor)

High Write: strobe signal for writing data to pins D8 to D15

PZ3

＿＿＿＿

R/W

1 I/O

Output

Port Z3: I/O port (with pull-up resistor)

P54

/BUSRQ

1 I/O

Input

Port 54: I/O port (with pull-up resistor)

Bus Request: High-Impedance used to request Bus Release

Read/Write: 1 represents Read or Dummy cycle; 0 represents write cycle.

P55

/BUSAK

1 I/O

Output

Port 55: I/O port (with pull-up resistor)

Bus Acknowledge: signal used to acknowledge Bus Release

P56

/WAIT

1 I/O

Input

Port 56: I/O port (with pull-up resistor)

Wait: pin used to request CPU bus wait

P60

/CS0

1 Output

Output

Port 60:Output port

Chip select 0: Outputs “0” when address is within specified address area.

P61

/CS1

1 Output

Output

Port 61:Output port

Chip Select 1: outputs “0” when address is within specified address area

P62

/CS2

/CS2A

1 Output

Output

Port 62: Output port

Chip Select 2: outputs “0” when address is within specified address area

Expand Chip Select: 2A: outputs 0 when address is within specified address area

P63

/CS3

1 Output

Output

Port 63:Output port

Chip Select 3: outputs “0” when address is within specified address area

P64

EA24

/CS2B

Output

Port 64: Output port

(Address 24: Expand address)

(Expand Chip Select: 2B: outputs “0” when address is within specified address area)

P65

EA25

/CS2C

1 Output

Output

Port 65: Output port

(Address 25: Expand address)

(Expand Chip Select: 2B: outputs “0” when address is within specified address area)

P66

/CS2D

1 Output

Output

Port 66: Output port

(Expand Chip Select: 2D: outputs “0” when address is within specified address area)

P67

/CS2E

1 Output

Output

Port 67: Output port

(Expand Chip Select: 2E: outputs “0” when address is within specified address area)

TMP91C824

91C824-

Pin Name Number

of Pins I/O Functions

P70

SCK

OPTRX0

1 I/O

I/O

Input

Port 70: I/O port

Serial bus interface clock I/O data at SIO mode

Serial recive data “0”

P71

SDA

OPTTX0

1 I/O

Output

I/O

Output

Port 71: I/O port

Serial bus interface send data at SIO mode

Serial bus interface send/recive data at I2C mode

Open drain output mode by programmable (with pull up)

Serial send data “0”

P72

SCL

1 I/O

Input

I/O

Port 72I/O port

Serial bus interface recive data at SIO mode

Serial bus interface clock I/O data at I2C mode

Open drain output mode by programmable (with pull up)

P80 to P87

AN0 to AN7

/ADTRG

8 Input

Input

Port 80 to 87 port: Pin used to input ports

Analog input 0 to 7: Pin used to Input to A/D conveter

A/D trigger: Signal used to request A/D start (with used to P83)

PB0

TA0IN

1 I/O

Input

Port B0: I/O port

8bit timer 0 input: Timer 0 input

PB1

TA1OUT

1 I/O

Output

Port B1: I/O port

8bit timer 1 output: Timer 0 input or Timer 1 output

PB2

TA3OUT

1 I/O

Output

Port B2: I/O port

8bit timer 3 output: Timer 2 input or Timer 3 output

PB3

INT0

1 I/O

input

Port B0: I/O port

Interrupt request pin0: Interrupt request pin with programmable level / rising /

falling edge

PB4 to PB6

INT1 to INT3

3 I/O

input

Port B4 to B6: I/O port

Interrupt request pin1 to 3: Interrupt request pin with programmable level / rising

/falling edge

PC0

TXD0

1 I/O

Output

Port C0: I/O port

Serial 0 send data: Open drain output pin by programmable

PC1

RXD0

1 I/O

Input

Port C1: I/O port

Serial 0 recive data

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