Texas Instruments TMS320VC5501 Manuel utilisateur

TMS320VC5501/5502/5503/5507/5509/5510 DSP

Multichannel Buffered Serial Port (McBSP)

Reference Guide

Literature Number: SPRU592E

April 2005

iiiRead This First

Preface

Read This First

About This Manual

This manual describes the type of multichannel buffered serial ports (McBSP)

available on the TMS320C55x™DSPs. The McBSPs provide a direct serial

interface between a C55x™DSP and other devices in a system. For the

number of McBSPs available on a particular C55x device, see the

device-specific data manual.

Notational Conventions

This document uses the following conventions.

-When the part number TMS320VC5509 is used, it refers both to

TMS320VC5509 devices and to TMS320VC5509A devices.

-In most cases, hexadecimal numbers are shown with the suffix h. For

example, the following number is a hexadecimal 40 (decimal 64):

40h

Similarly, binary numbers often are shown with the suffix b. For example,

the following number is the decimal number 4 shown in binary form:

0100b

-If a signal or pin is active low, it has an overbar. For example, the RESET

signal is active low.

Related Documentation From Texas Instruments

The following documents describe the C55x devices and related support tools.

Copies of these documents are available on the Internet at www.ti.com.

Tip: Enter the literature number in the search box provided at www.ti.com.

TMS320VC5501 Fixed-Point Digital Signal Processor Data Manual

(literature number SPRS206) describes the features of the

TMS320VC5501 fixed-point DSP and provides signal descriptions,

pinouts, electrical specifications, and timings for the device.

Related Documentation From Texas Instruments

TMS320VC5502 Fixed-Point Digital Signal Processor Data Manual

(literature number SPRS166) describes the features of the

TMS320VC5502 fixed-point DSP and provides signal descriptions,

pinouts, electrical specifications, and timings for the device.

TMS320VC5503 Fixed-Point Digital Signal Processor Data Manual (litera-

ture number SPRS245) describes the features of the TMS320VC5503

fixed-point DSP and provides signal descriptions, pinouts, electrical

specifications, and timings for the device.

TMS320VC5507 Fixed-Point Digital Signal Processor Data Manual (litera-

ture number SPRS244) describes the features of the TMS320VC5507

fixed-point DSP and provides signal descriptions, pinouts, electrical

specifications, and timings for the device.

TMS320VC5509 Fixed-Point Digital Signal Processor Data Manual

(literature number SPRS163) describes the features of the

TMS320VC5509 fixed-point DSP and provides signal descriptions,

pinouts, electrical specifications, and timings for the device.

TMS320VC5509A Fixed-Point Digital Signal Processor Data Manual

(literature number SPRS205) describes the features of the

TMS320VC5509A fixed-point DSP and provides signal descriptions,

pinouts, electrical specifications, and timings for the device.

TMS320VC5510 Fixed-Point Digital Signal Processor Data Manual

(literature number SPRS076) describes the features of the

TMS320VC5510 fixed-point DSP and provides signal descriptions,

pinouts, electrical specifications, and timings for the device.

TMS320C55x Technical Overview (literature number SPRU393) introduces

the TMS320C55x DSPs, the latest generation of fixed-point DSPs in the

TMS320C5000™DSP platform. Like the previous generations, this

processor is optimized for high performance and low-power operation.

This book describes the CPU architecture, low-power enhancements,

and embedded emulation features.

TMS320C55x DSP CPU Reference Guide (literature number SPRU371)

describes the architecture, registers, and operation of the CPU for the

TMS320C55x DSPs.

TMS320C55x DSP Peripherals Overview Reference Guide (literature

number SPRU317) introduces the peripherals, interfaces, and related

hardware that are available on TMS320C55x DSPs.

Related Documentation From Texas Instruments

vRead This First

TMS320C55x DSP Algebraic Instruction Set Reference Guide (literature

number SPRU375) describes the TMS320C55x DSP algebraic

instructions individually. Also includes a summary of the instruction set,

a list of the instruction opcodes, and a cross-reference to the mnemonic

instruction set.

TMS320C55x DSP Mnemonic Instruction Set Reference Guide (literature

number SPRU374) describes the TMS320C55x DSP mnemonic

instructions individually. Also includes a summary of the instruction set,

a list of the instruction opcodes, and a cross-reference to the algebraic

instruction set.

TMS320C55x Optimizing C/C++ Compiler User’s Guide (literature number

SPRU281) describes the TMS320C55x C/C++ Compiler. This C/C++

compiler accepts ISO standard C and C++ source code and produces

assembly language source code for TMS320C55x devices.

TMS320C55x Assembly Language Tools User’s Guide (literature number

SPRU280) describes the assembly language tools (assembler, linker,

and other tools used to develop assembly language code), assembler

directives, macros, common object file format, and symbolic debugging

directives for TMS320C55x devices.

TMS320C55x DSP Programmer’s Guide (literature number SPRU376)

describes ways to optimize C and assembly code for the TMS320C55x

DSPs and explains how to write code that uses special features and

instructions of the DSPs.

Trademarks

TMS320C5000, TMS320C55x, and C55x are trademarks of

Texas Instruments.

Other trademarks are the property of their respective owners.

Related Documentation From Texas Instruments / Trademarks

This page is intentionally left blank.

Contents

vii

Contents

1 Introduction to the McBSP 1-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.1 Introduction 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.2 Key Features of the McBSP 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.3 Block Diagram of the McBSP 1-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.4 McBSP Pins 1-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2 McBSP Operation 2-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1 Data Transfer Process of a McBSP 2-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.1 Data Transfer Process for Word Length of 8, 12, or 16 Bits 2-2. . . . . . . . . . . . . . . .

2.1.2 Data Transfer Process for Word Length of 20, 24, or 32 Bits 2-3. . . . . . . . . . . . . .

2.2 Companding (Compressing and Expanding) Data 2-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.1 Companding Formats 2-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.2 Capability to Compand Internal Data 2-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.3 Reversing Bit Order: Option to Transfer LSB First 2-6. . . . . . . . . . . . . . . . . . . . . . . .

2.3 Clocking and Framing Data 2-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3.1 Clocking 2-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3.2 Serial Words 2-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3.3 Frames and Frame Synchronization 2-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3.4 Detecting Frame-Sync Pulses, Even in the Reset State 2-9. . . . . . . . . . . . . . . . . . .

2.3.5 Ignoring Unexpected Frame-Sync Pulses 2-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3.6 Frame Frequency 2-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3.7 Maximum Frame Frequency 2-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.4 Frame Phases 2-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.4.1 Number of Phases, Words, and Bits Per Frame 2-11. . . . . . . . . . . . . . . . . . . . . . . .

2.4.2 Single-Phase Frame Example 2-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.4.3 Dual-Phase Frame Example 2-12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.4.4 Implementing the AC97 Standard With a Dual-Phase Frame 2-13. . . . . . . . . . . . .

2.5 McBSP Reception 2-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.6 McBSP Transmission 2-17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.7 Interrupts and DMA Events Generated by a McBSP 2-19. . . . . . . . . . . . . . . . . . . . . . . . . . . .

3 Sample Rate Generator of the McBSP 3-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.1 Sample Rate Generator 3-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2 Clock Generation in the Sample Rate Generator 3-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2.1 Choosing an Input Clock 3-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2.2 Choosing a Polarity for the Input Clock 3-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Contents

viii

3.2.3 Choosing a Frequency for the Output Clock (CLKG) 3-7. . . . . . . . . . . . . . . . . . . . .

3.2.4 Keeping CLKG Synchronized to an External Input Clock 3-8. . . . . . . . . . . . . . . . . .

3.3 Frame Sync Generation in the Sample Rate Generator 3-9. . . . . . . . . . . . . . . . . . . . . . . . . .

3.3.1 Choosing the Width of the Frame-Sync Pulse on FSG 3-9. . . . . . . . . . . . . . . . . . . .

3.3.2 Controlling the Period Between the Starting Edges of Frame-Sync Pulses on . . .

FSG 3-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.4 Synchronizing Sample Rate Generator Outputs to an External Clock 3-10. . . . . . . . . . . . .

3.4.1 Synchronization Examples 3-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.5 Reset and Initialization Procedure for the Sample Rate Generator 3-12. . . . . . . . . . . . . . . .

3.6 Sample Rate Generator Clocking Examples 3-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.6.1 Double-Rate ST-Bus Clock 3-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.6.2 Single-Rate ST-Bus Clock 3-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.6.3 Other Double-Rate Clock 3-16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4 McBSP Exception/Error Conditions 4-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.1 McBSP Exception/Error Conditions 4-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.2 Overrun in the Receiver 4-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.2.1 Example of the Overrun Condition 4-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.2.2 Example of Preventing the Overrun Condition 4-4. . . . . . . . . . . . . . . . . . . . . . . . . . .

4.3 Unexpected Receive Frame-Sync Pulse 4-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.3.1 Possible Responses to Receive Frame-Sync Pulses 4-5. . . . . . . . . . . . . . . . . . . . .

4.3.2 Example of an Unexpected Receive Frame-Sync Pulse 4-6. . . . . . . . . . . . . . . . . .

4.3.3 Preventing Unexpected Receive Frame-Sync Pulses 4-7. . . . . . . . . . . . . . . . . . . . .

4.4 Overwrite in the Transmitter 4-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.4.1 Example of the Overwrite Condition 4-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.4.2 Preventing Overwrites 4-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.5 Underflow in the Transmitter 4-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.5.1 Example of the Underflow Condition 4-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.5.2 Example of Preventing the Underflow Condition 4-10. . . . . . . . . . . . . . . . . . . . . . . .

4.6 Unexpected Transmit Frame-Sync Pulse 4-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.6.1 Possible Responses to Transmit Frame-Sync Pulses 4-11. . . . . . . . . . . . . . . . . . . .

4.6.2 Example of an Unexpected Transmit Frame-Sync Pulse 4-12. . . . . . . . . . . . . . . . .

4.6.3 Preventing Unexpected Transmit Frame-Sync Pulses 4-13. . . . . . . . . . . . . . . . . . .

5 Multichannel Selection Modes 5-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.1 Channels, Blocks, and Partitions 5-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.2 Multichannel Selection 5-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.3 Configuring a Frame for Multichannel Selection 5-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.4 Using Two Partitions 5-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.4.1 Assigning Blocks to Partitions A and B 5-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.4.2 Reassigning Blocks During Reception/Transmission 5-6. . . . . . . . . . . . . . . . . . . . .

5.5 Using Eight Partitions 5-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.6 Receive Multichannel Selection Mode 5-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.7 Transmit Multichannel Selection Mode 5-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Contents

ixContents

5.7.1 Disabling/Enabling Versus Masking/Unmasking 5-12. . . . . . . . . . . . . . . . . . . . . . . .

5.7.2 Activity on McBSP Pins for Different Values of XMCM 5-13. . . . . . . . . . . . . . . . . . .

5.8 Using Interrupts Between Block Transfers 5-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6 SPI Operation Using the Clock Stop Mode 6-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.1 SPI Protocol 6-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.2 Clock Stop Mode 6-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.3 Bits Used to Enable and Configure the Clock Stop Mode 6-4. . . . . . . . . . . . . . . . . . . . . . . . .

6.4 Clock Stop Mode Timing Diagrams 6-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.5 Procedure for Configuring a McBSP for SPI Operation 6-8. . . . . . . . . . . . . . . . . . . . . . . . . . .

6.6 McBSP as the SPI Master 6-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.7 McBSP as an SPI Slave 6-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7 Receiver Configuration 7-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.1 Configuring the McBSP Receiver 7-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.2 Programming McBSP Registers for Desired Receiver Operation 7-3. . . . . . . . . . . . . . . . . .

7.3 Resetting and Enabling the Receiver 7-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.3.1 Reset Considerations 7-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.4 Setting the Receiver Pins to Operate as McBSP Pins 7-6. . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.5 Enabling/Disabling the Digital Loopback Mode 7-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.5.1 About the Digital Loopback Mode 7-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.6 Enabling/Disabling the Clock Stop Mode 7-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.6.1 About the Clock Stop Mode 7-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.7 Enabling/Disabling the Receive Multichannel Selection Mode 7-9. . . . . . . . . . . . . . . . . . . . .

7.8 Choosing One or Two Phases for the Receive Frame 7-10. . . . . . . . . . . . . . . . . . . . . . . . . .

7.9 Setting the Receive Word Length(s) 7-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.9.1 About the Word Length Bits 7-12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.10 Setting the Receive Frame Length 7-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.10.1 About the Selected Frame Length 7-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.11 Enabling/Disabling the Receive Frame-Sync Ignore Function 7-15. . . . . . . . . . . . . . . . . . . .

7.11.1 About Unexpected Frame-Sync Pulses and the Frame-Sync Ignore

Function 7-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.12 Setting the Receive Companding Mode 7-16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.13 Setting the Receive Data Delay 7-17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.13.1 About the Data Delay 7-17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.13.2 0-Bit Data Delay 7-18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.13.3 2-Bit Data Delay 7-18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.14 Setting the Receive Sign-Extension and Justification Mode 7-20. . . . . . . . . . . . . . . . . . . . . .

7.14.1 About the Sign Extension and the Justification 7-20. . . . . . . . . . . . . . . . . . . . . . . . .

7.15 Setting the Receive Interrupt Mode 7-22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.15.1 About the Receive Interrupt and the Associated Modes 7-22. . . . . . . . . . . . . . . . . .

7.16 Setting the Receive Frame-Sync Mode 7-23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.16.1 About the Receive Frame-Sync Modes 7-25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.17 Setting the Receive Frame-Sync Polarity 7-26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Contents

7.17.1 About Frame Sync Pulses, Clock Signals, and Their Polarities 7-26. . . . . . . . . . .

7.18 Setting the SRG Frame-Sync Period and Pulse Width 7-29. . . . . . . . . . . . . . . . . . . . . . . . . .

7.18.1 About the Frame-Sync Period and the Frame-Sync Pulse Width 7-30. . . . . . . . . .

7.19 Setting the Receive Clock Mode 7-31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.19.1 Selecting a Source for the Receive Clock and a Data Direction for the

CLKR Pin 7-32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.20 Setting the Receive Clock Polarity 7-34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.20.1 About Frame Sync Pulses, Clock Signals, and Their Polarities 7-34. . . . . . . . . . .

7.21 Setting the SRG Clock Divide-Down Value 7-37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.21.1 About the Sample Rate Generator Clock Divider 7-37. . . . . . . . . . . . . . . . . . . . . . . .

7.22 Setting the SRG Clock Synchronization Mode 7-39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.23 Setting the SRG Clock Mode (Choosing an Input Clock) 7-40. . . . . . . . . . . . . . . . . . . . . . . .

7.23.1 About the SRG Clock Mode 7-40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.24 Setting the SRG Input Clock Polarity 7-41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.24.1 Using CLKSP/CLKXP/CLKRP to Choose an Input Clock Polarity 7-42. . . . . . . . .

8 Transmitter Configuration 8-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.1 Configuring the Transmitter 8-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.2 Programming McBSP Registers for Desired Transmitter Operation 8-3. . . . . . . . . . . . . . . .

8.3 Resetting and Enabling the Transmitter 8-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.3.1 Reset Considerations 8-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.4 Setting the Transmitter Pins to Operate as McBSP Pins 8-6. . . . . . . . . . . . . . . . . . . . . . . . .

8.5 Enabling/Disabling the Digital Loopback Mode 8-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.5.1 About the Digital Loopback Mode 8-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.6 Enabling/Disabling the Clock Stop Mode 8-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.6.1 About the Clock Stop Mode 8-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.7 Enabling/Disabling Transmit Multichannel Selection 8-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.8 Choosing One or Two Phases for the Transmit Frame 8-10. . . . . . . . . . . . . . . . . . . . . . . . . .

8.9 Setting the Transmit Word Length(s) 8-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.9.1 About the Word Length Bits 8-12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.10 Setting the Transmit Frame Length 8-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.10.1 About the Selected Frame Length 8-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.11 Enabling/Disabling the Transmit Frame-Sync Ignore Function 8-15. . . . . . . . . . . . . . . . . . .

8.11.1 About Unexpected Frame-Sync Pulses and the Frame-Sync Ignore

Function 8-15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.12 Setting the Transmit Companding Mode 8-16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.13 Setting the Transmit Data Delay 8-17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.13.1 About the Data Delay 8-17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.13.2 0-Bit Data Delay 8-18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.13.3 2-Bit Data Delay 8-18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.14 Setting the Transmit DXENA Mode 8-20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.14.1 About the DXENA Mode 8-20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.15 Setting the Transmit Interrupt Mode 8-21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.15.1 About the Transmitter Interrupt and the Associated Modes 8-21. . . . . . . . . . . . . . .

Contents

xiContents

8.16 Setting the Transmit Frame-Sync Mode 8-22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.16.1 About the Transmit Frame-Sync Modes 8-22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.16.2 Other Considerations 8-23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.17 Setting the Transmit Frame-Sync Polarity 8-24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.17.1 About Frame Sync Pulses, Clock Signals, and Their Polarities 8-24. . . . . . . . . . .

8.18 Setting the SRG Frame-Sync Period and Pulse Width 8-27. . . . . . . . . . . . . . . . . . . . . . . . . .

8.18.1 About the Frame-Sync Period and the Frame-Sync Pulse Width 8-27. . . . . . . . . .

8.19 Setting the Transmit Clock Mode 8-29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.19.1 Selecting a Source for the Transmit Clock and a Data Direction for the

CLKX Pin 8-29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.19.2 Other Considerations 8-30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.20 Setting the Transmit Clock Polarity 8-31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.20.1 About Frame Sync Pulses, Clock Signals, and Their Polarities 8-31. . . . . . . . . . .

8.21 Setting the SRG Clock Divide-Down Value 8-34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.21.1 About the Sample Rate Generator Clock Divider 8-34. . . . . . . . . . . . . . . . . . . . . . . .

8.22 Setting the SRG Clock Synchronization Mode 8-36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.23 Setting the SRG Clock Mode (Choosing an Input Clock) 8-37. . . . . . . . . . . . . . . . . . . . . . . .

8.23.1 About the SRG Clock Mode 8-37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.24 Setting the SRG Input Clock Polarity 8-38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.24.1 Using CLKSP/CLKXP/CLKRP to Choose an Input Clock Polarity 8-39. . . . . . . . .

9 General-Purpose I/O on the McBSP Pins 9-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9.1 Using the McBSP Pins for GPIO 9-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10 Emulation, Power, and Reset Considerations 10-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10.1 McBSP Emulation Mode 10-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10.2 McBSP Power Management on the TMS320VC5503/5507/5509 and

TMS320VC5510 Devices 10-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10.3 McBSP Power Management on the TMS320VC5501 and

TMS320VC5502 Devices 10-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10.4 Resetting and Initializing a McBSP 10-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10.4.1 McBSP Pin States: DSP Reset Versus Receiver/Transmitter Reset 10-5. . . . . . .

10.4.2 DSP Reset, McBSP Reset, and Sample Rate Generator Reset 10-5. . . . . . . . . . .

10.4.3 McBSP Initialization Procedure 10-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10.4.4 Resetting the Transmitter While the Receiver is Running 10-8. . . . . . . . . . . . . . . .

11 Data Packing Examples 11-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

11.1 Data Packing Using Frame Length and Word Length 11-2. . . . . . . . . . . . . . . . . . . . . . . . . . .

11.2 Data Packing Using Word Length and the Frame-Sync Ignore Function 11-4. . . . . . . . . . .

12 McBSP Registers 12-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.1 Data Receive Registers (DRR1 and DRR2) 12-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.1.1 How Data Travels From the Data Receive (DR) Pin to the DRRs 12-2. . . . . . . . . .

12.2 Data Transmit Registers (DXR1 and DXR2) 12-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

12.2.1 How Data Travels From the DXRs to the Data Transmit (DX) Pin 12-3. . . . . . . . .

12.3 Serial Port Control Registers (SPCR1 and SPCR2) 12-4. . . . . . . . . . . . . . . . . . . . . . . . . . . .

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