Texas Instruments TMS320DM648 Manuel utilisateur

TMS320DM647/DM648

Video Port/VCXO Interpolated Control (VIC)Port

User's Guide

Literature Number: SPRUEM1

May 2007

2 SPRUEM1 – May 2007Submit Documentation Feedback

Contents
Preface .............................................................................................................................. 13
1 Overview ................................................................................................................. 161.1 Video Port ................................................................................................................ 171.2 Video Port FIFO ......................................................................................................... 191.2.1 EDMA Interface ................................................................................................. 191.2.2 Video Capture FIFO Configurations .......................................................................... 201.2.3 Video Display FIFO Configurations .......................................................................... 231.3 Video Port Registers .................................................................................................. 251.4 Video Port Pin Mapping .............................................................................................. 261.4.1 VDIN Bus Usage for Capture Modes ........................................................................ 271.4.2 VDOUT Data Bus Usage for Display Modes ................................................................ 281.5 Video Port Pin Multiplexing ........................................................................................ 281.6 VideoPort Clocking .................................................................................................... 28
2 Video Port ............................................................................................................... 292.1 Reset Operation ........................................................................................................ 302.1.1 Power-On Reset ................................................................................................ 302.1.2 Peripheral Bus Reset .......................................................................................... 302.1.3 Software Port Reset ............................................................................................ 302.1.4 Capture Channel Reset ........................................................................................ 312.1.5 Display Channel Reset......................................................................................... 312.2 Interrupt Operation .................................................................................................... 312.3 EDMA Operation ........................................................................................................ 322.3.1 Capture EDMA Event Generation ............................................................................ 322.3.2 Display EDMA Event Generation ............................................................................. 332.3.3 EDMA Size and Threshold Restrictions ..................................................................... 332.3.4 EDMA Interface Operation .................................................................................... 342.4 Video Port Control Registers ...................................................................................... 342.4.1 Video Port Control Register (VPCTL) ........................................................................ 352.4.2 Video Port Status Register (VPSTAT) ....................................................................... 372.4.3 Video Port Interrupt Enable Register (VPIE) ................................................................ 382.4.4 Video Port Interrupt Status Register (VPIS) ................................................................ 40
3 Video Capture Port ................................................................................................... 453.1 Video Capture Mode Selection .................................................................................... 463.2 BT.656 Video Capture Mode ........................................................................................ 463.2.1 BT.656 Capture Channels ..................................................................................... 463.2.2 BT.656 Timing Reference Codes ............................................................................. 463.2.3 BT.656 Image Window and Capture ......................................................................... 483.2.4 BT.656 Data Sampling ......................................................................................... 493.2.5 BT.656 FIFO Packing .......................................................................................... 493.3 Y/C Video Capture Mode ............................................................................................ 503.3.1 Y/C Capture Channels ......................................................................................... 503.3.2 Y/C Timing Reference Codes ................................................................................. 50
SPRUEM1 – May 2007 Table of Contents 3Submit Documentation Feedback

3.3.3 Y/C Image Window and Capture ............................................................................. 503.3.4 Y/C FIFO Packing .............................................................................................. 513.4 BT.656 and Y/C Mode Field and Frame Operation .......................................................... 513.4.1 Capture Determination and Notification ..................................................................... 523.4.2 Vertical Synchronization ....................................................................................... 533.4.3 Horizontal Synchronization .................................................................................... 553.4.4 Field Identification .............................................................................................. 563.4.5 Short and Long Field Detect .................................................................................. 573.5 Video Input Filtering .................................................................................................. 573.5.1 Input Filter Modes .............................................................................................. 583.5.2 Chrominance Re-sampling Operation ....................................................................... 583.5.3 Scaling Operation ............................................................................................... 583.5.4 Edge Pixel Replication ......................................................................................... 593.6 Ancillary Data Capture ............................................................................................... 603.6.1 Horizontal Ancillary (HANC) Data Capture .................................................................. 613.6.2 Vertical Ancillary (VANC) Data Capture ..................................................................... 613.7 Raw Data Capture Mode ............................................................................................. 613.7.1 Raw Data Capture Notification ................................................................................ 613.7.2 Raw Data FIFO Packing ....................................................................................... 623.8 TCI Capture Mode ...................................................................................................... 633.8.1 TCI Capture Features .......................................................................................... 633.8.2 TCI Data Capture ............................................................................................... 633.8.3 TCI Capture Error Detection .................................................................................. 643.8.4 Synchronizing the System Clock ............................................................................. 643.8.5 TCI Data Capture Notification ................................................................................. 653.8.6 Writing to the FIFO ............................................................................................. 663.8.7 Reading from the FIFO ........................................................................................ 663.9 Capture Line Boundary Conditions .............................................................................. 673.10 Capturing Video in BT.656 or Y/C Mode ....................................................................... 673.10.1 Handling FIFO Overrun in BT.656 or Y/C Mode .......................................................... 683.11 Capturing Video in Raw Data Mode ............................................................................. 683.11.1 Handling FIFO Overrun Condition in Raw Data Mode ................................................... 693.12 Capturing Data in TCI Capture Mode ............................................................................ 693.12.1 Handling FIFO Overrun Condition in TCI Capture Mode ................................................. 703.13 Video Capture Registers ............................................................................................ 703.13.1 Video Capture Channel x Status Register (VCASTAT, VCBSTAT) .................................... 713.13.2 Video Capture Channel A Control Register (VCACTL) ................................................... 723.13.3 Video Capture Channel x Field 1 Start Register (VCxSTRT1) .......................................... 753.13.4 Video Capture Channel x Field 1 Stop Register (VCxSTOP1) .......................................... 763.13.5 Video Capture Channel x Field 2 Start Register (VCxSTRT2) .......................................... 773.13.6 Video Capture Channel x Field 2 Stop Register (VC xSTOP2) .......................................... 783.13.7 Video Capture Channel x Vertical Interrupt Register (VCxVINT) ....................................... 793.13.8 Video Capture Channel x Threshold Register (VCATHRLD, VCBTHRLD) ............................ 803.13.9 Video Capture Channel x Event Count Register (VCxEVTCT) .......................................... 813.13.10 Video Capture Channel B Control Register (VCBCTL) ................................................. 813.13.11 TCI Capture Control Register (TCICTL) .................................................................. 843.13.12 TCI Clock Initialization LSB Register (TCICLKINITL) ................................................... 853.13.13 TCI Clock Initialization MSB Register (TCICLKINITM) .................................................. 86
4Contents SPRUEM1 – May 2007Submit Documentation Feedback

3.13.14 TCI System Time Clock LSB Register (TCISTCLKL) ................................................... 863.13.15 TCI System Time Clock MSB Register (TCISTCLKM) .................................................. 873.13.16 TCI System Time Clock Compare LSB Register (TCISTCMPL) ...................................... 883.13.17 TCI System Time Clock Compare MSB Register (TCISTCMPM) ..................................... 883.13.18 TCI System Time Clock Compare Mask LSB Register (TCISTMSKL) ............................... 893.13.19 TCI System Time Clock Compare Mask MSB Register (TCISTMSKM) .............................. 893.13.20 TCI System Time Clock Ticks Interrupt Register (TCITICKS) ......................................... 903.14 Video Capture FIFO Registers ..................................................................................... 91
4 Video Display Port .................................................................................................... 924.1 Video Display Mode Selection ..................................................................................... 934.1.1 Image Timing .................................................................................................... 934.1.2 Video Display Counters ........................................................................................ 964.1.3 Sync Signal Generation ........................................................................................ 984.1.4 External Sync Operation ....................................................................................... 984.1.5 Port Sync Operation ............................................................................................ 984.2 BT.656 Video Display Mode ........................................................................................ 984.2.1 Display Timing Reference Codes ............................................................................ 994.2.2 Blanking Codes ................................................................................................ 1014.2.3 BT.656 Image Display ........................................................................................ 1014.2.4 BT.656 FIFO Unpacking ..................................................................................... 1014.3 Y/C Video Display Mode ........................................................................................... 1024.3.1 Y/C Display Timing Reference Codes ...................................................................... 1024.3.2 Y/C Blanking Codes .......................................................................................... 1024.3.3 Y/C Image Display ............................................................................................ 1024.3.4 Y/C FIFO Unpacking .......................................................................................... 1034.4 Video Output Filtering .............................................................................................. 1034.4.1 Output Filter Modes ........................................................................................... 1034.4.2 Chrominance Re-sampling Operation ...................................................................... 1044.4.3 Scaling Operation ............................................................................................. 1044.4.4 Edge Pixel Replication ....................................................................................... 1054.5 Ancillary Data Display .............................................................................................. 1064.5.1 Horizontal Ancillary (HANC) Data Display ................................................................. 1064.5.2 Vertical Ancillary (VANC) Data Display .................................................................... 1064.6 Raw Data Display Mode ............................................................................................ 1064.6.1 Raw Mode RGB Output Support ............................................................................ 1074.6.2 Raw Data FIFO Unpacking .................................................................................. 1074.7 Video Display Field and Frame Operation ................................................................... 1084.7.1 Display Determination and Notification ..................................................................... 1084.7.2 Video Display Event Generation ............................................................................ 1094.8 Display Line Boundary Conditions ............................................................................. 1094.9 Display Timing Examples ......................................................................................... 1104.9.1 Interlaced BT.656 Timing Example ......................................................................... 1104.9.2 Interlaced Raw Display Example ............................................................................ 1134.9.3 Y/C Progressive Display Example .......................................................................... 1164.10 Displaying Video in BT.656 or Y/C Mode ..................................................................... 1194.11 Displaying Video in Raw Data Mode ........................................................................... 1204.11.1 Handling Under-run Condition of the Display FIFO ..................................................... 121
SPRUEM1 – May 2007 Contents 5Submit Documentation Feedback

12 Video Display Registers ........................................................................................... 1224.12.1 Video Display Status Register (VDSTAT) ................................................................ 1224.12.2 Video Display Control Register (VDCTL) ................................................................. 1234.12.3 Video Display Frame Size Register (VDFRMSZ) ........................................................ 1274.12.4 Video Display Horizontal Blanking Register (VDHBLNK) ............................................... 1274.12.5 Video Display Field 1 Vertical Blanking Start Register (VDVBLKS1) ................................. 1284.12.6 Video Display Field 1 Vertical Blanking End Register (VDVBLKE1) .................................. 1294.12.7 Video Display Field 2 Vertical Blanking Start Register (VDVBLKS2) ................................. 1304.12.8 Video Display Field 2 Vertical Blanking End Register (VDVBLKE2) .................................. 1314.12.9 Video Display Field 1 Image Offset Register (VDIMGOFF1) .......................................... 1324.12.10 Video Display Field 1 Image Size Register (VDIMGSZ1) ............................................. 1334.12.11 Video Display Field 2 Image Offset Register (VDIMGOFF2) ......................................... 1344.12.12 Video Display Field 2 Image Size Register (VDIMGSZ2) ............................................. 1354.12.13 Video Display Field 1 Timing Register (VDFLDT1) .................................................... 1354.12.14 Video Display Field 2 Timing Register (VDFLDT2) .................................................... 1364.12.15 Video Display Threshold Register (VDTHRLD) ........................................................ 1374.12.16 Video Display Horizontal Synchronization Register (VDHSYNC) .................................... 1384.12.17 Video Display Field 1 Vertical Synchronization Start Register (VDVSYNS1) ...................... 1384.12.18 Video Display Field 1 Vertical Synchronization End Register (VDVSYNE1) ....................... 1394.12.19 Video Display Field 2 Vertical Synchronization Start Register (VDVSYNS2) ...................... 1404.12.20 Video Display Field 2 Vertical Synchronization End Register (VDVSYNE2) ....................... 1404.12.21 Video Display Counter Reload Register (VDRELOAD) ............................................... 1414.12.22 Video Display Event Register (VDDISPEVT) ........................................................... 1424.12.23 Video Display Clipping Register (VDCLIP) .............................................................. 1424.12.24 Video Display Default Display Value Register (VDDEFVAL) ......................................... 1434.12.25 Video Display Vertical Interrupt Register (VDVINT) ................................................... 1444.12.26 Video Display Field Bit Register (VDFBIT) .............................................................. 1454.12.27 Video Display Field 1 Vertical Blanking Bit Register (VDVBIT1) ..................................... 1464.12.28 Video Display Field 2 Vertical Blanking Bit Register (VDVBIT2) ..................................... 1474.13 Video Display Registers Recommended Values ........................................................... 1484.14 Video Display FIFO Registers .................................................................................... 149
General-Purpose I/O Operation ................................................................................. 1505.1 GPIO Registers ........................................................................................................ 1515.1.1 Video Port Peripheral Identification Register (VPPID) ................................................... 1525.1.2 Video Port Peripheral Control Register (PCR) ............................................................ 1535.1.3 Video Port Pin Function Register (PFUNC) ............................................................... 1545.1.4 Video Port Pin Direction Register (PDIR) .................................................................. 1565.1.5 Video Port Pin Data Input Register (PDIN) ................................................................ 1585.1.6 Video Port Pin Data Output Register (PDOUT) ........................................................... 1595.1.7 Video Port Pin Data Set Register (PDSET) ............................................................... 1615.1.8 Video Port Pin Data Clear Register (PDCLR) ............................................................. 1625.1.9 Video Port Pin Interrupt Enable Register (PIEN) ......................................................... 1635.1.10 Video Port Pin Interrupt Polarity Register (PIPOL) ...................................................... 1645.1.11 Video Port Pin Interrupt Status Register (PISTAT) ...................................................... 1655.1.12 Video Port Pin Interrupt Clear Register (PICLR) ......................................................... 166
VCXO Interpolated Control Port ................................................................................ 1676.1 Overview ................................................................................................................ 1686.2 Interface ................................................................................................................. 168
6Contents SPRUEM1 – May 2007Submit Documentation Feedback

6.3 Operational Details .................................................................................................. 1696.4 Enabling VIC Port .................................................................................................... 1706.5 VIC Port Registers ................................................................................................... 1706.5.1 VIC Control Register (VICCTL).............................................................................. 1716.5.2 VIC Input Register (VICIN) ................................................................................... 1726.5.3 VIC Clock Divider Register (VICDIV) ....................................................................... 173

SPRUEM1 – May 2007 Contents 7Submit Documentation Feedback

List of Figures
1-1 Video Port Block Diagram ................................................................................................. 181-2 BT.656 Video Capture FIFO Configuration ............................................................................. 201-3 8-Bit Raw Video Capture and TCI Video Capture FIFO Configuration.............................................. 211-4 Y/C Video Capture FIFO Configuration ................................................................................. 221-5 16-Bit Raw Video Capture FIFO Configuration ......................................................................... 231-6 BT.656 Video Display FIFO Configuration .............................................................................. 231-7 8-Bit Raw Video Display FIFO Configuration ........................................................................... 231-8 8-Bit Locked Raw Video Display FIFO Configuration ................................................................. 241-9 16-Bit Raw Video Display FIFO Configuration ......................................................................... 241-10 Y/C Video Display FIFO Configuration .................................................................................. 252-1 Video Port Control Register (VPCTL) ................................................................................... 352-2 Video Port Status Register (VPSTAT) ................................................................................... 372-3 Video Port Interrupt Enable Register (VPIE) ........................................................................... 382-4 Video Port Interrupt Status Register (VPIS) ............................................................................ 403-1 Video Capture Parameters ................................................................................................ 483-2 8-Bit BT.656 FIFO Packing ............................................................................................... 503-3 8-Bit Y/C FIFO Packing .................................................................................................... 513-4 VCOUNT Operation Example (EXC = 0) ................................................................................ 543-5 HCOUNT Operation Example (EXC = 0) ............................................................................... 553-6 HCOUNT Operation Example (EXC = 1) ............................................................................... 563-7 Field 1 Detection Timing................................................................................................... 573-8 Chrominance Re-sampling ................................................................................................ 583-9 1/2 Scaled Co-Sited Filtering ............................................................................................. 593-10 1/2 Scaled Chrominance Re-sampled Filtering ........................................................................ 593-11 Edge Pixel Replication ..................................................................................................... 603-12 Capture Window Not Requiring Edge Pixel Replication .............................................................. 603-13 8-Bit Raw Data FIFO Packing ............................................................................................ 623-14 16-Bit Raw Data FIFO Packing ........................................................................................... 633-15 Parallel TCI Capture ....................................................................................................... 643-16 Program Clock Reference (PCR) Header Format ..................................................................... 643-17 System Time Clock Counter Operation ................................................................................. 653-18 TCI FIFO Packing .......................................................................................................... 663-19 TCI Timestamp Format (Little Endian) .................................................................................. 663-20 Capture Line Boundary Example ......................................................................................... 673-21 Video Capture Channel x Status Register (VCxSTAT) ................................................................ 713-22 Video Capture Channel A Control Register (VCACTL) ............................................................... 733-23 Video Capture Channel x Field 1 Start Register (VCxSTRT1) ....................................................... 763-24 Video Capture Channel x Field 1 Stop Register (VCxSTOP1) ....................................................... 773-25 Video Capture Channel x Field 2 Start Register (VCxSTRT2) ....................................................... 773-26 Video Capture Channel x Field 2 Stop Register (VC xSTOP2) ....................................................... 783-27 Video Capture Channel x Vertical Interrupt Register (VCxVINT) .................................................... 793-28 Video Capture Channel x Threshold Register (VC xTHRLD) ......................................................... 803-29 Video Capture Channel x Event Count Register (VCxEVTCT) ...................................................... 813-30 Video Capture Channel B Control Register (VCBCTL) ............................................................... 823-31 TCI Capture Control Register (TCICTL) ................................................................................. 843-32 TCI Clock Initialization LSB Register (TCICLKINITL) ................................................................. 853-33 TCI Clock Initialization MSB Register (TCICLKINITM) ................................................................ 863-34 TCI System Time Clock LSB Register (TCISTCLKL) ................................................................. 873-35 TCI System Time Clock MSB Register (TCISTCLKM) ................................................................ 873-36 TCI System Time Clock Compare LSB Register (TCISTCMPL) ..................................................... 883-37 TCI System Time Clock Compare MSB Register (TCISTCMPM) ................................................... 883-38 TCI System Time Clock Compare Mask LSB Register (TCISTMSKL) .............................................. 89
8List of Figures SPRUEM1 – May 2007Submit Documentation Feedback

3-39 TCI System Time Clock Compare Mask MSB Register (TCISTMSKM) ............................................ 903-40 TCI System Time Clock Ticks Interrupt Register (TCITICKS) ........................................................ 904-1 NTSC Compatible Interlaced Display .................................................................................... 934-2 SMPTE 296M Compatible Progressive Scan Display ................................................................. 944-3 Interlaced Blanking Intervals and Video Areas ......................................................................... 954-4 Progressive Blanking Intervals and Video Area ........................................................................ 964-5 Horizontal Blanking and Horizontal Sync Timing ...................................................................... 974-6 Vertical Blanking, Sync and Even/Odd Frame Signal Timing ........................................................ 974-7 Video Display Module Synchronization Chain .......................................................................... 984-8 BT.656 Output Sequence ................................................................................................. 984-9 525/60 BT.656 Horizontal Blanking Timing ............................................................................. 994-10 625/50 BT.656 Horizontal Blanking Timing ............................................................................. 994-11 Digital Vertical F and V Transitions ..................................................................................... 1004-12 8-Bit BT.656 FIFO Unpacking ........................................................................................... 1014-13 Y/C Horizontal Blanking Timing (BT.1120 60I) ....................................................................... 1024-14 8-Bit Y/C FIFO Unpacking ............................................................................................... 1034-15 Chrominance Re-sampling .............................................................................................. 1044-16 2x Co-Sited Scaling ...................................................................................................... 1044-17 2x Interspersed Scaling .................................................................................................. 1054-18 Output Edge Pixel Replication .......................................................................................... 1054-19 Luma Edge Replication .................................................................................................. 1054-20 Interspersed Chroma Edge Replication ................................................................................ 1064-21 8-Bit Raw FIFO Unpacking .............................................................................................. 1074-22 16-Bit Raw FIFO Unpacking............................................................................................. 1074-23 8-Bit Raw FIFO Unpacking ........................................................................................... 1074-24 Display Line Boundary Example ........................................................................................ 1104-25 BT.656 Interlaced Display Horizontal Timing Example .............................................................. 1114-26 BT.656 Interlaced Display Vertical Timing Example ................................................................. 1134-27 Raw Interlaced Display Horizontal Timing Example ................................................................. 1144-28 Raw Interlaced Display Vertical Timing Example ..................................................................... 1154-29 Y/C Progressive Display Horizontal Timing Example ................................................................ 1174-30 Y/C Progressive Display Vertical Timing Example ................................................................... 1184-31 Video Display Status Register (VDSTAT) ............................................................................. 1234-32 Video Display Control Register (VDCTL) .............................................................................. 1244-33 Video Display Frame Size Register (VDFRMSZ) ..................................................................... 1274-34 Video Display Horizontal Blanking Register (VDHBLNK) ........................................................... 1284-35 Video Display Field 1 Vertical Blanking Start Register (VDVBLKS1) .............................................. 1294-36 Video Display Field 1 Vertical Blanking End Register (VDVBLKE1) ............................................... 1294-37 Video Display Field 2 Vertical Blanking Start Register (VDVBLKS2) .............................................. 1304-38 Video Display Field 2 Vertical Blanking End Register (VDVBLKE2) ............................................... 1314-39 Video Display Field 1 Image Offset Register (VDIMGOFF1) ....................................................... 1324-40 Video Display Field 1 Image Size Register (VDIMGSZ1) ........................................................... 1334-41 Video Display Field 2 Image Offset Register (VDIMGOFF2) ....................................................... 1344-42 Video Display Field 2 Image Size Register (VDIMGSZ2) ........................................................... 1354-43 Video Display Field 1 Timing Register (VDFLDT1) .................................................................. 1364-44 Video Display Field 2 Timing Register (VDFLDT2) .................................................................. 1364-45 Video Display Threshold Register (VDTHRLD) ....................................................................... 1374-46 Video Display Horizontal Synchronization Register (VDHSYNC) .................................................. 1384-47 Video Display Field 1 Vertical Synchronization Start Register (VDVSYNS1) ..................................... 1394-48 Video Display Field 1 Vertical Synchronization End Register (VDVSYNE1) ..................................... 1394-49 Video Display Field 2 Vertical Synchronization Start Register (VDVSYNS2) ..................................... 1404-50 Video Display Field 2 Vertical Synchronization End Register (VDVSYNE2) ..................................... 1414-51 Video Display Counter Reload Register (VDRELOAD) .............................................................. 141
SPRUEM1 – May 2007 List of Figures 9Submit Documentation Feedback

4-52 Video Display Event Register (VDDISPEVT) ......................................................................... 1424-53 Video Display Clipping Register (VDCLIP) ............................................................................ 1434-54 Video Display Default Display Value Register (VDDEFVAL) ....................................................... 1444-55 Video Display Default Display Value Register (VDDEFVAL) - Raw Data Mode ................................. 1444-56 Video Display Vertical Interrupt Register (VDVINT) .................................................................. 1454-57 Video Display Field Bit Register (VDFBIT) ............................................................................ 1464-58 Video Display Field 1 Vertical Blanking Bit Register (VDVBIT1) ................................................... 1464-59 Video Display Field 2 Vertical Blanking Bit Register (VDVBIT2) ................................................... 1475-1 Video Port Peripheral Identification Register (VPPID) ............................................................... 1525-2 Video Port Peripheral Control Register (PCR) ........................................................................ 1535-3 Video Port Pin Function Register (PFUNC) ........................................................................... 1545-4 Video Port Pin Direction Register (PDIR) .............................................................................. 1565-5 Video Port Pin Data Input Register (PDIN) ............................................................................ 1585-6 Video Port Pin Data Output Register (PDOUT) ....................................................................... 1595-7 Video Port Pin Data Set Register (PDSET) ........................................................................... 1615-8 Video Port Pin Data Clear Register (PDCLR) ......................................................................... 1625-9 Video Port Pin Interrupt Enable Register (PIEN) ..................................................................... 1635-10 Video Port Pin Interrupt Polarity Register (PIPOL) ................................................................... 1645-11 Video Port Pin Interrupt Status Register (PISTAT) ................................................................... 1655-12 Video Port Pin Interrupt Clear Register (PICLR) ..................................................................... 1666-1 TCI System Block Diagram .............................................................................................. 1686-2 Program Clock Reference (PCR) Header Format .................................................................... 1696-3 VIC Control Register (VICCTL) ......................................................................................... 1716-4 VIC Input Register (VICIN) .............................................................................................. 1726-5 VIC Clock Divider Register (VICDIV) ................................................................................... 173
10 List of Figures SPRUEM1 – May 2007Submit Documentation Feedback

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