Texas Instruments LMK00101BEVAL/NOPB Manuel utilisateur

SNLU098A–March 2012–Revised July 2019

LMK00101 User’s Guide

User's Guide

SNLU098A–March 2012–Revised July 2019

LMK00101 User’s Guide

This user guide describes how to set up and operate the LMK00101 evaluation board kit (EVK). The

LMK00101 is a high performance, low noise, low voltage CMOS fanout buffer. The core voltage can be

2.5 or 3.3 volts, while the power supply for the outputs can be selected from: 1.5 V, 1.8 V, 2.5 V, or 3.3 V,

provided that it does not exceed the core supply voltage .

Contents

1 Introduction ................................................................................................................... 2

2 Quick Start.................................................................................................................... 2

2.1 Quick Start Description............................................................................................. 3

3 Signal Path and Control Switches......................................................................................... 3

4 Power Supplies .............................................................................................................. 4

5 Clock Inputs .................................................................................................................. 4

5.1 Crystal Oscillator Interface......................................................................................... 4

5.2 Configuring OSCin for a Crystal Mode........................................................................... 4

6 Clock Outputs ................................................................................................................ 4

7 Schematics ................................................................................................................... 5

8 PCB Layout................................................................................................................... 7

9 Bill of Materials............................................................................................................... 9

List of Figures

1 LMK00101 Quick Start Setup.............................................................................................. 2

2 Schematic Sheet 1 .......................................................................................................... 5

3 Schematic Sheet 2 .......................................................................................................... 6

4 PCB Top ...................................................................................................................... 7

5 Bottom Side (Layer Inverted, Not to Scale) .............................................................................. 8

List of Tables

1 Part Description.............................................................................................................. 2

2 Default Clock Output Modes / Interfaces................................................................................. 3

3 Input Selection (0=SW OFF, 1=SW ON) ................................................................................. 3

4 Output Enable Selection (0=OFF, 1=ON) ................................................................................ 3

5 Power Supply Configuration................................................................................................ 4

6 Bill of Materials............................................................................................................... 9

Trademarks

All trademarks are the property of their respective owners.

Output

Power Supply

Core

Power Supply

CLKin0

DiﬀerentialSingle Ended

Oscillator Input

CLKin1

Diﬀerential

Input Select

DIP Switches

CLKout0-

CLKout5

CLKout6-

CLKout9

Introduction

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2SNLU098A–March 2012–Revised July 2019

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LMK00101 User’s Guide

1 Introduction

This user guide describes how to set up and operate the LMK00101 evaluation board kit (EVK). The

LMK00101 is a high performance, low noise, low voltage CMOS fanout buffer. The core voltage can be

2.5 or 3.3 volts, while the power supply for the outputs can be selected from: 1.5 V, 1.8 V, 2.5 V, or 3.3 V,

provided that it does not exceed the core supply voltage .

Table 1. Part Description

BUFFER IC PACKAGE

U1 LMK00101 LLP-32

2 Quick Start

Figure 1. LMK00101 Quick Start Setup

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Quick Start

SNLU098A–March 2012–Revised July 2019

LMK00101 User’s Guide

2.1 Quick Start Description

The LMK00101 EVK allows full verification of the device functionality and performance specifications. To

quickly set up and operate the board with basic equipment, refer to the quick start procedure below and

test setup shown in Figure 1.

1. Verify the output mode control switches, S1[1:4], match the states shown in Table 2 to reflect the

default output clock interfaces configured on the EVK.

Table 2. Default Clock Output Modes / Interfaces

SW POSITION/NAME SW STATE

S1[1] / SEL1 0 (OFF)

S1[2] / SEL0 1 (ON)

S1[3] / OE 1 (OFF)

S1[4] / NC Unused

2. Connect the Vdd SMA from the board to a 3.3 V source. This powers the non-output portions of the

LMK00101.

3. Connect the Vdd CLKout SMA from the board to a 3.3 V source. This powers the output drivers of the

LMK00101.

4. Set the desired clock input using the input selection control switches, S1[1:2], per Table 3. A

differential clock source can be connected to SMAs CLKin0/0* or CLKin1/1*.

Note: CLKin0/0* and CLKin1/1* paths are configured by default to receive a differential clock as the

input. The SMA inputs are DC coupled to the device inputs and terminated with 100 Ωdifferential.

Refer to the Clock Inputs section to configure the EVK for a single-ended input.

Table 3. Input Selection (0=SW OFF, 1=SW ON)

SELECTED INPUT DEFAULT INPUT MODE S1[1]CLKin_Sel0 State S1[2] CLKin_Sel1 State

CLKin0/0* Differential clock 0 0

CLKin1/1* Differential clock 0 1

OSCin Select OSCin 1 Don't Care

5. Connect and measure any clock output SMA labeled CLKoutX to an oscilloscope or other test

instrument using SMA cable(s). The output clock will be level-translated/buffered copy of the selected

clock input or crystal oscillator. Note: All output clocks are AC-coupled to the SMA connectors to

ensure safe use with RF instruments.

Note: Switching noise from one or more un-terminated outputs may impair the signal quality of the

measured output(s). To minimize switching noise and EMI, properly terminate any unused output path

using an SMA load or the component options near the SMA outputs, or alternatively, remove the 0 Ω

series resistor nearest the unused output pin.

3 Signal Path and Control Switches

The LMK00101 supports single-ended or differential clocks on CLKin0 and CLKin1. A third input, OSCin,

has an integrated crystal oscillator interface that supports a fundamental mode, AT-cut crystal or an

external single-ended clock. The three-input multiplexer is pin-controlled. To achieve the maximum

operating frequency and lowest additive jitter, it is recommended to use a differential clock with high input

slew rate (>1 V/ns) and DC-coupling to either CLKin0 or CLKin1 port.

All control pins are configured with the control switch, S3. The output enable logic is shown in Table 4.

Table 4. Output Enable Selection (0=OFF, 1=ON)

CLKout ENABLE MODE S1[3]-OE

Disabled/Hi-Z 0

Enabled 1

Power Supplies

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LMK00101 User’s Guide

4 Power Supplies

By default, Vdd and VddCLKout are supplied by two external power supplies. To modify the EVK with a

different power supply configuration, populate the resistor options as shown in Table 5.Then, apply the

appropriate voltage(s) to the EVK power input(s).

Decoupling capacitors and 0 Ωresistor footprints, which can accommodate ferrite beads, can be used to

isolate the EVK power input(s) from the device power pins. Do not disconnect or ground any of the

VddCLKout pins as they are all internally connected inside the device.

Table 5. Power Supply Configuration

DUAL EXTERNAL INPUTS (DEFAULT) SINGLE EXTERNAL INPUT 3.3 V

Vdd input Apply 3.3 V Apply 3.3 V ± 5%

VddCLKout input Apply Voltage ≤Vdd Not used

R38 0 ΩDNP

R39 0 Ω0Ω

R43 DNP 0 Ω

5 Clock Inputs

The SMA inputs labeled CLKin0 & CLKin0* and CLKin1 & CLKin1* are configured to receive a differential

clock or single ended clock. Best performance is achieved with DC-coupled differential input clock.

5.1 Crystal Oscillator Interface

The LMK00101 has an integrated crystal oscillator interface (OSCin/OSCout) that supports a fundamental

mode, AT-cut crystal. If the crystal input is selected, an optional onboard crystal on either footprint Y1 or

Y2 will start-up and the oscillator clock can be measured on any enabled output.

A crystal with the HC49 footprint can be populated on the bottom side of the PCB. Alternatively, a 3.2 x

2.5 mm crystal can be populated on Y2, located on the top side. Only one crystal footprint should be used

at a time.

The values of C42 and C25(CEXT) depend on the load capacitance (CL) specified for the crystal. The OSC

input capacitance (CIN) of the device is 1 pF differential, and the trace capacitance (CTRACE) of OSCin and

OSCout is around 1 pF. If the selected crystal is specified for CLof 18 pF, the CEXT is calculated as

follows:

CEXT= (CL–CIN–CTRACE/2) * 2 (1)

CEXT= (18 pF –1 pF –1 pF/2) * 2 (2)

CEXT= 33 pF (3)

5.2 Configuring OSCin for a Crystal Mode

To configure the board to use crystal mode remove C26 to disconnect the OSCin Port. Install 0 Ωresistors

on R33 and R34. Install a crystal in either footprint (Y1 or Y2) and install the proper load capacitors in C24

and C25.

6 Clock Outputs

All clock outputs are LVCMOS. In the case that not all outputs are used, any unused outputs should be

left floating.

1 2

LMK00101 Main Schematic

3/20/2012

LMK0101ENG_Sheet2.SchDoc

Sheet Title:

Size: Schematic:

Mod. Date:

File:

Rev:

Sheet: of

Texas Instruments and/or its licensors do not warrant the accur acy or completeness of this

speciﬁcation or any information contained therein. Texas Instruments and/or its licensors do not

warrant that this design will meet the speciﬁcations, will be suitable for your application or ﬁt for

any particular purpose, or will operate in an implementation. T

exas Instruments and/or its

licensors do not warrant that the design is production worthy. You should completely validate

and test your design implementation to conﬁrm the system funct ionality for your application. http://www.ti.com

Contact: http://www.national.com/support

LMK00101 EVK

Project:

Designe d for: Public Release

870600680 X1

Assemb ly Va riant: Customer

CLKin1*

142-0701-851

CLKin1

142-0701-851

CLKin0*

142-0701-851

CLKin0

142-0701-851

GND

100

GND

100

R14

GND

DNP 51

DNP

R13

DNP 51

R12

DNP

0.1uF

R10

0.1uF

R11

R27

DNP

R26

DNP

R24

DNP

R25

DNP

R23

DNP

R18

DNP

R19

DNP

VCCO

GND

VCC

VCCO

5.6pF

C24

DNP

5.6pF

C25

DNP

R34

DNP

R33

DNP

OSCin

142-0701-851

0.1 F

C26

R16

GND

40 MHz

DNP

R15

R17

GND

C22

C23

C20

C21

C0_N

C0_P

DNP

VddCLKout

CLKout1

GND

CLKout2

VddCLKout

CLKout3

CLKout4

CLKout0

Vdd 10

OSCin 11

OSCout 12

CLKin0 13

CLKin0* 14

GND 15

GND 16

GND 9

CLKout6 18

VddCLKout 19

CLKout7 20

GND 21

CLKout8 22

VddCLKout 23

CLKout9 24

CLKout5 17

GND`

CLKin1*

CLKin1

SEL1

SEL0

GND

DAP

LMK00101

GND

R22

DNP

R21

DNP

R20

DNP

0.1 F

C32

0.1 F

C33

0.1 F

C34

0.1 F

C36

0.1 F

C35

GND

CLKout7

142-0701-851

GND

CLKout6

142-0701-851

CLKout5

142-0701-851

GND

CLKout9

142-0701-851

CLKout8

142-0701-851

GND

0.1 F

C28

0.1 F

C27

CLKout0

142-0701-851

CLKout1

142-0701-851

GND

0.1 F

C31

0.1 F

C30

0.1 F

C29

GND

CLKout4

142-0701-851

CLKout3

142-0701-851

CLKout2

142-0701-851

GND

VCC

910

uWire

HEADER_2X5

DNP

GND

10 F

1 F

0.01 F

GND

VCC

SEL1

SEL0

C1_P

C1_N

C1in_N

C1in_P

R28

GND

VCCO

GND

15k

R303

DNP 15k

R304

DNP 15k

R305

DNP

4.7k

R302

DNP

4.7k

R301

DNP

GND

100

DNP

100

DNP

100

DNP

100

DNP

C0in_N

C0in_P

GND

R35

R36

R37

GND

A6S-4104-H

R29

R31

R32

0.01 F

C11

DNP

0.1 F

C10

DNP

0.01 F

C12

DNP

0.1 F

C13

DNP

0.01 F

C17

DNP

0.1 F

C16

DNP

0.01 F

C18

DNP

0.1 F

C19

DNP

0.01 F

C15

DNP 0.1 F

C14

DNP

R30

4.7k

R300

DNP

Note: Parts with Designators greater than or equal to 300 are on the bottom side.

100pF

C37

GND

100pF

C38

GND

100pF

C39

100pF

C40

GND

100pF

C41

GND

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Schematics

SNLU098A–March 2012–Revised July 2019

LMK00101 User’s Guide

7 Schematics

Figure 2. Schematic Sheet 1

2 2

LMK00101 Power Supply

3/20/2012

LMK0101ENG_Sheet3.SchDoc

Sheet Title:

Size: Schematic:

Mod. Date:

File:

Rev:

Sheet: of

Texas Instruments and/or its licensors do not warrant the accur acy or completeness of this

speciﬁcation or any information contained therein. Texas Instr uments and/or its licensors do not

warrant that this design will meet the speciﬁcations, will be suitable for your application or ﬁt for

any particular purpose, or will operate in an implementation. T

exas Instruments and/or its

licensors do not warrant that the design is production worthy. You should completely validate

and test your design implementation to conﬁrm the system funct ionality for your application. http://www.ti.com

Contact: http://www.national.com/support

LMK00101 EVK

Project:

Designed for: Public Release

870600680 X1

Assemb ly Va riant: Customer

600680 001

551

PCB Part Number: REV A

Vdd

142-0701-851

Vdd_TB

TERMBLOCK_2

DNP

R39

R42

DNP

VccIN

ADJ 6

GND 3

DAP

OUT 5

BYP 1

LP3878SD-ADJ/NOPB

DNP

10 F

1 F

0.01 F

GND

VCC

10 F

C304

DNP 10 F

C306

DNP

2200pF

C305

DNP

0.01 F

C307

DNP

51k

R310

DNP 2.00k

R312

DNP

866

R311

DNP

GND

GND TP_VCC_LDO

DNP

TPVcc

DNP

TPVccIN

DNP

R41

DNP

R309

DNP

ADJ 6

GND 3

DAP

OUT 5

BYP 1

LP3878SD-ADJ/NOPB

DNP

10 F

C300

DNP 10 F

C302

DNP

2200pF

C301

DNP

0.01 F

C303

DNP

51k

R306

DNP 1.30k

R308

DNP

866

R307

DNP

GND

TP_VCCO_LDO

DNP

R40

DNP

1 F

VCCO

10 F

R43

DNP

VddCLKout

142-0701-851

R38

GND

TPVcco

DNP

SO1

0.375" Standoﬀ

SO2

0.375" Standoﬀ

SO3

0.375" Standoﬀ

SO4

0.375" Standoﬀ

0.1 F

GND

VddCLKout_TB

TERMBLOCK_2

DNP

SO5

0.375" Standoﬀ

SO6

0.375" Standoﬀ

Schematics

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LMK00101 User’s Guide

Figure 3. Schematic Sheet 2

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PCB Layout

SNLU098A–March 2012–Revised July 2019

LMK00101 User’s Guide

8 PCB Layout

Figure 4. PCB Top

PCB Layout

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LMK00101 User’s Guide

Figure 5. Bottom Side (Layer Inverted, Not to Scale)

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Bill of Materials

SNLU098A–March 2012–Revised July 2019

LMK00101 User’s Guide

9 Bill of Materials

Table 6. Bill of Materials

Item DESCRIPTION QTY DESIGNATOR MANUFACTURER PART NUMBER

1CAP, CERM, 10uF, 10V,

+/-10%, X5R, 0805 3 C1, C4, C7 MuRata GRM21BR61A106KE19L

2CAP, CERM, 1uF, 16V, +/-

10%, X7R, 0603 3 C2, C5, C8 TDK C1608X7R1C105K

3CAP, CERM, 0.01uF,

100V, +/-5%, X7R, 0603 2 C3, C9 Kemet C0603C103J1RACTU

4CAP, CERM, 0.1uF, 16V,

+80/-20%, Y5V, 0603 1 C6 TDK C1608Y5V1C104Z

5RES, 0 ohm, 5%, 0.1W,

0603 11 C20, C21, C22, C23, R15,

R17, R35, R36, R37, R38,

R39 Vishay-Dale CRCW06030000Z0EA

6CAP, CERM, 0.1uF, 16V,

+/-10%, X7R, 0603 15 C26, C27, C28, C29, C30,

C31, C32, C33, C34, C35,

C36, R3, R4, R10, R11 TDK C1608X7R1C104K

7CAP, CERM, 100pF, 25V,

+/-5%, C0G/NP0, 0402 5 C37, C38, C39, C40, C41 MuRata GRM1555C1E101JA01D

8Connector, SMT, End

launch SMA 50 ohm 17

CLKin0, CLKin0*, CLKin1,

CLKin1*, CLKout0,

CLKout1, CLKout2,

CLKout3, CLKout4,

CLKout5, CLKout6,

CLKout7, CLKout8,

CLKout9, OSCin, Vdd,

VddCLKout

Emerson Network Power

Connectivity 142-0701-851

9RES, 100 ohm, 5%, 0.1W,

0603 2 R5, R14 Vishay-Dale CRCW0603100RJNEA

10 RES, 51 ohm, 5%, 0.1W,

0603 1 R16 Vishay-Dale CRCW060351R0JNEA

11 RES, 0 ohm, 5%, 0.063W,

0402 5 R28, R29, R30, R31, R32 Vishay-Dale CRCW04020000Z0ED

12 DIP Switch, 4 position slide

actuator, SPST, SMD 1 S1 Omron Electronic

Components A6S-4104-H

13 0.375" Standoff 6 SO1, SO2, SO3, SO4,

SO5, SO6

14 LMK00101 1 U1 Texas Instruments LMK00101

15 CAP, CERM, 0.1uF, 16V,

+80/-20%, Y5V, 0402 0 C10, C13, C14, C16, C19 TDK C1005Y5V1C104Z

16 CAP, CERM, 0.01uF, 25V,

+/-10%, X7R, 0402 0 C11, C12, C15, C17, C18 TDK C1005X7R1E103K

17 CAP, CERM, 5.6pF, 50V,

+/-5%, C0G/NP0, 0603 0 C24, C25 AVX 06035A5R6CAT2A

18 CAP, CERM, 10uF, 10V,

+/-10%, X5R, 0805 0 C300, C302, C304, C306 MuRata GRM21BR61A106KE19L

19 CAP, CERM, 2200pF,

100V, +/-5%, X7R, 0603 0 C301, C305 AVX 06031C222JAT2A

20 CAP, CERM, 0.01uF, 25V,

+/-5%, C0G/NP0, 0603 0 C303, C307 TDK C1608C0G1E103J

21 RES, 100 ohm, 5%, 0.1W,

0603 0 R1, R2, R8, R9 Vishay-Dale CRCW0603100RJNEA

22 RES, 51 ohm, 5%, 0.1W,

0603 0R6, R7, R12, R13, R18,

R19, R20, R21, R22, R23,

R24, R25, R26, R27 Vishay-Dale CRCW060351R0JNEA

23 RES, 0 ohm, 5%, 0.1W,

0603 0R33, R34, R40, R41, R42,

R43, R309 Vishay-Dale CRCW06030000Z0EA

24 RES, 4.7k ohm, 5%, 0.1W,

0603 0 R300, R301, R302 Vishay-Dale CRCW06034K70JNEA

Bill of Materials

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LMK00101 User’s Guide

Table 6. Bill of Materials (continued)

Item DESCRIPTION QTY DESIGNATOR MANUFACTURER PART NUMBER

25 RES, 15k ohm, 5%, 0.1W,

0603 0 R303, R304, R305 Vishay-Dale CRCW060315K0JNEA

26 RES, 51k ohm, 5%, 0.1W,

0603 0 R306, R310 Vishay-Dale CRCW060351K0JNEA

27 RES, 866 ohm, 1%, 0.1W,

0603 0 R307, R311 Vishay-Dale CRCW0603866RFKEA

28 RES,1.30k ohm, 1%, 0.1W,

0603 0 R308 Vishay-Dale CRCW06031K30FKEA

29 RES, 2.00k ohm, 1%,

0.1W, 0603 0 R312 Vishay-Dale CRCW06032K00FKEA

30 Testpoint 0 TP_VCC_LDO,

TP_VCCO_LDO, TPVcc,

TPVccIN, TPVcco

Micropower800mA Low

Noise "Ceramic Stable"

Adjustable Voltage

Regulator for 1V to 5V

Applications, 8-pin LLP,

Pb-Free

0 U2, U3 Texas Instruments LP3878SD-ADJ/NOPB

32 0 uWire, Vdd_TB,

VddCLKout_TB

33 Crystal, xxxMHz, xxpF,

[MountType] 0 Y1

34 Crystal, Citizen CS325,

XXMHz 0 Y2

Ce manuel convient aux modèles suivants

Table des matières

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