Texas Instruments LMX2594EVM Manuel utilisateur

SNAU210A–March 2017–Revised March 2020

LMX2594 EVM Instructions – 15-GHz Wideband Low Noise PLL With

Integrated VCO

User's Guide

SNAU210A–March 2017–Revised March 2020

LMX2594 EVM Instructions – 15-GHz Wideband Low Noise

PLL With Integrated VCO

This Evaluation Module is for the LMX2594, which is the first PLL with integrated VCO in industry to get

fundamental VCO output up to 15 GHz. The industry leading PLL FOM is –236 dBc/Hz with 1/f of –129

dBc/Hz. This device supports the JESD204B standard (as in the LMX2594 can generate or repeat the

SYSREF signal), and is designed for clock high-speed data converters. The integrated jitter from the EVM

measurements is less than 50 fs at 9-GHz carrier frequency. By providing a SYNC signal, the user can

synchronize the output phase across multiple LMX2594 devices. The LMX2594 can also generate a

frequency ramp as demonstrated in this evaluation module. With an on-board oscillator, the setup process

only requires a 3.3-V power supply and a Reference Pro module (included for SPI Programming

interface). The software is simple with an intuitive and user-friendly GUI.

Figure 1. LMX2594EVM

Contents

1 Evaluation Board Setup .................................................................................................... 3

2 EVM Description ............................................................................................................. 3

3 Bringing LMX2594 to a Lock State........................................................................................ 5

4 Loop Filter Configuration.................................................................................................... 5

5 Key Results to Expect....................................................................................................... 6

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LMX2594 EVM Instructions – 15-GHz Wideband Low Noise PLL With

Integrated VCO

Appendix A Schematic............................................................................................................ 7

Appendix B Bill of Materials...................................................................................................... 8

Appendix C Board Layers Stack-Up ............................................................................................ 9

Appendix D Changing Reference Oscillator and Setup..................................................................... 11

Appendix E Connecting Reference Pro....................................................................................... 12

Appendix F Ramping Feature ................................................................................................. 14

Appendix G SYSREF Feature ................................................................................................. 15

Appendix H Enabling Onboard DC-DC Buck Converter (TPS62150)..................................................... 16

Trademarks

PLLATINUM is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

Diff. RF

Output A

Diff. RF

Output B

LMX2594

Reference input

SE or Diff

Power supply

3.3 Volt

SYNC

SYSREF

Lock

indicator

LED

1: SPI read block

2: Lock indicator

Upper position = ON

Lower position = OFF

Loop filter

components

(*_LF)

Serial Interface Pin-out

2 4 6 8 10

13579

(Optional)

Add a XO here

3.3 V supply

RFoutAP

Connect to

an analyzer

50 

termination

Connect to

a PC

Clean 100 MHz

clock source

Reference Pro

board LMX2594EVM

board

Connect both

serial interface

together

OSCinM can be left

open

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Evaluation Board Setup

SNAU210A–March 2017–Revised March 2020

LMX2594 EVM Instructions – 15-GHz Wideband Low Noise PLL With

Integrated VCO

1 Evaluation Board Setup

Figure 2. LMX2594EVM Setup

1. Power:

a. Set power supply to 3.3 V with 600-mA current limit and connect to VCC SMA.

2. Input Signal:

a. Connect a clean 100-MHz clock source to the OSCinP SMA.

3. Programming Interface:

• Reference Pro will provide SPI interface to program LMX2594.

a. Connect USB cable from laptop or PC to USB port in Reference Pro. This provides power to

Reference Pro board and communication with TICS GUI.

b. Connect 10 pin ribbon cable from Reference Pro to LMX2594EVM as shown above.

4. Output:

a. Connect RFoutAM or RFoutAP to a phase noise analyzer. Connect a 50-Ωresistor on the unused

pin if you are using a single-ended output. Use a balun if you are using a differential output.

2 EVM Description

The LMX2594 is populated on a 4-layer PCB. This brief description should help you use the EVM:

Figure 3. LMX2594EVM Description

EVM Description

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LMX2594 EVM Instructions – 15-GHz Wideband Low Noise PLL With

Integrated VCO

The serial interface pin description is as follow:

Table 1. Serial Interface Connector Description

NO. NAME

1 RAMPDIR and CE (Choose with Resistors on Board)

2 CSB

3 MUXout

4 SDI

5 Not Used

6 GND

7 RampCLK

8 SCK

9 SysRefReq

10 SYNC

2.1 Installing the Software

1. Download TICS Pro from the TI Website at www.ti.com/tool/TICSPRO-SW.

2. Install the software by following the wizard.

3. Search for the LMX2594. In the menu bar, search Select Device →PLL + VCO →LMX2594

Figure 4. Search for LMX2594 on TICS Pro

4. You are now ready to use this software. Verify that you can communicate with Reference Pro. Select

Interface under USB communications.

Figure 5. USB Communications on TICS Pro

5. Click on Identify and you will see the LED (MSP430 Supplied) blinks on Reference Pro.

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Bringing LMX2594 to a Lock State

SNAU210A–March 2017–Revised March 2020

LMX2594 EVM Instructions – 15-GHz Wideband Low Noise PLL With

Integrated VCO

Figure 6. USB Communication Between TICS Pro and Reference Pro

3 Bringing LMX2594 to a Lock State

1. Load the default mode by clicking on Default configuration →Default Mode xxxx-xx-xx.

2. From the menu bar, select USB communications →Write All Registers, to write all the registers to

LMX2594.

Figure 7. TICS Pro GUI LMX2594 Default Configuration

4 Loop Filter Configuration

The parameters for the loop filters are:

Table 2. Loop Filter Configuration

PARAMETER VALUE

VCO Gain 132 MHz/V

Loop Bandwidth 285 kHz

Phase Margin 65 deg

C1_LF 390 pF

C2_LF 68 nF

C3_LF Open

C4_LF 1800 pF

Key Results to Expect

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LMX2594 EVM Instructions – 15-GHz Wideband Low Noise PLL With

Integrated VCO

Table 2. Loop Filter Configuration (continued)

PARAMETER VALUE

R2 68 Ω

R3_LF 0 Ω

R4_LF 18 Ω

Effective Charge Pump Gain 15 mA

Phase Detector Frequency (MHz) 200 MHz

VCO Frequency Designed for 15 GHz, but works

over the whole frequency range

Figure 8. Loop Filter Configuration

For detailed design and simulation of TI's PLLATINUM™ integrated circuits, see the PLLatinum Sim Tool.

For application notes, blogs, or videos on TI PLL products, see http://www.ti.com/pll.

5 Key Results to Expect

Figure 9. Phase Noise Plot at 14-GHz Output Frequency

This assumes that the input reference is very clean, such as a 100-MHz Wenzel oscillator. A signal

generator is NOT sufficiently clean.

SNAU210A–March 2017–Revised March 2020

Schematic

Appendix A

SNAU210A–March 2017–Revised March 2020

Schematic

Figure 10. Schematic

8SNAU210A–March 2017–Revised March 2020

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Bill of Materials

Appendix B

SNAU210A–March 2017–Revised March 2020

Bill of Materials

Table 3. Bill of Materials

DESIGNATOR DESCRIPTION MANUFACTURER PART NUMBER QUANTITY

C1, C3, C9, C14, C15, C17, C30 CAP, CERM, 0.1 µF, 16 V, ±5%, X7R,

0603 AVX 0603YC104JAT2A 7

C1_LF CAP, CERM, 390 pF, 50 V, ±5%,

C0G/NP0, 0603 Kemet C0603C391J5GACTU 1

C2, C4, C8, C16 CAP, CERM, 10 µF, 10 V, ±10%, X5R,

0805 Kemet C0805C106K8PACTU 4

C2_LF CAP, CERM, 0.068 µF, 50 V, ±10%, X7R,

0603 MuRata GRM188R71H683KA93D 1

C4_LF CAP, CERM, 1800 pF, 50 V, ±5%,

C0G/NP0, 0603 MuRata GRM1885C1H182JA01D 1

C5, C6, C7, C10, C11, C12 CAP, CERM, 0.01 µF, 16 V, ±10%, X7R,

0402 AT Ceramics 520L103KT16T 6

C18, C23, C24, C26, C27, C28, C29 CAP, CERM, 1 µF, 16 V, ±10%, X7R, 0603 TDK C1608X7R1C105K080AC 7

C19, C20, C21, C22, C25 CAP, CERM, 10 µF, 10 V, ±20%, X5R,

0603 TDK C1608X5R1A106M080AC 5

CE_TP, CSB_TP, GND_TP, MUXout_TP,

RampCLK_TP, RampDIR_TP, SCK_TP,

SDI_TP, SYNC_TP, SysRefReq_TP,

Vcc_TP, VccRF_TP, Vtune_TP

Test Point, Compact, White, TH Keystone 5007 13

Cin_0 CAP, CERM, 10 µF, 25 V, ±10%, X5R,

0805 MuRata GRM219R61E106KA12D 1

Cout0 CAP, CERM, 22 µF, 16 V, ±10%, X5R,

0805 TDK C2012X5R1C226K125AC 1

Css CAP, CERM, 3300 pF, 50 V, ±5%,

C0G/NP0, 0603 MuRata GRM1885C1H332JA01D 1

D1 LED, Green, SMD Lite-On LTST-C190GKT 1

L1, L2 Inductor, Multilayer, Air Core, 18 nH, 0.3 A,

0.36 Ω, SMD MuRata LQG15HS18NJ02D 2

L1_TPS Inductor, Shielded, Composite, 2.2 µH, 3.7

A, 0.02 Ω, SMD Coilcraft XFL4020-222MEB 1

MUXout_SW Switch, SPST, Slide, Off-On, 2 Pos, 0.1 A,

20 V, SMD CTS Electrocomponents 219-2MST 1

OSCinM, OSCinP, SYNC, SysRef, Vcc Connector, SMT, End launch SMA 50 ohm Emerson Network Power

Connectivity 142-0701-851 5

R1 RES, 330 Ω, 5%, 0.1 W, 0603 Yageo America RC0603JR-07330RL 1

R2 RES, 100 k, 5%, 0.1 W, 0603 Vishay-Dale CRCW0603100KJNEA 1

R2_LF RES, 68, 5%, 0.1 W, 0603 Vishay-Dale CRCW060368R0JNEA 1

R3_LF, R12, R15, R24, R26, R25, R30,

R31, R34, R35, R36, R41, R42, R43, R44,

R45 RES, 0, 5%, 0.1 W, 0603 Vishay-Dale CRCW06030000Z0EA 16

R4_LF RES, 18, 5%, 0.1 W, 0603 Vishay-Dale CRCW060318R0JNEA 1

R5, R7, R8, R9, R16, R19, R20, R22 RES, 12 kΩ, 5%, 0.1 W, 0603 Vishay-Dale CRCW060312K0JNEA 8

R37, R38, R39, R40 RES, 50, 0.1%, 0.05 W, 0402 Vishay-Dale FC0402E50R0BST1 4

Rfbb1 RES, 180 k, 0.1%, 0.1 W, 0603 Yageo America RT0603BRD07180KL 1

Rfbt1 RES, 562 k, 1%, 0.1 W, 0603 Vishay-Dale CRCW0603562KFKEA 1

RFoutAM, RFoutAP, RFoutBM, RFoutBP JACK, SMA, 50 Ω, Gold, Edge Mount Johnson 142-0771-831 4

U1 Wideband RF Synthesizer Texas Instruments LMX2594RHAR 1

uWire Header (shrouded), 100 mil, 5x2, Gold

plated, SMD FCI 52601-S10-8LF 1

Top layer

RO4003 (Er = 3.38)

16 mil

GND layer

FR4 (Er = 4.6)

Power layer

FR4 (Er = 4.6)

Bottom layer

62 mil

SNAU210A–March 2017–Revised March 2020

Board Layers Stack-Up

Appendix C

SNAU210A–March 2017–Revised March 2020

Board Layers Stack-Up

The top layer is 1-oz. copper.

Figure 11. Board Layer Stack-Up

Figure 12. Top Layer

Appendix C

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Board Layers Stack-Up

Figure 13. GND Layer

Figure 14. Power Layer

Figure 15. Bottom Layer

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